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Diffstat (limited to 'gcc/config/ia64/ia64-modes.def')
| -rw-r--r-- | gcc/config/ia64/ia64-modes.def | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/gcc/config/ia64/ia64-modes.def b/gcc/config/ia64/ia64-modes.def new file mode 100644 index 000000000..a3d04d981 --- /dev/null +++ b/gcc/config/ia64/ia64-modes.def @@ -0,0 +1,86 @@ +/* Definitions of target machine GNU compiler. IA-64 version. + Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. + Contributed by James E. Wilson <wilson@cygnus.com> and + David Mosberger <davidm@hpl.hp.com>. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* IA64 requires both XF and TF modes. + XFmode is __float80 is IEEE extended; TFmode is __float128 + is IEEE quad. Both these modes occupy 16 bytes, but XFmode + only has 80 significant bits. RFmode is __fpreg is IA64 internal + register format with 82 significant bits but otherwise handled like + XFmode. */ + +FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format); +FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format); +FLOAT_MODE (TF, 16, ieee_quad_format); + +/* The above produces: + + mode ILP32 size/align LP64 size/align + XF 16/16 16/16 + TF 16/16 16/16 + + psABI expectations: + + mode ILP32 size/align LP64 size/align + XF 12/4 - + TF - - + + HPUX expectations: + + mode ILP32 size/align LP64 size/align + XF - - + TF 16/8 - + + We fix this up here. */ + +ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX) + ? &ieee_extended_intel_96_format + : &ieee_extended_intel_128_format); +ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16); +ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16); + +ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX) + ? &ieee_extended_intel_96_format + : &ieee_extended_intel_128_format); +ADJUST_BYTESIZE (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16); +ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16); + +ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16); + +/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */ +INT_MODE (OI, 32); + +/* Add any extra modes needed to represent the condition code. + + CCImode is used to mark a single predicate register instead + of a register pair. This is currently only used in reg_raw_mode + so that flow doesn't do something stupid. */ + +CC_MODE (CCI); + +/* Vector modes. */ +VECTOR_MODES (INT, 4); /* V4QI V2HI */ +VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ +VECTOR_MODE (INT, QI, 16); +VECTOR_MODE (INT, HI, 8); +VECTOR_MODE (INT, SI, 4); +VECTOR_MODE (FLOAT, SF, 2); +VECTOR_MODE (FLOAT, SF, 4); + |