From 554fd8c5195424bdbcabf5de30fdc183aba391bd Mon Sep 17 00:00:00 2001
From: upstream source tree <ports@midipix.org>
Date: Sun, 15 Mar 2015 20:14:05 -0400
Subject: obtained gcc-4.6.4.tar.bz2 from upstream website; verified
 gcc-4.6.4.tar.bz2.sig; imported gcc-4.6.4 source tree from verified upstream
 tarball.

downloading a git-generated archive based on the 'upstream' tag
should provide you with a source tree that is binary identical
to the one extracted from the above tarball.

if you have obtained the source via the command 'git clone',
however, do note that line-endings of files in your working
directory might differ from line-endings of the respective
files in the upstream repository.
---
 gcc/testsuite/gcc.target/microblaze/isa/bshift.c   | 53 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/div.c      | 52 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c    | 10 +++
 gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c    | 10 +++
 gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c    | 10 +++
 gcc/testsuite/gcc.target/microblaze/isa/fcvt.c     | 21 +++++
 gcc/testsuite/gcc.target/microblaze/isa/float.c    | 18 +++++
 gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c    | 10 +++
 .../gcc.target/microblaze/isa/mul-bshift-pcmp.c    | 53 +++++++++++++
 .../gcc.target/microblaze/isa/mul-bshift.c         | 53 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/mul.c      | 52 +++++++++++++
 .../gcc.target/microblaze/isa/mulh-bshift-pcmp.c   | 53 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/mulh.c     | 53 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c   | 21 +++++
 gcc/testsuite/gcc.target/microblaze/isa/nofloat.c  | 19 +++++
 gcc/testsuite/gcc.target/microblaze/isa/pcmp.c     | 52 +++++++++++++
 gcc/testsuite/gcc.target/microblaze/isa/vanilla.c  | 89 ++++++++++++++++++++++
 17 files changed, 629 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/bshift.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/div.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fcvt.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/float.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/mul.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/mulh.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/nofloat.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/pcmp.c
 create mode 100644 gcc/testsuite/gcc.target/microblaze/isa/vanilla.c

(limited to 'gcc/testsuite/gcc.target/microblaze/isa')

diff --git a/gcc/testsuite/gcc.target/microblaze/isa/bshift.c b/gcc/testsuite/gcc.target/microblaze/isa/bshift.c
new file mode 100644
index 000000000..64cf1e2e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/bshift.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/div.c b/gcc/testsuite/gcc.target/microblaze/isa/div.c
new file mode 100644
index 000000000..25ee42ce5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/div.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-div" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
new file mode 100644
index 000000000..4041a2413
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 <= f3) 
+        print ("le");
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
new file mode 100644
index 000000000..3902b839d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 < f3) 
+        print ("lt");
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
new file mode 100644
index 000000000..8555974dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 == f3) 
+        print ("eq");
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c b/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c
new file mode 100644
index 000000000..ee057c1b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c
@@ -0,0 +1,21 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-convert" } */
+
+int float_func (float f) 
+{
+  /* { dg-final { scan-assembler "flt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return f;
+}
+
+
+float int_func (int i) 
+{
+  /* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return i;
+}
+
+
+float uint_func (unsigned int i) 
+{
+  /* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return i;
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/float.c b/gcc/testsuite/gcc.target/microblaze/isa/float.c
new file mode 100644
index 000000000..f5ef3186c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/float.c
@@ -0,0 +1,18 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fmul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler "fadd\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler "frsub\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler "fdiv\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 / f3;
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c b/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c
new file mode 100644
index 000000000..4c2466e4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-sqrt" } */
+#include <math.h>
+
+float sqrt_func (float f) 
+{
+  /* { dg-final { scan-assembler "fsqrt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return sqrtf (f);
+}
+
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c
new file mode 100644
index 000000000..ce186314e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c
new file mode 100644
index 000000000..76d174ec7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul.c b/gcc/testsuite/gcc.target/microblaze/isa/mul.c
new file mode 100644
index 000000000..d2a6bec61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/mul.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c
new file mode 100644
index 000000000..a15983af1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare -mxl-multiply-high" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = (long long)l1 * l2;
+
+  /* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    ullp = (unsigned long long)ul1 * ul2;
+
+  /* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = (long long)l1 * ul2;        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mulh.c b/gcc/testsuite/gcc.target/microblaze/isa/mulh.c
new file mode 100644
index 000000000..6e0cc3ac4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/mulh.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul -mxl-multiply-high" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
new file mode 100644
index 000000000..ebfb170ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
@@ -0,0 +1,21 @@
+/* { dg-options "-O3 -mcpu=v6.00.a " } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+    /* { dg-final { scan-assembler-not "fcmp" } } */
+    if (f2 <= f3) 
+        print ("le");
+    else if (f2 == f3) 
+        print ("eq");
+    else if (f2 < f3) 
+        print ("lt");
+    else if (f2 > f3) 
+        print ("gt");
+    else if (f2 >= f3) 
+        print ("ge");
+    else if (f2 != f3) 
+        print ("ne");
+    
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c b/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c
new file mode 100644
index 000000000..647da3cfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -msoft-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler-not "fmul" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler-not "fadd" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler-not "frsub" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler-not "fdiv" } } */
+    f1 = f2 / f3;
+
+}
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c
new file mode 100644
index 000000000..aea795721
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-pattern-compare" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
new file mode 100644
index 000000000..1d6ba807b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
@@ -0,0 +1,89 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mcpu=v6.00.a" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
+
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler-not "fmul" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler-not "fadd" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler-not "frsub" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler-not "fdiv" } } */
+    f1 = f2 / f3;
+
+}
+
+void float_cmp_func () 
+{
+    /* { dg-final { scan-assembler-not "fcmp" } } */
+    if (f2 <= f3) 
+        print ("le");
+    else if (f2 == f3) 
+        print ("eq");
+    else if (f2 < f3) 
+        print ("lt");
+    else if (f2 > f3) 
+        print ("gt");
+    else if (f2 >= f3) 
+        print ("ge");
+    else if (f2 != f3) 
+        print ("ne");
+    
+}
-- 
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