From 554fd8c5195424bdbcabf5de30fdc183aba391bd Mon Sep 17 00:00:00 2001 From: upstream source tree Date: Sun, 15 Mar 2015 20:14:05 -0400 Subject: obtained gcc-4.6.4.tar.bz2 from upstream website; verified gcc-4.6.4.tar.bz2.sig; imported gcc-4.6.4 source tree from verified upstream tarball. downloading a git-generated archive based on the 'upstream' tag should provide you with a source tree that is binary identical to the one extracted from the above tarball. if you have obtained the source via the command 'git clone', however, do note that line-endings of files in your working directory might differ from line-endings of the respective files in the upstream repository. --- gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c (limited to 'gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c') diff --git a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c new file mode 100644 index 000000000..68c4b7ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c @@ -0,0 +1,18 @@ +/* { dg-options "-O2 -mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */ +int bar (int); + +/* Test that code after a branch-likely does not get an unnecessary + cache barrier. */ + +NOMIPS16 void +foo (int n, int *x) +{ + do + n = bar (n * 4 + 1); + while (n); + /* The preceding branch should be a branch likely, with the shift as + its delay slot. We therefore don't need a cache barrier here. */ + x[0] = 0; +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ -- cgit v1.2.3