; Options for the IA-32 and AMD64 ports of the compiler.

; Copyright (C) 2005, 2006, 2007, 2008, 2009,
; 2010, 2011 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

; Bit flags that specify the ISA we are compiling for.
Variable
int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT

;; Definitions to add to the cl_target_option structure
;; -march= processor
TargetSave
unsigned char arch

;; -mtune= processor
TargetSave
unsigned char tune

;; -mfpath=
TargetSave
unsigned char fpmath

;; CPU schedule model
TargetSave
unsigned char schedule

;; branch cost
TargetSave
unsigned char branch_cost

;; which flags were passed by the user
TargetSave
int ix86_isa_flags_explicit

;; which flags were passed by the user
TargetSave
int ix86_target_flags_explicit

;; whether -mtune was not specified
TargetSave
unsigned char tune_defaulted

;; whether -march was specified
TargetSave
unsigned char arch_specified

;; x86 options
m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 16

m80387
Target Report Mask(80387) Save
Use hardware fp

m96bit-long-double
Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 12

maccumulate-outgoing-args
Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
Reserve space for outgoing arguments in the function prologue

malign-double
Target Report Mask(ALIGN_DOUBLE) Save
Align some doubles on dword boundary

malign-functions=
Target RejectNegative Joined Var(ix86_align_funcs_string)
Function starts are aligned to this power of 2

malign-jumps=
Target RejectNegative Joined Var(ix86_align_jumps_string)
Jump targets are aligned to this power of 2

malign-loops=
Target RejectNegative Joined Var(ix86_align_loops_string)
Loop code aligned to this power of 2

malign-stringops
Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
Align destination of the string operations

march=
Target RejectNegative Joined Var(ix86_arch_string)
Generate code for given CPU

masm=
Target RejectNegative Joined Var(ix86_asm_string)
Use given assembler dialect

mbranch-cost=
Target RejectNegative Joined Var(ix86_branch_cost_string)
Branches are this expensive (1-5, arbitrary units)

mlarge-data-threshold=
Target RejectNegative Joined Var(ix86_section_threshold_string)
Data greater than given threshold will go into .ldata section in x86-64 medium model

mcmodel=
Target RejectNegative Joined Var(ix86_cmodel_string)
Use given x86-64 code model

mcpu=
Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)

mfancy-math-387
Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
Generate sin, cos, sqrt for FPU

mforce-drap
Target Report Var(ix86_force_drap)
Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack

mfp-ret-in-387
Target Report Mask(FLOAT_RETURNS) Save
Return values of functions in FPU registers

mfpmath=
Target RejectNegative Joined Var(ix86_fpmath_string)
Generate floating point mathematics using given instruction set

mhard-float
Target RejectNegative Mask(80387) MaskExists Save
Use hardware fp

mieee-fp
Target Report Mask(IEEE_FP) Save
Use IEEE math for fp comparisons

minline-all-stringops
Target Report Mask(INLINE_ALL_STRINGOPS) Save
Inline all known string operations

minline-stringops-dynamically
Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
Inline memset/memcpy string operations, but perform inline version only for small blocks

mintel-syntax
Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
;; Deprecated

mms-bitfields
Target Report Mask(MS_BITFIELD_LAYOUT) Save
Use native (MS) bitfield layout

mno-align-stringops
Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save

mno-fancy-math-387
Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save

mno-push-args
Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save

mno-red-zone
Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save

momit-leaf-frame-pointer
Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
Omit the frame pointer in leaf functions

mpc
Target RejectNegative Report Joined Var(ix87_precision_string)
Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80)

mpreferred-stack-boundary=
Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string)
Attempt to keep stack aligned to this power of 2

mincoming-stack-boundary=
Target RejectNegative Joined Var(ix86_incoming_stack_boundary_string)
Assume incoming stack aligned to this power of 2

mpush-args
Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
Use push instructions to save outgoing arguments

mred-zone
Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
Use red-zone in the x86-64 code

mregparm=
Target RejectNegative Joined Var(ix86_regparm_string)
Number of registers used to pass integer arguments

mrtd
Target Report Mask(RTD) Save
Alternate calling convention

msoft-float
Target InverseMask(80387) Save
Do not use hardware fp

msseregparm
Target RejectNegative Mask(SSEREGPARM) Save
Use SSE register passing conventions for SF and DF mode

mstackrealign
Target Report Var(ix86_force_align_arg_pointer) Init(-1)
Realign stack in prologue

mstack-arg-probe
Target Report Mask(STACK_PROBE) Save
Enable stack probing

mstringop-strategy=
Target RejectNegative Joined Var(ix86_stringop_string)
Chose strategy to generate stringop using

mtls-dialect=
Target RejectNegative Joined Var(ix86_tls_dialect_string)
Use given thread-local storage dialect

mtls-direct-seg-refs
Target Report Mask(TLS_DIRECT_SEG_REFS)
Use direct references against %gs when accessing tls data

mtune=
Target RejectNegative Joined Var(ix86_tune_string)
Schedule code for given CPU

mabi=
Target RejectNegative Joined Var(ix86_abi_string)
Generate code that conforms to the given ABI

mveclibabi=
Target RejectNegative Joined Var(ix86_veclibabi_string)
Vector library ABI to use

mvect8-ret-in-mem
Target Report Mask(VECT8_RETURNS) Save
Return 8-byte vectors in memory

mrecip
Target Report Mask(RECIP) Save
Generate reciprocals instead of divss and sqrtss.

mcld
Target Report Mask(CLD) Save
Generate cld instruction in the function prologue.

mvzeroupper
Target Report Mask(VZEROUPPER) Save
Generate vzeroupper instruction before a transfer of control flow out of
the function.

mdispatch-scheduler
Target RejectNegative Var(flag_dispatch_scheduler)
Do dispatch scheduling if processor is bdver1 and Haifa scheduling
is selected.

mprefer-avx128
Target Report Mask(PREFER_AVX128) SAVE
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.

;; ISA support

m32
Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 32bit i386 code

m64
Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 64bit x86-64 code

mmmx
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
Support MMX built-in functions

m3dnow
Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
Support 3DNow! built-in functions

m3dnowa
Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
Support Athlon 3Dnow! built-in functions

msse
Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
Support MMX and SSE built-in functions and code generation

msse2
Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
Support MMX, SSE and SSE2 built-in functions and code generation

msse3
Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation

mssse3
Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation

msse4.1
Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation

msse4.2
Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation

msse4
Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation

mno-sse4
Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save
Do not support SSE4.1 and SSE4.2 built-in functions and code generation

msse5
Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
;; Deprecated

mavx
Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation

mfma
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation

msse4a
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation

mfma4
Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
Support FMA4 built-in functions and code generation 

mxop
Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
Support XOP built-in functions and code generation 

mlwp
Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
Support LWP built-in functions and code generation 

mabm
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
Support code generation of Advanced Bit Manipulation (ABM) instructions.

mpopcnt
Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
Support code generation of popcnt instruction.

mbmi
Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
Support BMI built-in functions and code generation

mtbm
Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
Support TBM built-in functions and code generation

mcx16
Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
Support code generation of cmpxchg16b instruction.

msahf
Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
Support code generation of sahf instruction in 64bit x86-64 code.

mmovbe
Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
Support code generation of movbe instruction.

mcrc32
Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
Support code generation of crc32 instruction.

maes
Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
Support AES built-in functions and code generation

mpclmul
Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
Support PCLMUL built-in functions and code generation

msse2avx
Target Report Var(ix86_sse2avx)
Encode SSE instructions with VEX prefix

mfsgsbase
Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
Support FSGSBASE built-in functions and code generation

mrdrnd
Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
Support RDRND built-in functions and code generation

mf16c
Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
Support F16C built-in functions and code generation

mfentry
Target Report Var(flag_fentry) Init(-1)
Emit profiling counter call at function entry before prologue.

m8bit-idiv
Target Report Mask(USE_8BIT_IDIV) Save
Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check

mavx256-split-unaligned-load
Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
Split 32-byte AVX unaligned load

mavx256-split-unaligned-store
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
Split 32-byte AVX unaligned store