clean: clean-gen clean-gen: rm -f gen.tag rm -f $(GEN_IR_SRCS) rm -f $(GEN_IR_HEADERS) rm -f $(GEN_EMITTER_SRCS) rm -f $(GEN_EMITTER_HEADERS) rm -f $(GEN_OPCODES_SRCS) rm -f $(GEN_OPCODES_HEADERS) rm -f $(GEN_REGALLOC_SRCS) rm -f $(GEN_REGALLOC_HEADERS) rm -f $(GEN_BE_DIR_ARM)/emitter.tag rm -f $(GEN_BE_DIR_AMD64)/emitter.tag rm -f $(GEN_BE_DIR_IA32)/emitter.tag rm -f $(GEN_BE_DIR_SPARC)/emitter.tag rm -f $(GEN_BE_DIR_TEMPLATE)/emitter.tag rm -f $(GEN_BE_DIR_ARM)/opcodes.tag rm -f $(GEN_BE_DIR_AMD64)/opcodes.tag rm -f $(GEN_BE_DIR_IA32)/opcodes.tag rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag rm -f $(GEN_BE_DIR_ARM)/regalloc.tag rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag rm -f $(GEN_BE_DIR_IA32)/regalloc.tag rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag GEN_ALL = $(GEN_IR_SRCS) \ $(GEN_IR_HEADERS) \ $(GEN_EMITTER_SRCS) \ $(GEN_EMITTER_HEADERS) \ $(GEN_OPCODES_SRCS) \ $(GEN_OPCODES_HEADERS) \ $(GEN_REGALLOC_SRCS) \ $(GEN_REGALLOC_HEADERS) \ # build/gen/ir/be GEN_BE_DIR_ARM = build/gen/ir/be/arm GEN_BE_DIR_AMD64 = build/gen/ir/be/amd64 GEN_BE_DIR_IA32 = build/gen/ir/be/ia32 GEN_BE_DIR_SPARC = build/gen/ir/be/sparc GEN_BE_DIR_TEMPLATE = build/gen/ir/be/TEMPLATE GEN_SPEC_ARM = $(SOURCE_DIR)/ir/be/arm/arm_spec.pl GEN_SPEC_AMD64 = $(SOURCE_DIR)/ir/be/amd64/amd64_spec.pl GEN_SPEC_IA32 = $(SOURCE_DIR)/ir/be/ia32/ia32_spec.pl GEN_SPEC_SPARC = $(SOURCE_DIR)/ir/be/sparc/sparc_spec.pl GEN_SPEC_TEMPLATE = $(SOURCE_DIR)/ir/be/TEMPLATE/TEMPLATE_spec.pl # gen-ir GEN_IR_TOOL = $(SOURCE_DIR)/scripts/gen_ir.py GEN_IR_SPEC = $(SOURCE_DIR)/scripts/ir_spec.py build/gen/ir/ir/%.c: $(SOURCE_DIR)/scripts/templates/%.c \ $(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag $(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@ build/gen/ir/ir/%.h: $(SOURCE_DIR)/scripts/templates/%.h \ $(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag $(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@ build/gen/include/libfirm/nodes.h: $(SOURCE_DIR)/scripts/templates/nodes.h \ $(GEN_IR_TOOL) $(GEN_IR_SPEC) tree.tag $(GEN_IR_TOOL) $(GEN_IR_SPEC) $< > $@ # gen-emitter GEN_EMITTER_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_emitter.pl $(GEN_BE_DIR_ARM)/emitter.tag: $(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) tree.tag $(GEN_EMITTER_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM) touch $@ $(GEN_BE_DIR_AMD64)/emitter.tag: $(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) tree.tag $(GEN_EMITTER_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64) touch $@ $(GEN_BE_DIR_IA32)/emitter.tag: $(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) tree.tag $(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32) touch $@ $(GEN_BE_DIR_SPARC)/emitter.tag: $(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) tree.tag $(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC) touch $@ $(GEN_BE_DIR_TEMPLATE)/emitter.tag: $(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag $(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE) touch $@ $(GEN_BE_DIR_ARM)/gen_arm_emitter.c: $(GEN_BE_DIR_ARM)/emitter.tag $(GEN_BE_DIR_ARM)/gen_arm_emitter.h: $(GEN_BE_DIR_ARM)/emitter.tag $(GEN_BE_DIR_AMD64)/gen_amd64_emitter.c: $(GEN_BE_DIR_AMD64)/emitter.tag $(GEN_BE_DIR_AMD64)/gen_amd64_emitter.h: $(GEN_BE_DIR_AMD64)/emitter.tag $(GEN_BE_DIR_IA32)/gen_ia32_emitter.c: $(GEN_BE_DIR_IA32)/emitter.tag $(GEN_BE_DIR_IA32)/gen_ia32_emitter.h: $(GEN_BE_DIR_IA32)/emitter.tag $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.c: $(GEN_BE_DIR_SPARC)/emitter.tag $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.h: $(GEN_BE_DIR_SPARC)/emitter.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.c: $(GEN_BE_DIR_TEMPLATE)/emitter.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.h: $(GEN_BE_DIR_TEMPLATE)/emitter.tag # gen-opcodes GEN_OPCODES_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_new_opcodes.pl $(GEN_BE_DIR_ARM)/opcodes.tag: $(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) tree.tag $(GEN_OPCODES_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM) touch $@ $(GEN_BE_DIR_AMD64)/opcodes.tag: $(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) tree.tag $(GEN_OPCODES_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64) touch $@ $(GEN_BE_DIR_IA32)/opcodes.tag: $(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) tree.tag $(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32) touch $@ $(GEN_BE_DIR_SPARC)/opcodes.tag: $(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) tree.tag $(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC) touch $@ $(GEN_BE_DIR_TEMPLATE)/opcodes.tag: $(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag $(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE) touch $@ $(GEN_BE_DIR_ARM)/gen_arm_new_nodes.c: $(GEN_BE_DIR_ARM)/opcodes.tag $(GEN_BE_DIR_ARM)/gen_arm_new_nodes.h: $(GEN_BE_DIR_ARM)/opcodes.tag $(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.c: $(GEN_BE_DIR_AMD64)/opcodes.tag $(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.h: $(GEN_BE_DIR_AMD64)/opcodes.tag $(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.c: $(GEN_BE_DIR_IA32)/opcodes.tag $(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.h: $(GEN_BE_DIR_IA32)/opcodes.tag $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.c: $(GEN_BE_DIR_SPARC)/opcodes.tag $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.h: $(GEN_BE_DIR_SPARC)/opcodes.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.c: $(GEN_BE_DIR_TEMPLATE)/opcodes.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.h: $(GEN_BE_DIR_TEMPLATE)/opcodes.tag # gen-regalloc GEN_REGALLOC_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_regalloc_if.pl $(GEN_BE_DIR_ARM)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) tree.tag $(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM) touch $@ $(GEN_BE_DIR_AMD64)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) tree.tag $(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64) touch $@ $(GEN_BE_DIR_IA32)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) tree.tag $(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32) touch $@ $(GEN_BE_DIR_SPARC)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) tree.tag $(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC) touch $@ $(GEN_BE_DIR_TEMPLATE)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag $(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE) touch $@ $(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.c: $(GEN_BE_DIR_ARM)/regalloc.tag $(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.h: $(GEN_BE_DIR_ARM)/regalloc.tag $(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.c: $(GEN_BE_DIR_AMD64)/regalloc.tag $(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.h: $(GEN_BE_DIR_AMD64)/regalloc.tag $(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.c: $(GEN_BE_DIR_IA32)/regalloc.tag $(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.h: $(GEN_BE_DIR_IA32)/regalloc.tag $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c: $(GEN_BE_DIR_SPARC)/regalloc.tag $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h: $(GEN_BE_DIR_SPARC)/regalloc.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.c: $(GEN_BE_DIR_TEMPLATE)/regalloc.tag $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.h: $(GEN_BE_DIR_TEMPLATE)/regalloc.tag # gen-all gen-ir: $(GEN_IR_SRCS) $(GEN_IR_HEADERS) gen-emitter: $(GEN_EMITTER_SRCS) $(GEN_EMITTER_HEADERS) gen-opcodes: $(GEN_OPCODES_SRCS) $(GEN_OPCODES_HEADERS) gen-regalloc: $(GEN_REGALLOC_SRCS) $(GEN_REGALLOC_HEADERS) gen-all: gen-ir gen-emitter gen-opcodes gen-regalloc gen.tag: $(GEN_ALL) touch gen.tag gen: gen.tag .PHONY: clean-gen \ gen gen-all \ gen-ir gen-emitter gen-opcodes gen-regalloc