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authorupstream source tree <ports@midipix.org>2015-03-15 20:14:05 -0400
committerupstream source tree <ports@midipix.org>2015-03-15 20:14:05 -0400
commit554fd8c5195424bdbcabf5de30fdc183aba391bd (patch)
tree976dc5ab7fddf506dadce60ae936f43f58787092 /gcc/testsuite/gcc.c-torture/compile/20040109-1.c
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Diffstat (limited to 'gcc/testsuite/gcc.c-torture/compile/20040109-1.c')
-rw-r--r--gcc/testsuite/gcc.c-torture/compile/20040109-1.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.c-torture/compile/20040109-1.c b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c
new file mode 100644
index 000000000..028bd17c0
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c
@@ -0,0 +1,25 @@
+/* PR target/13380.
+ On m32r, the condition code register, (reg:SI 17), was replaced with
+ a pseudo reg, which would cause an unrecognized insn. */
+
+void
+foo (unsigned int a, unsigned int b)
+{
+ if (a > b)
+ {
+ while (a)
+ {
+ switch (b)
+ {
+ default:
+ a = 0;
+ case 2:
+ a = 0;
+ case 1:
+ a = 0;
+ case 0:
+ ;
+ }
+ }
+ }
+}