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author | upstream source tree <ports@midipix.org> | 2015-03-15 20:14:05 -0400 |
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committer | upstream source tree <ports@midipix.org> | 2015-03-15 20:14:05 -0400 |
commit | 554fd8c5195424bdbcabf5de30fdc183aba391bd (patch) | |
tree | 976dc5ab7fddf506dadce60ae936f43f58787092 /gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c | |
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Diffstat (limited to 'gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c')
-rw-r--r-- | gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c new file mode 100644 index 000000000..68c4b7ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c @@ -0,0 +1,18 @@ +/* { dg-options "-O2 -mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */ +int bar (int); + +/* Test that code after a branch-likely does not get an unnecessary + cache barrier. */ + +NOMIPS16 void +foo (int n, int *x) +{ + do + n = bar (n * 4 + 1); + while (n); + /* The preceding branch should be a branch likely, with the shift as + its delay slot. We therefore don't need a cache barrier here. */ + x[0] = 0; +} + +/* { dg-final { scan-assembler-not "\tcache\t" } } */ |