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| author | upstream source tree <ports@midipix.org> | 2015-03-15 20:14:05 -0400 |
|---|---|---|
| committer | upstream source tree <ports@midipix.org> | 2015-03-15 20:14:05 -0400 |
| commit | 554fd8c5195424bdbcabf5de30fdc183aba391bd (patch) | |
| tree | 976dc5ab7fddf506dadce60ae936f43f58787092 /gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c | |
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Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c new file mode 100644 index 000000000..375241ec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ +/* This used to ICE as the peephole was not checking to see + if the register is a floating point one (I think this cannot + happen in real life except in this example). */ + +register volatile double t1 __asm__("r14"); +register volatile double t2 __asm__("r15"); +register volatile double t3 __asm__("r16"), t4 __asm__("r17"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} + |