obtained gcc-4.6.4.tar.bz2 from upstream website;upstream

verified gcc-4.6.4.tar.bz2.sig;
imported gcc-4.6.4 source tree from verified upstream tarball.

downloading a git-generated archive based on the 'upstream' tag
should provide you with a source tree that is binary identical
to the one extracted from the above tarball.

if you have obtained the source via the command 'git clone',
however, do note that line-endings of files in your working
directory might differ from line-endings of the respective
files in the upstream repository.

72 files changed, 2413 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/sparc/20001013-1.c b/gcc/testsuite/gcc.target/sparc/20001013-1.c
new file mode 100644
index 000000000..891ccab0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/20001013-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int l;
+
+int baz (double x)
+{
+  return l == 0;
+}
+
+double bar (double x)
+{
+  return 1.0;
+}
+
+double foo (double x)
+{
+  if (l == -1 || baz (x)) return x;
+  if (x < 0.0)
+    return bar (x);
+  else
+    return 0.0;
+}
+
+union {
+  double d;
+  long long l;
+} x = { l: 0x7ff8000000000000LL }, y;
+
+main ()
+{
+  unsigned int fsr = 0;
+  __asm __volatile ("ld %0, %%fsr" : : "m" (fsr));
+  y.d = foo (x.d);
+  __asm __volatile ("st %%fsr, %0" : "=m" (fsr));
+  if (x.l != y.l || (fsr & 0x3ff))
+    abort ();
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/20001101-1.c b/gcc/testsuite/gcc.target/sparc/20001101-1.c
new file mode 100644
index 000000000..ec67e115f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/20001101-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+    }
+  if (!h)
+    {
+      for (g = 0; g <= 10; g++)
+        for (h = 0; h <= 10; h++)
+          e += d [10 + g - h];
+      goto l;
+    }
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/20001102-1.c b/gcc/testsuite/gcc.target/sparc/20001102-1.c
new file mode 100644
index 000000000..b4ce8a0e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/20001102-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+      goto l;
+    }
+
+  asm volatile ("" : : :
+		"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+		"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+		"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+		"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/20020116-2.c b/gcc/testsuite/gcc.target/sparc/20020116-2.c
new file mode 100644
index 000000000..828ffff26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/20020116-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=supersparc" } */
+
+/* This testcase ICEd on sparc64 because -mcpu=supersparc and implicit
+   -m64 resulted in MASK_V8 and MASK_V9 to be set at the same time.  */
+
+void bar (long *x, long *y);
+
+void foo (int x, long *y, long *z)
+{
+  int i;
+
+  for (i = x - 1; i >= 0; i--)
+    {
+      bar (z + i * 3 + 1, y);
+      bar (z + i * 3 + 2, y);
+    }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/20020416-1.c b/gcc/testsuite/gcc.target/sparc/20020416-1.c
new file mode 100644
index 000000000..05f0ee655
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/20020416-1.c
@@ -0,0 +1,15 @@
+/* PR bootstrap/6315 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mhard-quad-float" } */
+
+void bar (const char *, ...);
+
+void
+foo (const char *x, long double y, int z)
+{
+  if (z >= 0)
+    bar (x, z, y);
+  else
+    bar (x, y);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/align.c b/gcc/testsuite/gcc.target/sparc/align.c
new file mode 100644
index 000000000..804ca9397
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/align.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (vec16 a, vec16 b) {
+  return __builtin_vis_faligndatav4hi (a, b);
+}
+
+vec32 foo2 (vec32 a, vec32 b) {
+  return __builtin_vis_faligndatav2si (a, b);
+}
+
+vec8 foo3 (vec8 a, vec8 b) {
+  return __builtin_vis_faligndatav8qi (a, b);
+}
+
+int64_t foo4 (int64_t a, int64_t b) {
+  return __builtin_vis_faligndatadi (a, b);
+}
+
+unsigned char * foo5 (unsigned char *data) {
+  return __builtin_vis_alignaddr (data, 0);
+}
+
+/* { dg-final { scan-assembler-times "faligndata" 4 } } */
+/* { dg-final { scan-assembler "alignaddr.*%g0" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/cas64.c b/gcc/testsuite/gcc.target/sparc/cas64.c
new file mode 100644
index 000000000..ed27cd7cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/cas64.c
@@ -0,0 +1,15 @@
+/* PR target/49660 */
+
+/* { dg-do compile { target sparc*-*-solaris2.* } } */
+
+#include <stdint.h>
+
+extern int64_t *val, old, new;
+
+int
+cas64 (void)
+{
+  return __sync_bool_compare_and_swap (val, old, new);
+}
+
+/* { dg-final { scan-assembler-not "compare_and_swap_8" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/combined-1.c b/gcc/testsuite/gcc.target/sparc/combined-1.c
new file mode 100644
index 000000000..5f19db3b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/combined-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec16 fun16(vec16 a, vec16 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32(vec32 a, vec32 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+/* This should be transformed into ~b & a.  */
+vec16 fun16b(vec16 a, vec16 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32b(vec32 a, vec32 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 4 } } */
+/* { dg-final { scan-assembler-times "for\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpadd" 4 } } */
+/* { dg-final { scan-assembler-times "fxor\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpsub" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/combined-2.c b/gcc/testsuite/gcc.target/sparc/combined-2.c
new file mode 100644
index 000000000..c4b70a55a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/combined-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo (pixel a, pixel b) {
+  vec8 c = __builtin_vis_fpmerge (a, b);
+  vec16 d = { -1, -1, -1, -1 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);
+
+  return e;
+}
+
+vec16 bar (pixel a) {
+  vec16 d = { 0, 0, 0, 0 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);  /* Mulitplication by 0 = 0.  */
+
+  return e;
+}
+
+/* { dg-final { scan-assembler "fmul8x16" } } */
+/* { dg-final { scan-assembler "fzero" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fand.c b/gcc/testsuite/gcc.target/sparc/fand.c
new file mode 100644
index 000000000..3194c921c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fand.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a & b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fand\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fandnot.c b/gcc/testsuite/gcc.target/sparc/fandnot.c
new file mode 100644
index 000000000..41db849c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fandnot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a & b;
+}
+#endif
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () & ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a & ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fandnots.c b/gcc/testsuite/gcc.target/sparc/fandnots.c
new file mode 100644
index 000000000..7a5ed2414
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fandnots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo1_16 ();
+}
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fandnot1s\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fands.c b/gcc/testsuite/gcc.target/sparc/fands.c
new file mode 100644
index 000000000..f924f4531
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fands.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fands\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fexpand-2.c b/gcc/testsuite/gcc.target/sparc/fexpand-2.c
new file mode 100644
index 000000000..c37b806c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fexpand-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mcpu=ultrasparc -mvis -fdump-tree-optimized" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo () {
+  vec8 a = {(unsigned char)1,(unsigned char)2,(unsigned char)4,(unsigned char)8};
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-tree-dump "{ 16, 32, 64, 128 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fexpand.c b/gcc/testsuite/gcc.target/sparc/fexpand.c
new file mode 100644
index 000000000..21aeafff0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fexpand.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo (vec8 a) {
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-assembler "fexpand\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnand.c b/gcc/testsuite/gcc.target/sparc/fnand.c
new file mode 100644
index 000000000..89fe8694d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnand.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo2_16 ());
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () & foo2_32 ());
+}
+
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo2_16 ();
+}
+
+vec32 fun32b(void)
+{
+  return ~foo1_32 () | ~foo2_32 ();
+}
+
+/* { dg-final { scan-assembler-times "fnand\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnands.c b/gcc/testsuite/gcc.target/sparc/fnands.c
new file mode 100644
index 000000000..05d6c4733
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnands.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo1_16 ());
+}
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnands\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnot.c b/gcc/testsuite/gcc.target/sparc/fnot.c
new file mode 100644
index 000000000..dceee52f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnot.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern void foo2_8(vec8);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a)
+{
+  foo2_8 (~a);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern void foo2_16(vec16);
+
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a)
+{
+  foo2_16 (~a);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern void foo2_32(vec32);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a)
+{
+  foo2_32 (~a);
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fnot1\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fnots.c b/gcc/testsuite/gcc.target/sparc/fnots.c
new file mode 100644
index 000000000..f50eb0b3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnots.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+extern vec16 foo1_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnot1s\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/for.c b/gcc/testsuite/gcc.target/sparc/for.c
new file mode 100644
index 000000000..7348dce20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/for.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a | b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "for\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fornot.c b/gcc/testsuite/gcc.target/sparc/fornot.c
new file mode 100644
index 000000000..09fdb4f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fornot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a | b;
+}
+#endif
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () | ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a | ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fornot1\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fornots.c b/gcc/testsuite/gcc.target/sparc/fornots.c
new file mode 100644
index 000000000..db29a9926
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fornots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo1_16 ();
+}
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fornot1s\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fors.c b/gcc/testsuite/gcc.target/sparc/fors.c
new file mode 100644
index 000000000..0afdd4bbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fors\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpack16.c b/gcc/testsuite/gcc.target/sparc/fpack16.c
new file mode 100644
index 000000000..79e0c4c15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpack16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec8 foo (vec16 a) {
+  return __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler "fpack16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpack32.c b/gcc/testsuite/gcc.target/sparc/fpack32.c
new file mode 100644
index 000000000..031372e21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpack32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec8 foo (vec32 a, vec8 b) {
+  return __builtin_vis_fpack32 (a, b);
+}
+
+/* { dg-final { scan-assembler "fpack32\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpackfix.c b/gcc/testsuite/gcc.target/sparc/fpackfix.c
new file mode 100644
index 000000000..815bec0cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpackfix.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo (vec32 a) {
+  return __builtin_vis_fpackfix (a);
+}
+
+/* { dg-final { scan-assembler "fpackfix\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpadd16.c b/gcc/testsuite/gcc.target/sparc/fpadd16.c
new file mode 100644
index 000000000..071282d2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpadd16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpadd16s.c b/gcc/testsuite/gcc.target/sparc/fpadd16s.c
new file mode 100644
index 000000000..7f65a7a93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpadd16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16s\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpadd32.c b/gcc/testsuite/gcc.target/sparc/fpadd32.c
new file mode 100644
index 000000000..7c57018a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpadd32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd32\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpadd32s.c b/gcc/testsuite/gcc.target/sparc/fpadd32s.c
new file mode 100644
index 000000000..709ad83c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpadd32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () + foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpadd32s\t%" }  } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpmerge-2.c b/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
new file mode 100644
index 000000000..524c736f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+#define _(ARG) (unsigned char)ARG
+
+pixel foo () {
+  vec8 a = { _(1), _(3), _(5), _(7) };
+  vec8 b = { _(2), _(4), _(6), _(8) };
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler-not "fpmerge\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4, 5, 6, 7, 8 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpmerge.c b/gcc/testsuite/gcc.target/sparc/fpmerge.c
new file mode 100644
index 000000000..4d6a9c023
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpmerge.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+pixel foo (vec8 a, vec8 b) {
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler "fpmerge\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpmul-2.c b/gcc/testsuite/gcc.target/sparc/fpmul-2.c
new file mode 100644
index 000000000..e04673e5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpmul-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+
+vec16 foo1 () {
+  pixel a = { (unsigned char)1, (unsigned char)2, (unsigned char)3, (unsigned char)4 };
+  vec16 b = { (short)1, (short)2, (short)3, (short)4 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_1 () {
+  pixel a = { (unsigned char)1, (unsigned char)1, (unsigned char)1, (unsigned char)1 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)2048 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_2 () {
+  pixel a = { (unsigned char)255, (unsigned char)255, (unsigned char)255, (unsigned char)255 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)32767 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16\t%" } } */
+/* { dg-final { scan-tree-dump "{ 0, 0, 0, 0 }" "optimized" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 4, 8 }" "optimized" } } */
+/* { dg-final { scan-tree-dump "{ 255, 510, 1020, 32639 }" "optimized" } } */
+
+vec16 foo2 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16au (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16au\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4 }" "optimized" } } */
+
+vec16 foo3 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16al (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16al\t%" } } */
+/* { dg-final { scan-tree-dump "{ 2, 4, 6, 8 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpmul.c b/gcc/testsuite/gcc.target/sparc/fpmul.c
new file mode 100644
index 000000000..71b3b17ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpmul.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (pixel a, vec16 b) {
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo2 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16au (a, b);
+}
+
+vec16 foo3 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16al (a, b);
+}
+
+vec16 foo4 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8sux16 (a, b);
+}
+
+vec16 foo5 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8ulx16 (a, b);
+}
+
+vec32 foo6 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8sux16 (a, b);
+}
+
+vec32 foo7 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8ulx16 (a, b);
+}
+
+/* { dg-final { scan-assembler "fmul8x16\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16au\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16al\t%" } } */
+/* { dg-final { scan-assembler "fmul8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmul8ulx16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8ulx16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpsub16.c b/gcc/testsuite/gcc.target/sparc/fpsub16.c
new file mode 100644
index 000000000..05642dec1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpsub16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpsub16s.c b/gcc/testsuite/gcc.target/sparc/fpsub16s.c
new file mode 100644
index 000000000..29e0d3e18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpsub16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16s\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpsub32.c b/gcc/testsuite/gcc.target/sparc/fpsub32.c
new file mode 100644
index 000000000..e1813f491
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpsub32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub32\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fpsub32s.c b/gcc/testsuite/gcc.target/sparc/fpsub32s.c
new file mode 100644
index 000000000..c9d4ccc6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fpsub32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () - foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpsub32s\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxnor.c b/gcc/testsuite/gcc.target/sparc/fxnor.c
new file mode 100644
index 000000000..a685e08e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxnor.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo2_16 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () ^ foo2_32 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () ^ ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxnor\t%" 6 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxnors.c b/gcc/testsuite/gcc.target/sparc/fxnors.c
new file mode 100644
index 000000000..29775cffe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxnors.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo1_16 ());
+}
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxnors\t%" 4 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxor.c b/gcc/testsuite/gcc.target/sparc/fxor.c
new file mode 100644
index 000000000..581b37b54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxor.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () ^ foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a ^ b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxor\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fxors.c b/gcc/testsuite/gcc.target/sparc/fxors.c
new file mode 100644
index 000000000..5da017a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fxors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxors\t%" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/globalreg-1.c b/gcc/testsuite/gcc.target/sparc/globalreg-1.c
new file mode 100644
index 000000000..3839d9f13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/globalreg-1.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -Os" } */
+
+/* This is a massively distilled test case based upon
+   mm/memory.c:unmap_vmas() in the Linux kernel when compiled
+   on sparc64 for SMP which uses a global register as the
+   base of the per-cpu variable area.
+
+   Because of a bug in global register handling in the dataflow
+   code, the loop-invariant pass would move 'expression(regval)'
+   outside of the loop.  */
+
+extern void exit(int);
+extern void abort(void);
+
+register unsigned long regval __asm__("g6");
+
+extern void cond_resched(void);
+
+unsigned int var;
+
+static unsigned long expression(unsigned long v)
+{
+  unsigned long ret;
+
+  __asm__("" : "=r" (ret) : "0" (0));
+  return ret + v;
+}
+
+void func(unsigned long *pp)
+{
+  int i;
+
+  for (i = 0; i < 56; i++) {
+    cond_resched();
+    *pp = expression(regval);
+  }
+}
+
+void __attribute__((noinline)) cond_resched(void)
+{
+	regval++;
+}
+
+int main(void)
+{
+  unsigned long val;
+
+  regval = 100;
+  func(&val);
+  if (val != 156)
+    abort();
+  exit(0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/mfpu.c b/gcc/testsuite/gcc.target/sparc/mfpu.c
new file mode 100644
index 000000000..e95754c5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/mfpu.c
@@ -0,0 +1,11 @@
+/* Reported by Peter A. Krauss <peter.a.krauss@web.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-mfpu" } */
+
+float square(float x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fmuls" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/mnofpu.c b/gcc/testsuite/gcc.target/sparc/mnofpu.c
new file mode 100644
index 000000000..351585dd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/mnofpu.c
@@ -0,0 +1,90 @@
+/* PR target/35664 */
+/* Tetstcase by Mike Stein <mstein.lists@googlemail.com> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-fpu" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef unsigned long long u64;
+struct pt_regs {
+};
+static inline __attribute__((always_inline)) struct task_struct *__get_current(void)
+{
+}
+static inline __attribute__((always_inline)) u32 flip_dword (u32 l)
+{
+ return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
+}
+static inline __attribute__((always_inline)) u32 __readl(const volatile void *addr)
+{
+ return flip_dword(*( volatile u32 *)addr);
+}
+enum e1e_registers {
+ E1000_PRC64 = 0x0405C,
+ E1000_PRC127 = 0x04060,
+ E1000_PRC255 = 0x04064,
+ E1000_PTC511 = 0x040E4,
+ E1000_PTC1023 = 0x040E8,
+ E1000_PTC1522 = 0x040EC,
+ E1000_MPTC = 0x040F0,
+};
+enum e1000_media_type {
+ e1000_media_type_copper = 1,
+};
+struct e1000_rx_desc {
+ struct {
+ } wb;
+};
+struct e1000_hw_stats {
+ u64 prc64;
+ u64 prc127;
+ u64 prc255;
+ u64 ptc511;
+ u64 ptc1023;
+ u64 ptc1522;
+ u64 mptc;
+};
+struct e1000_shadow_ram {
+ u16 value;
+};
+struct e1000_dev_spec_ich8lan {
+ struct e1000_shadow_ram shadow_ram[2048];
+};
+struct e1000_hw {
+ u8 *hw_addr;
+ union {
+  struct e1000_dev_spec_ich8lan ich8lan;
+ } dev_spec;
+ enum e1000_media_type media_type;
+};
+struct e1000_adapter {
+ u16 link_speed;
+ struct e1000_hw hw;
+ struct e1000_hw_stats stats;
+ unsigned int flags;
+};
+static inline __attribute__((always_inline)) u32 __er32(struct e1000_hw *hw, unsigned long reg)
+{
+ return __readl(hw->hw_addr + reg);
+}
+void e1000e_update_stats(struct e1000_adapter *adapter)
+{
+ struct e1000_hw *hw = &adapter->hw;
+ u16 phy_tmp;
+ if (adapter->flags & (1 << 10)) {
+  adapter->stats.prc64 += __er32(hw, E1000_PRC64);
+  adapter->stats.prc127 += __er32(hw, E1000_PRC127);
+  adapter->stats.prc255 += __er32(hw, E1000_PRC255);
+  adapter->stats.ptc511 += __er32(hw, E1000_PTC511);
+  adapter->stats.ptc1023 += __er32(hw, E1000_PTC1023);
+  adapter->stats.ptc1522 += __er32(hw, E1000_PTC1522);
+ }
+ adapter->stats.mptc += __er32(hw, E1000_MPTC);
+ if (hw->media_type == e1000_media_type_copper) {
+  if ((adapter->link_speed == 1000) &&
+     (!e1e_rphy(hw, 0x0A, &phy_tmp))) {
+  }
+ }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/noresult.c b/gcc/testsuite/gcc.target/sparc/noresult.c
new file mode 100644
index 000000000..1be7458d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/noresult.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+void foo (vec16 a) {
+  __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler-not "fpack16\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/pdist-2.c b/gcc/testsuite/gcc.target/sparc/pdist-2.c
new file mode 100644
index 000000000..b9cbb3461
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/pdist-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+#define _(A) (unsigned char)A
+
+int64_t foo () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+/* { dg-final { scan-assembler-not "pdist\t%" } } */
+/* { dg-final { scan-tree-dump "return 475" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/pdist-3.c b/gcc/testsuite/gcc.target/sparc/pdist-3.c
new file mode 100644
index 000000000..03df4d96d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/pdist-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+extern void abort ();
+extern void exit (int);
+
+#define _(A) (unsigned char)A
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 2;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+
+static vec8 a = { 1, 2, 3, 4, 5, 6, 7, 255 };
+static vec8 b = { 2, 4, 8, 16, 32, 64, 128, 8 };
+
+int main (int argc, char *argv[]) {
+
+  if (foo (a, b) != bar ())
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/pdist.c b/gcc/testsuite/gcc.target/sparc/pdist.c
new file mode 100644
index 000000000..6ecc20aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/pdist.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 0;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar (vec8 a, vec8 b) {
+  int64_t d = 0;
+  return __builtin_vis_pdist (a, b, d);
+}
+
+int64_t baz (vec8 a, vec8 b, int64_t d) {
+  int64_t e = __builtin_vis_pdist (a, b, d);
+  return e + d;
+}
+
+/* { dg-final { scan-assembler-times "pdist\t%" 3 } } */
diff --git a/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c b/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
new file mode 100644
index 000000000..db3401648
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern int one ();
+
+int some_n ()
+{
+    return one ();
+}
+
+/* { dg-final { scan-assembler-not "nop" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-align-1.c b/gcc/testsuite/gcc.target/sparc/sparc-align-1.c
new file mode 100644
index 000000000..14c915e1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-align-1.c
@@ -0,0 +1,31 @@
+/* PR target/31100 */
+/* Reported by Erwin Unruh <Erwin.Unruh@fujitsu-siemens.com> */
+
+/* { dg-do run } */
+/* { dg-options "-falign-labels=16" } */
+
+extern void abort(void);
+
+int f(int i)
+{
+  int res;
+
+  switch (i)
+    {
+    case 5:
+      res = i - i;
+      break;
+    default:
+      res = i * 2;
+      break;
+    }
+
+  return res;
+}
+
+int main(void)
+{
+  if (f(2) != 4)
+    abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c b/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
new file mode 100644
index 000000000..491f9d3f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
@@ -0,0 +1,13 @@
+/* PR optimization/10876 */
+
+/* { dg-do compile } */
+
+/* Verify that adding the constant 4096 is turned
+   into substracting the constant -4096. */
+
+int foo(int a)
+{
+  return a+4096;
+}
+
+/* { dg-final { scan-assembler "sub" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c b/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
new file mode 100644
index 000000000..819ec3863
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
@@ -0,0 +1,32 @@
+/* PR target/10114 */
+/* Originator: James Troup <james@nocrew.org> */
+
+/* { dg-do compile } */
+/* { dg-options "-g -O1" } */
+
+extern __inline double sqrt (double __x)
+{
+  register double __r;
+  __asm ("fsqrtd %1,%0" : "=f" (__r) : "f" (__x));
+  return __r;
+}
+
+static double our_skew, max_update_skew;
+
+static double Sqr(double x)
+{
+  return x*x;
+}
+
+void REF_SetReference(double skew)
+{
+  double previous_skew, new_skew;
+  double old_weight, new_weight, sum_weight;
+  double delta_freq1, delta_freq2;
+  double skew1, skew2;
+
+  previous_skew = our_skew;
+  skew1 = sqrt((Sqr(delta_freq1) * old_weight + Sqr(delta_freq2) * new_weight) / sum_weight);
+  skew2 = (previous_skew * old_weight + new_skew * new_weight) / sum_weight;
+  our_skew = skew1 + skew2;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c b/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
new file mode 100644
index 000000000..7aac1e26e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
@@ -0,0 +1,13 @@
+/* PR target/24284 */
+
+/* { dg-do compile } */
+/* { dg-options "-O -g" } */
+
+void do_run(void *ip)
+{
+  char dummy[8192];
+
+  __asm__("" : : "g"(dummy));
+
+  goto *ip;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c b/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
new file mode 100644
index 000000000..cd468c562
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
@@ -0,0 +1,118 @@
+/* PR middle-end/22127 */
+/* Testcase by <akr@m17n.org> */
+
+/* { dg-do run { target *-*-solaris2.* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef unsigned int size_t;
+extern int printf(const char *, ...);
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef unsigned int uint_t;
+typedef char *caddr_t;
+typedef int greg_t;
+typedef greg_t gregset_t[19];
+struct rwindow {
+ greg_t rw_local[8];
+ greg_t rw_in[8];
+};
+typedef struct gwindows {
+ int wbcnt;
+ greg_t *spbuf[31];
+ struct rwindow wbuf[31];
+} gwindows_t;
+struct fpu {
+ union {
+  uint32_t fpu_regs[32];
+  double fpu_dregs[16];
+ } fpu_fr;
+ struct fq *fpu_q;
+ uint32_t fpu_fsr;
+ uint8_t fpu_qcnt;
+ uint8_t fpu_q_entrysize;
+ uint8_t fpu_en;
+};
+typedef struct fpu fpregset_t;
+typedef struct {
+ unsigned int xrs_id;
+ caddr_t xrs_ptr;
+} xrs_t;
+typedef struct {
+ gregset_t gregs;
+ gwindows_t *gwins;
+ fpregset_t fpregs;
+ xrs_t xrs;
+ long filler[19];
+} mcontext_t;
+typedef struct {
+ unsigned int __sigbits[4];
+} sigset_t;
+typedef struct sigaltstack {
+ void *ss_sp;
+ size_t ss_size;
+ int ss_flags;
+} stack_t;
+typedef struct ucontext ucontext_t;
+struct ucontext {
+ uint_t uc_flags;
+ ucontext_t *uc_link;
+ sigset_t uc_sigmask;
+ stack_t uc_stack;
+ mcontext_t uc_mcontext;
+ long uc_filler[23];
+};
+extern int getcontext(ucontext_t *);
+extern int setcontext(const ucontext_t *);
+
+int flag;
+ucontext_t cont;
+int pad[100];
+typedef void (*fun_t)(int);
+fun_t p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12;
+
+int global;
+
+extern void abort(void);
+
+void h1(int v)
+{
+  global = v;
+}
+
+void h2(int v)
+{
+  if (v != 1)
+    abort();
+}
+
+void f(void)
+{
+  flag = 1;
+  setcontext(&cont);
+}
+
+int g(void)
+{
+  int ret;
+
+  flag = 0;
+  getcontext(&cont);
+  ret = flag;
+  if (ret == 0) {
+    h1 (flag);
+    p0 = p1 = p2 = p3 = p4 = p5 = p6 = p7 = p8 = h1;
+    f();
+    p0(ret); p1(ret); p2(ret); p3(ret); p4(ret); p5(ret); p6(ret); p7(ret); p8(ret);
+  }
+  else {
+    h2 (flag);
+  }
+  return ret;
+}
+
+int main(void)
+{
+  g();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c b/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
new file mode 100644
index 000000000..cb8d00762
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
@@ -0,0 +1,19 @@
+/* PR optimization/10157 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+/* Verify that the loop optimizer doesn't
+   emit invalid reg-to-reg copy insns. */
+
+void g() {
+  while(1) {
+    int i,n;
+    double p,r;
+    for( i=0; i < n; i++ )
+      if( p > 1. )
+        for( i=0; i < n; i++ )
+          r += 2.;
+  }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c b/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
new file mode 100644
index 000000000..0adb4cdca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
@@ -0,0 +1,11 @@
+/* PR middle-end/20263 */
+
+/* { dg-do assemble } */
+/* { dg-options "" } */
+
+register void *tp __asm__("%g7");
+
+void set_tp(void)
+{
+  tp = 0;
+} 
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-ret.c b/gcc/testsuite/gcc.target/sparc/sparc-ret.c
new file mode 100644
index 000000000..11afc1082
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-ret.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mcpu=ultrasparc -O" } */
+
+/* Make sure that Ultrasparc return insn do not read below the stack.  */
+
+int bar (int a, int b, int c, int d, int e, int f, int g, int h)
+{
+  int res;
+
+  toto (&res);
+  return h;
+}
+/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*ld\[ \t\]*\\\[%sp\\+96\\\]" } } } */
+
+int bar2 ()
+{
+  int res;
+
+  toto (&res);
+  return res;
+}
+/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*nop" } } } */
diff --git a/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c b/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
new file mode 100644
index 000000000..82a86fbe1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
@@ -0,0 +1,21 @@
+/* PR target/15693 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* This used to fail on SPARC at -O2 because the combiner
+   produces a compare insn that was not rematched by the
+   compare expander.  */
+
+static __inline__ __attribute__ ((always_inline))
+int page_mapping (unsigned flags)
+{
+  if (1u & (flags >> 16))
+    return 1;
+  return 0;
+}
+void install_page (unsigned flags)
+{
+  if (__builtin_expect (!page_mapping (flags), 0))
+    __builtin_trap ();
+}
diff --git a/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc/testsuite/gcc.target/sparc/sparc.exp
new file mode 100644
index 000000000..9658d08bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/sparc.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 1997, 2004, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a SPARC target.
+if ![istarget sparc*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/sparc/struct-ret-check.c b/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
new file mode 100644
index 000000000..350224eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
@@ -0,0 +1,126 @@
+/* Copyright (C) 2006 Free Software Foundation, Inc. */
+/* Contributed by Carlos O'Donell on 2006-03-14 */
+
+/* Test that GCC follows the SPARC 32-bit psABI with regards to
+   structure return checking in a callee. When -mstd-struct-return 
+   is specificed then gcc will emit code to skip the unimp insn. */ 
+
+/* Origin: Carlos O'Donell <carlos@codesourcery.com> */
+/* { dg-do run { target sparc*-*-solaris* sparc*-*-linux* sparc*-*-*bsd* } } */
+/* { dg-options "-mstd-struct-return" } */
+/* { dg-require-effective-target ilp32 } */
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+
+/* Local declaration of div_t structure */
+struct mydiv_t {
+  int rem;
+  int quot;
+};
+
+/* Global check variable used by signal handler */
+int check = 1;
+struct mydiv_t dcheck;
+
+struct mydiv_t foo (void)
+{
+  struct mydiv_t bar;
+  bar.rem = 3;
+  bar.quot = 4;
+  return bar;
+}
+
+void handle_sigill (int signum)
+{
+  if (signum == SIGILL && check == 2)
+    {
+      /* We expected a SIGILL due to a mismatch in unimp size
+	 and struct mydiv_t size */
+      exit (0);
+    }
+  else
+    abort ();
+}
+
+/* Implement 3 checks to validate SPARC 32-bit psABI callee 
+   returns struct
+   
+   Test1: Save area is valid. unimp size is valid.
+   Success: Save area modified correctly.
+   Failure: Save area unmodified.
+
+   Test2: Save area is valid. unimp size is invalid (invalid insn).
+   Success: Save area unmodified. check == 2.
+   Failure: Save area modified or check == 1.
+
+   Test3: Save area is invalid. unimp size is invalid (invalid size).
+   Success: Will raise a SIGILL. 
+   Failure: SIGSEGV caused by write to invalid save area. */
+
+int main (void)
+{
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /*** Test1 ***/
+  /* Insert a call, insert unimp by hand */
+  __asm__ ("st %1, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %2\n\t" 
+	   : "=m" (dcheck)
+	   : "r" (&dcheck), "i" (sizeof(struct mydiv_t)) 
+	   : "memory");
+
+  /* If the caller doesn't adjust the return, then it crashes.
+     Check the result too. */
+
+  if ((dcheck.rem != 3) || (dcheck.quot !=4))
+    abort ();
+  
+
+  /*** Test 2 ***/
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /* Ignore the return of the function */
+  __asm__ ("st %3, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "mov %2, %0\n\t"
+	   : "+r" (check), "=m" (dcheck) 
+	   : "i" (0x2), "r" (&dcheck)
+	   : "memory");
+
+  /* If the caller does an unconditional adjustment it will skip
+     the mov, and then we can fail the test based on check's value 
+     We pass a valid pointer to a save area in order to check if 
+     caller incorrectly wrote to the save area aswell. There may
+     be a case where the unimp check and skip is correct, but the
+     write to the save area still occurs. */
+
+  if (check != 2)
+    abort ();
+
+  if ((dcheck.rem != 1) || (dcheck.quot != 2))
+    abort ();
+
+  /*** Test 3 ***/
+  /* Prepare a test that must SIGILL. According to the spec
+     if the sizes of the save area and return don't match then
+     the copy is ignored and we return to the unimp. */
+
+  signal (SIGILL, handle_sigill);
+
+  __asm__ ("st %%g0, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %0\n\t"
+	   : /* No outputs */ 
+	   : "i" (sizeof(struct mydiv_t)-1) 
+	   : "memory");
+
+  /* NEVER REACHED */
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp1.c b/gcc/testsuite/gcc.target/sparc/ultrasp1.c
new file mode 100644
index 000000000..7db750589
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp1.c
@@ -0,0 +1,8 @@
+/* Simplified from testcase by David Staepelaere <staapa@ultimatech.com> */
+
+/* { dg-do compile } */
+/* { dg-options -mcpu=ultrasparc } */
+
+int foo(long long y) {
+  return -1 * y;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp10.c b/gcc/testsuite/gcc.target/sparc/ultrasp10.c
new file mode 100644
index 000000000..d3edaca6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp10.c
@@ -0,0 +1,27 @@
+/* PR target/11965 */
+/* Originator: <jk@tools.de> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because GCC emitted
+   an invalid shift instruction.  */
+
+
+static inline unsigned int shift(int n, unsigned int value)
+{
+  return value << n;
+}
+
+unsigned int val = 1;
+
+int main(void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    val = shift(32, val);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp11.c b/gcc/testsuite/gcc.target/sparc/ultrasp11.c
new file mode 100644
index 000000000..91e64782b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp11.c
@@ -0,0 +1,26 @@
+/* PR target/17245 */
+/* Origin: <aaronw@net.com> */
+/* Testcase by Christian Ehrhardt <ehrhardt@mathematik.uni-ulm.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=v9" } */
+
+/* This used to fail on 32-bit Ultrasparc because reload was emitting
+   a move insn that doesn't satisfy its constraints.  */
+
+int n; 
+double range ;
+double bin ;
+double wmean;
+
+double f ()
+{
+  int i ;
+  long double W = 0 ;
+  for ( i = 0 ; i < n ; i ++) {
+    double xi = range;
+    double wi = bin;
+    W += wi ;
+    wmean += ( xi - wmean) * ( wi / W);
+  }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp2.c b/gcc/testsuite/gcc.target/sparc/ultrasp2.c
new file mode 100644
index 000000000..24202ba5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp2.c
@@ -0,0 +1,11 @@
+/* Copyright (C) 1999 Free Software Foundation
+   by Alexandre Oliva <oliva@lsd.ic.unicamp.br>
+   Simplified from libg++/src/Fix16.cc */
+
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+short foo() {
+  short i = (short)(1<<15);
+  return i;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp3.c b/gcc/testsuite/gcc.target/sparc/ultrasp3.c
new file mode 100644
index 000000000..870258813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp3.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { ! { ilp32 && ultrasparc_hw } } } */
+/* { dg-options "-mcpu=ultrasparc -mv8plus" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned long long foo (unsigned long long x)
+{
+  return 0x73500000735LL * x;
+}
+
+unsigned long long a, b;
+unsigned long p;
+
+unsigned long long bar (void)  
+{
+  unsigned long long c = a | b;
+  return 0x73500000735LL * c;
+}
+
+unsigned long long baz (void)
+{
+  unsigned long long c = (p + 345) & -2;
+  return c * a;
+}
+
+int main (void)
+{
+  if (foo (0x56789LL) != 0x26f32e5d26f32e5dLL)
+    abort ();
+  a = 0x8000000080000000LL;
+  b = 0x0000000180000001LL;
+  if (bar () != 0x120480000735LL)
+    abort ();
+  p = 0xffffffff;
+  if (baz () != 0xac00000000LL)
+    abort ();
+  exit (0);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp4.c b/gcc/testsuite/gcc.target/sparc/ultrasp4.c
new file mode 100644
index 000000000..f3958cbe7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp4.c
@@ -0,0 +1,12 @@
+/* Simplified from PR target/5309.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+extern long bar (unsigned int);
+
+long
+foo (long x, unsigned int y)
+{
+  return *(((long *) (bar (y) - 1)) + 1 + (x >> 2) % 359);
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp5.c b/gcc/testsuite/gcc.target/sparc/ultrasp5.c
new file mode 100644
index 000000000..feb6cf244
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp5.c
@@ -0,0 +1,13 @@
+/* PR target/10072 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O1 -mcpu=ultrasparc -ffast-math" } */
+
+void p(int v)
+{
+  int i=v,j;
+  float a,b,c,x[i];
+
+  x[i] = (a/(((b)>(c)) ? (b) : (c)) - (((i) == (j)) ? 1.f : 0.f));
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp6.c b/gcc/testsuite/gcc.target/sparc/ultrasp6.c
new file mode 100644
index 000000000..ad341dc16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp6.c
@@ -0,0 +1,151 @@
+/* PR target/7784 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+typedef struct
+{
+  float EnergyErg;
+  float ots;
+} EmLine;
+
+extern const int ipH_LIKE ;
+extern const int ipHYDROGEN ;
+extern const int ipH1s;
+extern const int ipH2s;
+extern const int ipH2p;
+
+extern EmLine ****EmisLines;
+
+typedef struct
+{
+  long n;
+  long s;
+  long l;
+} Elevels;
+
+extern struct t_iso
+{
+  float ***Pop2Ion;
+  long int numLevels[2][30L];
+} iso;
+
+extern struct t_LineSave
+{
+  long int nsum;
+  long int ndsum;
+  long int nComment;
+  long int npxdd;
+  long int ipass;
+  char chHoldComments[10][200];
+} LineSave;
+
+extern struct t_hydro
+{
+  int lgHydEmiss;
+  float **pestrk ;
+} hydro;
+
+extern struct t_dense
+{
+  double DensityLaw[10];
+  float frad[500];
+  float fhden[500];
+  float den0;
+  double eden;
+} dense;
+
+extern struct t_abund
+{
+  float xIonFracs[30L +3][30L +1];
+} abund;
+
+extern struct t_CaseBHS
+{
+  long int nDensity[2][8] , ntemp[2][8] , ncut[2][8] ;
+  int lgHCaseBOK[2][8];
+} CaseBHS ;
+
+extern struct t_smbeta
+{
+  float SimHBeta,
+    cn4861,
+    cn1216,
+    sv4861,
+    sv1216;
+} smbeta;
+
+extern struct t_phycon
+{
+  float te;
+} phycon;
+
+
+extern struct t_sphere
+{
+  int lgSphere;
+  float covgeo;
+} sphere;
+
+void linadd(double xInten, float wavelength, char *chLab, char chInfo);
+
+extern struct t_radiusVar
+{
+  int lgDrNeg;
+  double dVeff;
+} radius;
+
+void lines_hydro(void)
+{
+  long int i, nelem, ipHi, ipLo;
+  double hbetab, em , EmisFac, pump;
+  char chLabel[5];
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][3]*hydro.pestrk[3][2]*3.025e-12, 6563,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][2]*4.084e-12, 4861,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][3]*1.059e-12, 18751,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][5]*hydro.pestrk[5][4]*4.900e-13, 40512,"Strk",'i');
+
+  ((void)((LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.) || (__assert("LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.", "lines_hydro.c", 118), 0)));
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].ots*EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].EnergyErg, 6563,"Dest",'i');
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][5][4].ots*EmisLines[ipH_LIKE][ipHYDROGEN][5][4].EnergyErg,40516, "Dest",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta/(float)radius.dVeff*sphere.covgeo;
+
+  linadd(smbeta.SimHBeta,4861,"Q(H)",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta*(float)radius.dVeff/sphere.covgeo;
+
+  for( nelem=0; nelem < 30L; nelem++ )
+  {
+    int iCase;
+    for( iCase=0; iCase<2; ++iCase )
+    {
+      char chAB[2]={'A','B'};
+      char chLab[5]="Ca  ";
+
+      for( ipLo=1+iCase; ipLo<(((6)<(iso.numLevels[ipH_LIKE][nelem])) ? (6) : (5)); ++ipLo )
+      {
+        for( ipHi=ipLo+1; ipHi< (((ipLo+5)<(iso.numLevels[ipH_LIKE][nelem])) ? (ipLo+5) : (iso.numLevels[ipH_LIKE][nelem])); ++ipHi )
+        {
+          float wl;
+
+          hbetab = HSRate( ipHi,ipLo , nelem+1, phycon.te , dense.eden, chAB[iCase] );
+          if( hbetab<=0. )
+            CaseBHS.lgHCaseBOK[iCase][nelem] = 0;
+
+          if( !hydro.lgHydEmiss )
+            hbetab *= abund.xIonFracs[nelem][nelem+1]*dense.eden;
+
+         linadd(hbetab,wl,chLab,'i' );
+        }
+      }
+    }
+  }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp7.c b/gcc/testsuite/gcc.target/sparc/ultrasp7.c
new file mode 100644
index 000000000..b5a17b448
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp7.c
@@ -0,0 +1,51 @@
+/* PR c/8281 */
+/* Originator: TANIGUCHI Yasuaki <yasuaki@k8.dion.ne.jp> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcpu=ultrasparc -fPIC" } */
+
+static const double bp = 1.0, dp_l[] = { 0.0 };
+
+double __ieee754_pow(double x, double y)
+{
+  union {
+    int lo;
+    double d;
+  }uz;
+
+  double y1,t1,p_h,t,z;
+  double z_h,z_l,p_l;
+  double t2,r,s,u,v,w;
+  int i = 0;
+ 
+  double s_h,t_h;
+  double s2,s_l,t_l;
+ 
+ 
+  v = 1.0/(v+bp);
+  uz.d = s_h = s = u*v;
+  uz.lo = 0;
+  s_h = uz.d;
+  uz.d = t_h;
+  uz.lo = 3;
+  t_h = uz.d;
+  s_l = v*((u-s_h*t_h)-s_h*t_l);
+  s2 = s*s;
+  r = s2* s2* (1.1+s2*(1.2+s2*(1.3+s2*(1.4+s2*(1.5+s2*1.6)))));
+  s2 = s_h*s_h;
+  uz.lo = 0;
+  t_h = uz.d;
+  t_l = r-((t_h-3.0)-s2);
+  v = s_l*t_h+t_l*s;
+  p_l = v-(p_h-u);
+  z_h = bp *p_h;
+  z_l = bp*p_h+p_l*1.0+dp_l[i];
+  t = (double)i;
+  t1 = (((bp+z_l)+bp)+t);
+  t2 = z_l-(((t1-t)-bp)-z_h);
+  p_l = (y-y1)*t1+y*t2;
+  z = p_l+p_h;
+
+  return s*z;
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp8.c b/gcc/testsuite/gcc.target/sparc/ultrasp8.c
new file mode 100644
index 000000000..a8bfefee5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp8.c
@@ -0,0 +1,40 @@
+/* PR target/10067 */
+/* Originator: <dat94ali@ludat.lth.se> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=supersparc" } */
+
+struct _reent;
+
+extern unsigned long __malloc_trim_threshold;
+extern unsigned long __malloc_top_pad;
+
+int _mallopt_r(struct _reent *reent_ptr, int param_number, int value)
+{
+  __malloc_lock(reent_ptr);
+
+  switch(param_number)
+  {
+    case -1:
+      __malloc_trim_threshold = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -2:
+      __malloc_top_pad = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -3:
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -4:
+      __malloc_unlock(reent_ptr);
+      return value == 0;
+
+    default:
+      __malloc_unlock(reent_ptr);
+      return 0;
+  }
+}
diff --git a/gcc/testsuite/gcc.target/sparc/ultrasp9.c b/gcc/testsuite/gcc.target/sparc/ultrasp9.c
new file mode 100644
index 000000000..b26d7dce1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/ultrasp9.c
@@ -0,0 +1,41 @@
+/* PR optimization/11018 */
+/* Originator: <partain@dcs.gla.ac.uk> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because
+   of broken DImode shift patterns.  */
+
+extern void abort(void);
+
+typedef unsigned long long uint64_t;
+typedef unsigned int size_t;
+
+
+void to_octal (uint64_t value, char *where, size_t size)
+{
+  uint64_t v = value;
+  size_t i = size;
+
+  do
+    {
+      where[--i] = '0' + (v & ((1 << 3) - 1));
+      v >>= 3;
+    }
+  while (i);
+}
+
+
+int main (void)
+{
+  char buf[8];
+
+  to_octal(010644, buf, 6);
+
+  if (buf[1] != '1')
+     abort();
+
+  return 0;
+}