diff options
Diffstat (limited to 'gcc/config/pdp11')
| -rw-r--r-- | gcc/config/pdp11/constraints.md | 81 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11-modes.def | 26 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11-protos.h | 47 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11.c | 1923 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11.h | 685 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11.md | 1386 | ||||
| -rw-r--r-- | gcc/config/pdp11/pdp11.opt | 87 | ||||
| -rw-r--r-- | gcc/config/pdp11/predicates.md | 55 | ||||
| -rw-r--r-- | gcc/config/pdp11/t-pdp11 | 44 |
9 files changed, 4334 insertions, 0 deletions
diff --git a/gcc/config/pdp11/constraints.md b/gcc/config/pdp11/constraints.md new file mode 100644 index 000000000..6e5a5798e --- /dev/null +++ b/gcc/config/pdp11/constraints.md @@ -0,0 +1,81 @@ +;;- Constraint definitions for the pdp11 for GNU C compiler +;; Copyright (C) 2010 Free Software Foundation, Inc. +;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_register_constraint "f" "FPU_REGS" + "Any FPU register") + +(define_register_constraint "a" "LOAD_FPU_REGS" + "FPU register that can be directly loaded from memory") + +(define_register_constraint "d" "MUL_REGS" + "General register that can be used for 16-bit multiply (odd numbered)") + +(define_constraint "I" + "Integer constant that fits in 16 bits unsigned" + (and (match_code "const_int") + (match_test "(ival & 0xffff0000) == 0"))) + +(define_constraint "J" + "Integer constant whose low 16 bits are zero" + (and (match_code "const_int") + (match_test "(ival & 0xffff) == 0"))) + +(define_constraint "K" + "Integer constant whose lower and upper 16 bit half are both non-zero" + (and (match_code "const_int") + (match_test "(ival & 0xffff) != 0 && (ival & 0xffff0000) != 0"))) + +(define_constraint "L" + "Integer constant 1" + (and (match_code "const_int") + (match_test "ival == 1"))) + +(define_constraint "M" + "Integer constant -1" + (and (match_code "const_int") + (match_test "ival == -1"))) + +(define_constraint "N" + "Integer constant 0" + (and (match_code "const_int") + (match_test "ival == 0"))) + +(define_constraint "O" + "Integer constant for which several individual shifts are better than one big one" + (and (match_code "const_int") + (match_test "abs (ival) > 1 && abs (ival) <= 4"))) + +(define_constraint "G" + "Defines a real zero constant." + (and (match_code "const_double") + (match_test "op == CONST0_RTX (GET_MODE (op))"))) + +(define_constraint "Q" + "Memory reference that requires an additional word after the opcode" + (and (match_code "mem") + (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0)) + && !simple_memory_operand (op, GET_MODE (op))"))) + +(define_constraint "R" + "Memory reference that is encoded within the opcode" + (and (match_code "mem") + (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0)) + && simple_memory_operand (op, GET_MODE (op))"))) + diff --git a/gcc/config/pdp11/pdp11-modes.def b/gcc/config/pdp11/pdp11-modes.def new file mode 100644 index 000000000..b91cde7d1 --- /dev/null +++ b/gcc/config/pdp11/pdp11-modes.def @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for the pdp-11 + Copyright (C) 2002, 2004, 2007 Free Software Foundation, Inc. + Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* Add any extra modes needed to represent the condition code. + CCFPmode is used for FPU, but should we use a separate reg? */ + +CC_MODE (CCFP); +RESET_FLOAT_FORMAT (SF, pdp11_f_format); +RESET_FLOAT_FORMAT (DF, pdp11_d_format); diff --git a/gcc/config/pdp11/pdp11-protos.h b/gcc/config/pdp11/pdp11-protos.h new file mode 100644 index 000000000..56ad909e1 --- /dev/null +++ b/gcc/config/pdp11/pdp11-protos.h @@ -0,0 +1,47 @@ +/* Definitions of target machine for GNU compiler, for the pdp-11 + Copyright (C) 2000, 2003, 2004, 2007, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* declarations */ +#ifdef RTX_CODE +extern int simple_memory_operand (rtx, enum machine_mode); + +extern int legitimate_const_double_p (rtx); +extern void notice_update_cc_on_set (rtx, rtx); +extern void output_addr_const_pdp11 (FILE *, rtx); +extern const char *output_move_multiple (rtx *); +extern const char *output_block_move (rtx *); +extern const char *output_jump (enum rtx_code, int, int); +extern void print_operand_address (FILE *, rtx); +extern bool pdp11_cannot_change_mode_class (enum machine_mode, + enum machine_mode, enum reg_class); +extern bool pdp11_secondary_memory_needed (reg_class_t, reg_class_t, + enum machine_mode); +typedef enum { no_action, dec_before, inc_after } pdp11_action; +typedef enum { little, either, big } pdp11_partorder; +extern bool pdp11_expand_operands (rtx *, rtx [][2], int, + pdp11_action *, pdp11_partorder); +extern int pdp11_initial_elimination_offset (int, int); +extern enum reg_class pdp11_regno_reg_class (int); + +#endif /* RTX_CODE */ + +extern void output_ascii (FILE *, const char *, int); +extern void pdp11_asm_output_var (FILE *, const char *, int, int, bool); diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c new file mode 100644 index 000000000..b6ed97989 --- /dev/null +++ b/gcc/config/pdp11/pdp11.c @@ -0,0 +1,1923 @@ +/* Subroutines for gcc2 for pdp11. + Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005, + 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "conditions.h" +#include "function.h" +#include "output.h" +#include "insn-attr.h" +#include "flags.h" +#include "recog.h" +#include "tree.h" +#include "expr.h" +#include "diagnostic-core.h" +#include "tm_p.h" +#include "target.h" +#include "target-def.h" +#include "df.h" + +/* this is the current value returned by the macro FIRST_PARM_OFFSET + defined in tm.h */ +int current_first_parm_offset; + +/* Routines to encode/decode pdp11 floats */ +static void encode_pdp11_f (const struct real_format *fmt, + long *, const REAL_VALUE_TYPE *); +static void decode_pdp11_f (const struct real_format *, + REAL_VALUE_TYPE *, const long *); +static void encode_pdp11_d (const struct real_format *fmt, + long *, const REAL_VALUE_TYPE *); +static void decode_pdp11_d (const struct real_format *, + REAL_VALUE_TYPE *, const long *); + +/* These two are taken from the corresponding vax descriptors + in real.c, changing only the encode/decode routine pointers. */ +const struct real_format pdp11_f_format = + { + encode_pdp11_f, + decode_pdp11_f, + 2, + 24, + 24, + -127, + 127, + 15, + 15, + false, + false, + false, + false, + false, + false, + false, + false + }; + +const struct real_format pdp11_d_format = + { + encode_pdp11_d, + decode_pdp11_d, + 2, + 56, + 56, + -127, + 127, + 15, + 15, + false, + false, + false, + false, + false, + false, + false, + false + }; + +static void +encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, + const REAL_VALUE_TYPE *r) +{ + (*vax_f_format.encode) (fmt, buf, r); + buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); +} + +static void +decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, + REAL_VALUE_TYPE *r, const long *buf) +{ + long tbuf; + tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); + (*vax_f_format.decode) (fmt, r, &tbuf); +} + +static void +encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, + const REAL_VALUE_TYPE *r) +{ + (*vax_d_format.encode) (fmt, buf, r); + buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); + buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); +} + +static void +decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, + REAL_VALUE_TYPE *r, const long *buf) +{ + long tbuf[2]; + tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); + tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); + (*vax_d_format.decode) (fmt, r, tbuf); +} + +/* This is where the condition code register lives. */ +/* rtx cc0_reg_rtx; - no longer needed? */ + +static bool pdp11_handle_option (size_t, const char *, int); +static void pdp11_option_init_struct (struct gcc_options *); +static const char *singlemove_string (rtx *); +static bool pdp11_assemble_integer (rtx, unsigned int, int); +static void pdp11_output_function_prologue (FILE *, HOST_WIDE_INT); +static void pdp11_output_function_epilogue (FILE *, HOST_WIDE_INT); +static bool pdp11_rtx_costs (rtx, int, int, int *, bool); +static bool pdp11_return_in_memory (const_tree, const_tree); +static rtx pdp11_function_value (const_tree, const_tree, bool); +static rtx pdp11_libcall_value (enum machine_mode, const_rtx); +static bool pdp11_function_value_regno_p (const unsigned int); +static void pdp11_trampoline_init (rtx, tree, rtx); +static rtx pdp11_function_arg (CUMULATIVE_ARGS *, enum machine_mode, + const_tree, bool); +static void pdp11_function_arg_advance (CUMULATIVE_ARGS *, + enum machine_mode, const_tree, bool); +static void pdp11_conditional_register_usage (void); + +/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ + +static const struct default_options pdp11_option_optimization_table[] = + { + { OPT_LEVELS_3_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + +/* Initialize the GCC target structure. */ +#undef TARGET_ASM_BYTE_OP +#define TARGET_ASM_BYTE_OP NULL +#undef TARGET_ASM_ALIGNED_HI_OP +#define TARGET_ASM_ALIGNED_HI_OP NULL +#undef TARGET_ASM_ALIGNED_SI_OP +#define TARGET_ASM_ALIGNED_SI_OP NULL +#undef TARGET_ASM_INTEGER +#define TARGET_ASM_INTEGER pdp11_assemble_integer + +#undef TARGET_ASM_FUNCTION_PROLOGUE +#define TARGET_ASM_FUNCTION_PROLOGUE pdp11_output_function_prologue +#undef TARGET_ASM_FUNCTION_EPILOGUE +#define TARGET_ASM_FUNCTION_EPILOGUE pdp11_output_function_epilogue + +#undef TARGET_ASM_OPEN_PAREN +#define TARGET_ASM_OPEN_PAREN "[" +#undef TARGET_ASM_CLOSE_PAREN +#define TARGET_ASM_CLOSE_PAREN "]" + +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS \ + (MASK_FPU | MASK_45 | TARGET_UNIX_ASM_DEFAULT) +#undef TARGET_HANDLE_OPTION +#define TARGET_HANDLE_OPTION pdp11_handle_option +#undef TARGET_OPTION_OPTIMIZATION_TABLE +#define TARGET_OPTION_OPTIMIZATION_TABLE pdp11_option_optimization_table +#undef TARGET_OPTION_INIT_STRUCT +#define TARGET_OPTION_INIT_STRUCT pdp11_option_init_struct + +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS pdp11_rtx_costs + +#undef TARGET_FUNCTION_ARG +#define TARGET_FUNCTION_ARG pdp11_function_arg +#undef TARGET_FUNCTION_ARG_ADVANCE +#define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance + +#undef TARGET_RETURN_IN_MEMORY +#define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory + +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE pdp11_function_value +#undef TARGET_LIBCALL_VALUE +#define TARGET_LIBCALL_VALUE pdp11_libcall_value +#undef TARGET_FUNCTION_VALUE_REGNO_P +#define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p + +#undef TARGET_TRAMPOLINE_INIT +#define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init + +#undef TARGET_SECONDARY_RELOAD +#define TARGET_SECONDARY_RELOAD pdp11_secondary_reload + +#undef TARGET_REGISTER_MOVE_COST +#define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost + +#undef TARGET_PREFERRED_RELOAD_CLASS +#define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class + +#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS +#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class + +#undef TARGET_LEGITIMATE_ADDRESS_P +#define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p + +#undef TARGET_CONDITIONAL_REGISTER_USAGE +#define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage + +#undef TARGET_ASM_FUNCTION_SECTION +#define TARGET_ASM_FUNCTION_SECTION pdp11_function_section + +#undef TARGET_PRINT_OPERAND +#define TARGET_PRINT_OPERAND pdp11_asm_print_operand + +#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P +#define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p + +/* Implement TARGET_HANDLE_OPTION. */ + +static bool +pdp11_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED) +{ + switch (code) + { + case OPT_m10: + target_flags &= ~(MASK_40 | MASK_45); + return true; + + default: + return true; + } +} + +/* Implement TARGET_OPTION_INIT_STRUCT. */ + +static void +pdp11_option_init_struct (struct gcc_options *opts) +{ + opts->x_flag_finite_math_only = 0; + opts->x_flag_trapping_math = 0; + opts->x_flag_signaling_nans = 0; +} + +/* + stream is a stdio stream to output the code to. + size is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. +*/ + +static void +pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size) +{ + HOST_WIDE_INT fsize = ((size) + 1) & ~1; + int regno; + int via_ac = -1; + + fprintf (stream, + "\n\t; /* function prologue %s*/\n", + current_function_name ()); + + /* if we are outputting code for main, + the switch FPU to right mode if TARGET_FPU */ + if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU) + { + fprintf(stream, + "\t;/* switch cpu to double float, single integer */\n"); + fprintf(stream, "\tsetd\n"); + fprintf(stream, "\tseti\n\n"); + } + + if (frame_pointer_needed) + { + fprintf(stream, "\tmov r5, -(sp)\n"); + fprintf(stream, "\tmov sp, r5\n"); + } + else + { + /* DON'T SAVE FP */ + } + + /* make frame */ + if (fsize) + asm_fprintf (stream, "\tsub $%#wo, sp\n", fsize); + + /* save CPU registers */ + for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++) + if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) + if (! ((regno == FRAME_POINTER_REGNUM) + && frame_pointer_needed)) + fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]); + /* fpu regs saving */ + + /* via_ac specifies the ac to use for saving ac4, ac5 */ + via_ac = -1; + + for (regno = AC0_REGNUM; regno <= AC5_REGNUM ; regno++) + { + /* ac0 - ac3 */ + if (LOAD_FPU_REG_P(regno) + && df_regs_ever_live_p (regno) + && ! call_used_regs[regno]) + { + fprintf (stream, "\tstd %s, -(sp)\n", reg_names[regno]); + via_ac = regno; + } + + /* maybe make ac4, ac5 call used regs?? */ + /* ac4 - ac5 */ + if (NO_LOAD_FPU_REG_P(regno) + && df_regs_ever_live_p (regno) + && ! call_used_regs[regno]) + { + gcc_assert (via_ac != -1); + fprintf (stream, "\tldd %s, %s\n", + reg_names[regno], reg_names[via_ac]); + fprintf (stream, "\tstd %s, -(sp)\n", reg_names[via_ac]); + } + } + + fprintf (stream, "\t;/* end of prologue */\n\n"); +} + +/* + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. */ + +/* maybe we can make leaf functions faster by switching to the + second register file - this way we don't have to save regs! + leaf functions are ~ 50% of all functions (dynamically!) + + set/clear bit 11 (dec. 2048) of status word for switching register files - + but how can we do this? the pdp11/45 manual says bit may only + be set (p.24), but not cleared! + + switching to kernel is probably more expensive, so we'll leave it + like this and not use the second set of registers... + + maybe as option if you want to generate code for kernel mode? */ + +static void +pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size) +{ + HOST_WIDE_INT fsize = ((size) + 1) & ~1; + int i, j, k; + + int via_ac; + + fprintf (stream, "\n\t; /*function epilogue */\n"); + + if (frame_pointer_needed) + { + /* hope this is safe - m68k does it also .... */ + df_set_regs_ever_live (FRAME_POINTER_REGNUM, false); + + for (i = PC_REGNUM, j = 0 ; i >= 0 ; i--) + if (df_regs_ever_live_p (i) && ! call_used_regs[i]) + j++; + + /* remember # of pushed bytes for CPU regs */ + k = 2*j; + + /* change fp -> r5 due to the compile error on libgcc2.c */ + for (i = PC_REGNUM ; i >= R0_REGNUM ; i--) + if (df_regs_ever_live_p (i) && ! call_used_regs[i]) + fprintf(stream, "\tmov %#" HOST_WIDE_INT_PRINT "o(r5), %s\n", + (-fsize-2*j--)&0xffff, reg_names[i]); + + /* get ACs */ + via_ac = AC5_REGNUM; + + for (i = AC5_REGNUM; i >= AC0_REGNUM; i--) + if (df_regs_ever_live_p (i) && ! call_used_regs[i]) + { + via_ac = i; + k += 8; + } + + for (i = AC5_REGNUM; i >= AC0_REGNUM; i--) + { + if (LOAD_FPU_REG_P(i) + && df_regs_ever_live_p (i) + && ! call_used_regs[i]) + { + fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n", + (-fsize-k)&0xffff, reg_names[i]); + k -= 8; + } + + if (NO_LOAD_FPU_REG_P(i) + && df_regs_ever_live_p (i) + && ! call_used_regs[i]) + { + gcc_assert (LOAD_FPU_REG_P(via_ac)); + + fprintf(stream, "\tldd %#" HOST_WIDE_INT_PRINT "o(r5), %s\n", + (-fsize-k)&0xffff, reg_names[via_ac]); + fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]); + k -= 8; + } + } + + fprintf(stream, "\tmov r5, sp\n"); + fprintf (stream, "\tmov (sp)+, r5\n"); + } + else + { + via_ac = AC5_REGNUM; + + /* get ACs */ + for (i = AC5_REGNUM; i >= AC0_REGNUM; i--) + if (df_regs_ever_live_p (i) && ! call_used_regs[i]) + via_ac = i; + + for (i = AC5_REGNUM; i >= AC0_REGNUM; i--) + { + if (LOAD_FPU_REG_P(i) + && df_regs_ever_live_p (i) + && ! call_used_regs[i]) + fprintf(stream, "\tldd (sp)+, %s\n", reg_names[i]); + + if (NO_LOAD_FPU_REG_P(i) + && df_regs_ever_live_p (i) + && ! call_used_regs[i]) + { + gcc_assert (LOAD_FPU_REG_P(via_ac)); + + fprintf(stream, "\tldd (sp)+, %s\n", reg_names[via_ac]); + fprintf(stream, "\tstd %s, %s\n", reg_names[via_ac], reg_names[i]); + } + } + + for (i = PC_REGNUM; i >= 0; i--) + if (df_regs_ever_live_p (i) && !call_used_regs[i]) + fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]); + + if (fsize) + fprintf((stream), "\tadd $%#" HOST_WIDE_INT_PRINT "o, sp\n", + (fsize)&0xffff); + } + + fprintf (stream, "\trts pc\n"); + fprintf (stream, "\t;/* end of epilogue*/\n\n\n"); +} + +/* Return the best assembler insn template + for moving operands[1] into operands[0] as a fullword. */ +static const char * +singlemove_string (rtx *operands) +{ + if (operands[1] != const0_rtx) + return "mov %1,%0"; + + return "clr %0"; +} + + +/* Expand multi-word operands (SImode or DImode) into the 2 or 4 + corresponding HImode operands. The number of operands is given + as the third argument, and the required order of the parts as + the fourth argument. */ +bool +pdp11_expand_operands (rtx *operands, rtx exops[][2], int opcount, + pdp11_action *action, pdp11_partorder order) +{ + int words, op, w, i, sh; + pdp11_partorder useorder; + bool sameoff = false; + enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype; + REAL_VALUE_TYPE r; + long sval[2]; + + words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; + + /* If either piece order is accepted and one is pre-decrement + while the other is post-increment, set order to be high order + word first. That will force the pre-decrement to be turned + into a pointer adjust, then offset addressing. + Otherwise, if either operand uses pre-decrement, that means + the order is low order first. + Otherwise, if both operands are registers and destination is + higher than source and they overlap, do low order word (highest + register number) first. */ + useorder = either; + if (opcount == 2) + { + if (!REG_P (operands[0]) && !REG_P (operands[1]) && + !(CONSTANT_P (operands[1]) || + GET_CODE (operands[1]) == CONST_DOUBLE) && + ((GET_CODE (XEXP (operands[0], 0)) == POST_INC && + GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) || + (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && + GET_CODE (XEXP (operands[1], 0)) == POST_INC))) + useorder = big; + else if ((!REG_P (operands[0]) && + GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) || + (!REG_P (operands[1]) && + !(CONSTANT_P (operands[1]) || + GET_CODE (operands[1]) == CONST_DOUBLE) && + GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) + useorder = little; + else if (REG_P (operands[0]) && REG_P (operands[1]) && + REGNO (operands[0]) > REGNO (operands[1]) && + REGNO (operands[0]) < REGNO (operands[1]) + words) + useorder = little; + + /* Check for source == offset from register and dest == push of + the same register. In that case, we have to use the same + offset (the one for the low order word) for all words, because + the push increases the offset to each source word. + In theory there are other cases like this, for example dest == pop, + but those don't occur in real life so ignore those. */ + if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + sameoff = true; + } + + /* If the caller didn't specify order, use the one we computed, + or high word first if we don't care either. If the caller did + specify, verify we don't have a problem with that order. + (If it matters to the caller, constraints need to be used to + ensure this case doesn't occur). */ + if (order == either) + order = (useorder == either) ? big : useorder; + else + gcc_assert (useorder == either || useorder == order); + + + for (op = 0; op < opcount; op++) + { + /* First classify the operand. */ + if (REG_P (operands[op])) + optype = REGOP; + else if (CONSTANT_P (operands[op]) + || GET_CODE (operands[op]) == CONST_DOUBLE) + optype = CNSTOP; + else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC) + optype = POPOP; + else if (GET_CODE (XEXP (operands[op], 0)) == PRE_DEC) + optype = PUSHOP; + else if (!reload_in_progress || offsettable_memref_p (operands[op])) + optype = OFFSOP; + else if (GET_CODE (operands[op]) == MEM) + optype = MEMOP; + else + optype = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Return failure for such cases. */ + if (optype == RNDOP) + return false; + + if (action != NULL) + action[op] = no_action; + + /* If the operand uses pre-decrement addressing but we + want to get the parts high order first, + decrement the former register explicitly + and change the operand into ordinary indexing. */ + if (optype == PUSHOP && order == big) + { + gcc_assert (action != NULL); + action[op] = dec_before; + operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), + XEXP (XEXP (operands[op], 0), 0)); + optype = OFFSOP; + } + /* If the operand uses post-increment mode but we want + to get the parts low order first, change the operand + into ordinary indexing and remember to increment + the register explicitly when we're done. */ + else if (optype == POPOP && order == little) + { + gcc_assert (action != NULL); + action[op] = inc_after; + operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), + XEXP (XEXP (operands[op], 0), 0)); + optype = OFFSOP; + } + + if (GET_CODE (operands[op]) == CONST_DOUBLE) + { + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[op]); + REAL_VALUE_TO_TARGET_DOUBLE (r, sval); + } + + for (i = 0; i < words; i++) + { + if (order == big) + w = i; + else if (sameoff) + w = words - 1; + else + w = words - 1 - i; + + /* Set the output operand to be word "w" of the input. */ + if (optype == REGOP) + exops[i][op] = gen_rtx_REG (HImode, REGNO (operands[op]) + w); + else if (optype == OFFSOP) + exops[i][op] = adjust_address (operands[op], HImode, w * 2); + else if (optype == CNSTOP) + { + if (GET_CODE (operands[op]) == CONST_DOUBLE) + { + sh = 16 - (w & 1) * 16; + exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff); + } + else + { + sh = ((words - 1 - w) * 16); + exops[i][op] = gen_rtx_CONST_INT (HImode, trunc_int_for_mode (INTVAL(operands[op]) >> sh, HImode)); + } + } + else + exops[i][op] = operands[op]; + } + } + return true; +} + +/* Output assembler code to perform a multiple-word move insn + with operands OPERANDS. This moves 2 or 4 words depending + on the machine mode of the operands. */ + +const char * +output_move_multiple (rtx *operands) +{ + rtx exops[4][2]; + pdp11_action action[2]; + int i, words; + + words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; + + pdp11_expand_operands (operands, exops, 2, action, either); + + /* Check for explicit decrement before. */ + if (action[0] == dec_before) + { + operands[0] = XEXP (operands[0], 0); + output_asm_insn ("sub $4,%0", operands); + } + if (action[1] == dec_before) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn ("sub $4,%1", operands); + } + + /* Do the words. */ + for (i = 0; i < words; i++) + output_asm_insn (singlemove_string (exops[i]), exops[i]); + + /* Check for increment after. */ + if (action[0] == inc_after) + { + operands[0] = XEXP (operands[0], 0); + output_asm_insn ("add $4,%0", operands); + } + if (action[1] == inc_after) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn ("add $4,%1", operands); + } + + return ""; +} + +/* Output an ascii string. */ +void +output_ascii (FILE *file, const char *p, int size) +{ + int i; + + /* This used to output .byte "string", which doesn't work with the UNIX + assembler and I think not with DEC ones either. */ + fprintf (file, "\t.byte "); + + for (i = 0; i < size; i++) + { + register int c = p[i]; + if (c < 0) + c += 256; + fprintf (file, "%#o", c); + if (i < size - 1) + putc (',', file); + } + putc ('\n', file); +} + + +void +pdp11_asm_output_var (FILE *file, const char *name, int size, + int align, bool global) +{ + if (align > 8) + fprintf (file, "\n\t.even\n"); + if (global) + { + fprintf (file, ".globl "); + assemble_name (file, name); + } + fprintf (file, "\n"); + assemble_name (file, name); + fprintf (file, ": .=.+ %#ho\n", (unsigned short)size); +} + +static void +pdp11_asm_print_operand (FILE *file, rtx x, int code) +{ + REAL_VALUE_TYPE r; + long sval[2]; + + if (code == '#') + fprintf (file, "#"); + else if (code == '@') + { + if (TARGET_UNIX_ASM) + fprintf (file, "*"); + else + fprintf (file, "@"); + } + else if (GET_CODE (x) == REG) + fprintf (file, "%s", reg_names[REGNO (x)]); + else if (GET_CODE (x) == MEM) + output_address (XEXP (x, 0)); + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != SImode) + { + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_TARGET_DOUBLE (r, sval); + fprintf (file, "$%#lo", sval[0] >> 16); + } + else + { + putc ('$', file); + output_addr_const_pdp11 (file, x); + } +} + +static bool +pdp11_asm_print_operand_punct_valid_p (unsigned char c) +{ + return (c == '#' || c == '@'); +} + +void +print_operand_address (FILE *file, register rtx addr) +{ + register rtx breg; + rtx offset; + int again = 0; + + retry: + + switch (GET_CODE (addr)) + { + case MEM: + if (TARGET_UNIX_ASM) + fprintf (file, "*"); + else + fprintf (file, "@"); + addr = XEXP (addr, 0); + again = 1; + goto retry; + + case REG: + fprintf (file, "(%s)", reg_names[REGNO (addr)]); + break; + + case PRE_MODIFY: + case PRE_DEC: + fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); + break; + + case POST_MODIFY: + case POST_INC: + fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); + break; + + case PLUS: + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) + || GET_CODE (XEXP (addr, 0)) == MEM) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) + || GET_CODE (XEXP (addr, 1)) == MEM) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) + ; + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + breg = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + breg = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG) + { + gcc_assert (breg == 0); + breg = addr; + addr = 0; + } + if (offset != 0) + { + gcc_assert (addr == 0); + addr = offset; + } + if (addr != 0) + output_addr_const_pdp11 (file, addr); + if (breg != 0) + { + gcc_assert (GET_CODE (breg) == REG); + fprintf (file, "(%s)", reg_names[REGNO (breg)]); + } + break; + + default: + if (!again && GET_CODE (addr) == CONST_INT) + { + /* Absolute (integer number) address. */ + if (!TARGET_UNIX_ASM) + fprintf (file, "@$"); + } + output_addr_const_pdp11 (file, addr); + } +} + +/* Target hook to assemble integer objects. We need to use the + pdp-specific version of output_addr_const. */ + +static bool +pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p) +{ + if (aligned_p) + switch (size) + { + case 1: + fprintf (asm_out_file, "\t.byte\t"); + output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff)); +; + fprintf (asm_out_file, " /* char */\n"); + return true; + + case 2: + fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t"); + output_addr_const_pdp11 (asm_out_file, x); + fprintf (asm_out_file, " /* short */\n"); + return true; + } + return default_assemble_integer (x, size, aligned_p); +} + + +/* register move costs, indexed by regs */ + +static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] = +{ + /* NO MUL GEN LFPU NLFPU FPU ALL */ + +/* NO */ { 0, 0, 0, 0, 0, 0, 0}, +/* MUL */ { 0, 2, 2, 22, 22, 22, 22}, +/* GEN */ { 0, 2, 2, 22, 22, 22, 22}, +/* LFPU */ { 0, 22, 22, 2, 2, 2, 22}, +/* NLFPU */ { 0, 22, 22, 2, 10, 10, 22}, +/* FPU */ { 0, 22, 22, 2, 10, 10, 22}, +/* ALL */ { 0, 22, 22, 22, 22, 22, 22} +} ; + + +/* -- note that some moves are tremendously expensive, + because they require lots of tricks! do we have to + charge the costs incurred by secondary reload class + -- as we do here with 10 -- or not ? */ + +static int +pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, + reg_class_t c1, reg_class_t c2) +{ + return move_costs[(int)c1][(int)c2]; +} + +static bool +pdp11_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total, + bool speed ATTRIBUTE_UNUSED) +{ + switch (code) + { + case CONST_INT: + if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1) + { + *total = 0; + return true; + } + /* FALLTHRU */ + + case CONST: + case LABEL_REF: + case SYMBOL_REF: + /* Twice as expensive as REG. */ + *total = 2; + return true; + + case CONST_DOUBLE: + /* Twice (or 4 times) as expensive as 16 bit. */ + *total = 4; + return true; + + case MULT: + /* ??? There is something wrong in MULT because MULT is not + as cheap as total = 2 even if we can shift! */ + /* If optimizing for size make mult etc cheap, but not 1, so when + in doubt the faster insn is chosen. */ + if (optimize_size) + *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (11); + return false; + + case DIV: + if (optimize_size) + *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (25); + return false; + + case MOD: + if (optimize_size) + *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (26); + return false; + + case ABS: + /* Equivalent to length, so same for optimize_size. */ + *total = COSTS_N_INSNS (3); + return false; + + case ZERO_EXTEND: + /* Only used for qi->hi. */ + *total = COSTS_N_INSNS (1); + return false; + + case SIGN_EXTEND: + if (GET_MODE (x) == HImode) + *total = COSTS_N_INSNS (1); + else if (GET_MODE (x) == SImode) + *total = COSTS_N_INSNS (6); + else + *total = COSTS_N_INSNS (2); + return false; + + case ASHIFT: + case LSHIFTRT: + case ASHIFTRT: + if (optimize_size) + *total = COSTS_N_INSNS (1); + else if (GET_MODE (x) == QImode) + { + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + *total = COSTS_N_INSNS (8); /* worst case */ + else + *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))); + } + else if (GET_MODE (x) == HImode) + { + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + if (abs (INTVAL (XEXP (x, 1))) == 1) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); + } + else + *total = COSTS_N_INSNS (10); /* worst case */ + } + else if (GET_MODE (x) == SImode) + { + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); + else /* worst case */ + *total = COSTS_N_INSNS (18); + } + return false; + + default: + return false; + } +} + +const char * +output_jump (enum rtx_code code, int inv, int length) +{ + static int x = 0; + + static char buf[1000]; + const char *pos, *neg; + + if (cc_prev_status.flags & CC_NO_OVERFLOW) + { + switch (code) + { + case GTU: code = GT; break; + case LTU: code = LT; break; + case GEU: code = GE; break; + case LEU: code = LE; break; + default: ; + } + } + switch (code) + { + case EQ: pos = "beq", neg = "bne"; break; + case NE: pos = "bne", neg = "beq"; break; + case GT: pos = "bgt", neg = "ble"; break; + case GTU: pos = "bhi", neg = "blos"; break; + case LT: pos = "blt", neg = "bge"; break; + case LTU: pos = "blo", neg = "bhis"; break; + case GE: pos = "bge", neg = "blt"; break; + case GEU: pos = "bhis", neg = "blo"; break; + case LE: pos = "ble", neg = "bgt"; break; + case LEU: pos = "blos", neg = "bhi"; break; + default: gcc_unreachable (); + } + +#if 0 +/* currently we don't need this, because the tstdf and cmpdf + copy the condition code immediately, and other float operations are not + yet recognized as changing the FCC - if so, then the length-cost of all + jump insns increases by one, because we have to potentially copy the + FCC! */ + if (cc_status.flags & CC_IN_FPU) + output_asm_insn("cfcc", NULL); +#endif + + switch (length) + { + case 2: + + sprintf(buf, "%s %%l1", inv ? neg : pos); + + return buf; + + case 6: + + sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x); + + x++; + + return buf; + + default: + + gcc_unreachable (); + } + +} + +void +notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED) +{ + if (GET_CODE (SET_DEST (exp)) == CC0) + { + cc_status.flags = 0; + cc_status.value1 = SET_DEST (exp); + cc_status.value2 = SET_SRC (exp); + } + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + } + else if (SET_DEST(exp) == pc_rtx) + { + /* jump */ + } + else if (GET_MODE (SET_DEST(exp)) == HImode + || GET_MODE (SET_DEST(exp)) == QImode) + { + cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + + if (cc_status.value1 && GET_CODE (cc_status.value1) == REG + && cc_status.value2 + && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) + cc_status.value2 = 0; + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM + && cc_status.value2 + && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + } + else + { + CC_STATUS_INIT; + } +} + + +int +simple_memory_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) +{ + rtx addr; + + /* Eliminate non-memory operations */ + if (GET_CODE (op) != MEM) + return FALSE; + +#if 0 + /* dword operations really put out 2 instructions, so eliminate them. */ + if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) + return FALSE; +#endif + + /* Decode the address now. */ + + indirection: + + addr = XEXP (op, 0); + + switch (GET_CODE (addr)) + { + case REG: + /* (R0) - no extra cost */ + return 1; + + case PRE_DEC: + case POST_INC: + /* -(R0), (R0)+ - cheap! */ + return 0; + + case MEM: + /* cheap - is encoded in addressing mode info! + + -- except for @(R0), which has to be @0(R0) !!! */ + + if (GET_CODE (XEXP (addr, 0)) == REG) + return 0; + + op=addr; + goto indirection; + + case CONST_INT: + case LABEL_REF: + case CONST: + case SYMBOL_REF: + /* @#address - extra cost */ + return 0; + + case PLUS: + /* X(R0) - extra cost */ + return 0; + + default: + break; + } + + return FALSE; +} + + +/* + * output a block move: + * + * operands[0] ... to + * operands[1] ... from + * operands[2] ... length + * operands[3] ... alignment + * operands[4] ... scratch register + */ + + +const char * +output_block_move(rtx *operands) +{ + static int count = 0; + char buf[200]; + int unroll; + int lastbyte = 0; + + /* Move of zero bytes is a NOP. */ + if (operands[2] == const0_rtx) + return ""; + + /* Look for moves by small constant byte counts, those we'll + expand to straight line code. */ + if (CONSTANT_P (operands[2])) + { + if (INTVAL (operands[2]) < 16 + && (!optimize_size || INTVAL (operands[2]) < 5) + && INTVAL (operands[3]) == 1) + { + register int i; + + for (i = 1; i <= INTVAL (operands[2]); i++) + output_asm_insn("movb (%1)+, (%0)+", operands); + + return ""; + } + else if (INTVAL(operands[2]) < 32 + && (!optimize_size || INTVAL (operands[2]) < 9) + && INTVAL (operands[3]) >= 2) + { + register int i; + + for (i = 1; i <= INTVAL (operands[2]) / 2; i++) + output_asm_insn ("mov (%1)+, (%0)+", operands); + if (INTVAL (operands[2]) & 1) + output_asm_insn ("movb (%1), (%0)", operands); + + return ""; + } + } + + /* Ideally we'd look for moves that are multiples of 4 or 8 + bytes and handle those by unrolling the move loop. That + makes for a lot of code if done at run time, but it's ok + for constant counts. Also, for variable counts we have + to worry about odd byte count with even aligned pointers. + On 11/40 and up we handle that case; on older machines + we don't and just use byte-wise moves all the time. */ + + if (CONSTANT_P (operands[2]) ) + { + if (INTVAL (operands[3]) < 2) + unroll = 0; + else + { + lastbyte = INTVAL (operands[2]) & 1; + + if (optimize_size || INTVAL (operands[2]) & 2) + unroll = 1; + else if (INTVAL (operands[2]) & 4) + unroll = 2; + else + unroll = 3; + } + + /* Loop count is byte count scaled by unroll. */ + operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll); + output_asm_insn ("mov %2, %4", operands); + } + else + { + /* Variable byte count; use the input register + as the scratch. */ + operands[4] = operands[2]; + + /* Decide whether to move by words, and check + the byte count for zero. */ + if (TARGET_40_PLUS && INTVAL (operands[3]) > 1) + { + unroll = 1; + output_asm_insn ("asr %4", operands); + } + else + { + unroll = 0; + output_asm_insn ("tst %4", operands); + } + sprintf (buf, "beq movestrhi%d", count + 1); + output_asm_insn (buf, NULL); + } + + /* Output the loop label. */ + sprintf (buf, "\nmovestrhi%d:", count); + output_asm_insn (buf, NULL); + + /* Output the appropriate move instructions. */ + switch (unroll) + { + case 0: + output_asm_insn ("movb (%1)+, (%0)+", operands); + break; + + case 1: + output_asm_insn ("mov (%1)+, (%0)+", operands); + break; + + case 2: + output_asm_insn ("mov (%1)+, (%0)+", operands); + output_asm_insn ("mov (%1)+, (%0)+", operands); + break; + + default: + output_asm_insn ("mov (%1)+, (%0)+", operands); + output_asm_insn ("mov (%1)+, (%0)+", operands); + output_asm_insn ("mov (%1)+, (%0)+", operands); + output_asm_insn ("mov (%1)+, (%0)+", operands); + break; + } + + /* Output the decrement and test. */ + if (TARGET_40_PLUS) + { + sprintf (buf, "sob %%4, movestrhi%d", count); + output_asm_insn (buf, operands); + } + else + { + output_asm_insn ("dec %4", operands); + sprintf (buf, "bgt movestrhi%d", count); + output_asm_insn (buf, NULL); + } + count ++; + + /* If constant odd byte count, move the last byte. */ + if (lastbyte) + output_asm_insn ("movb (%1), (%0)", operands); + else if (!CONSTANT_P (operands[2])) + { + /* Output the destination label for the zero byte count check. */ + sprintf (buf, "\nmovestrhi%d:", count); + output_asm_insn (buf, NULL); + count++; + + /* If we did word moves, check for trailing last byte. */ + if (unroll) + { + sprintf (buf, "bcc movestrhi%d", count); + output_asm_insn (buf, NULL); + output_asm_insn ("movb (%1), (%0)", operands); + sprintf (buf, "\nmovestrhi%d:", count); + output_asm_insn (buf, NULL); + count++; + } + } + + return ""; +} + +/* This function checks whether a real value can be encoded as + a literal, i.e., addressing mode 27. In that mode, real values + are one word values, so the remaining 48 bits have to be zero. */ +int +legitimate_const_double_p (rtx address) +{ + REAL_VALUE_TYPE r; + long sval[2]; + REAL_VALUE_FROM_CONST_DOUBLE (r, address); + REAL_VALUE_TO_TARGET_DOUBLE (r, sval); + if ((sval[0] & 0xffff) == 0 && sval[1] == 0) + return 1; + return 0; +} + +/* Implement CANNOT_CHANGE_MODE_CLASS. */ +bool +pdp11_cannot_change_mode_class (enum machine_mode from, + enum machine_mode to, + enum reg_class rclass) +{ + /* Also, FPU registers contain a whole float value and the parts of + it are not separately accessible. + + So we disallow all mode changes involving FPRs. */ + if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to)) + return true; + + return reg_classes_intersect_p (FPU_REGS, rclass); +} + +/* TARGET_PREFERRED_RELOAD_CLASS + + Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + +loading is easier into LOAD_FPU_REGS than FPU_REGS! */ + +static reg_class_t +pdp11_preferred_reload_class (rtx x, reg_class_t rclass) +{ + if (rclass == FPU_REGS) + return LOAD_FPU_REGS; + if (rclass == ALL_REGS) + { + if (FLOAT_MODE_P (GET_MODE (x))) + return LOAD_FPU_REGS; + else + return GENERAL_REGS; + } + return rclass; +} + +/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS + + Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + +loading is easier into LOAD_FPU_REGS than FPU_REGS! */ + +static reg_class_t +pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass) +{ + if (rclass == FPU_REGS) + return LOAD_FPU_REGS; + if (rclass == ALL_REGS) + { + if (FLOAT_MODE_P (GET_MODE (x))) + return LOAD_FPU_REGS; + else + return GENERAL_REGS; + } + return rclass; +} + + +/* TARGET_SECONDARY_RELOAD. + + FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an + intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else + can be loade/stored directly. */ +static reg_class_t +pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, + rtx x, + reg_class_t reload_class, + enum machine_mode reload_mode ATTRIBUTE_UNUSED, + secondary_reload_info *sri ATTRIBUTE_UNUSED) +{ + if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG || + REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS) + return NO_REGS; + + return LOAD_FPU_REGS; +} + +/* Target routine to check if register to register move requires memory. + + The answer is yes if we're going between general register and FPU + registers. The mode doesn't matter in making this check. +*/ +bool +pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2, + enum machine_mode mode ATTRIBUTE_UNUSED) +{ + int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || + c1 == FPU_REGS); + int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || + c2 == FPU_REGS); + + return (fromfloat != tofloat); +} + +/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + +*/ + +static bool +pdp11_legitimate_address_p (enum machine_mode mode, + rtx operand, bool strict) +{ + rtx xfoob; + + /* accept @#address */ + if (CONSTANT_ADDRESS_P (operand)) + return true; + + switch (GET_CODE (operand)) + { + case REG: + /* accept (R0) */ + return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand)); + + case PLUS: + /* accept X(R0) */ + return GET_CODE (XEXP (operand, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))) + && CONSTANT_ADDRESS_P (XEXP (operand, 1)); + + case PRE_DEC: + /* accept -(R0) */ + return GET_CODE (XEXP (operand, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); + + case POST_INC: + /* accept (R0)+ */ + return GET_CODE (XEXP (operand, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); + + case PRE_MODIFY: + /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ + return GET_CODE (XEXP (operand, 0)) == REG + && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM + && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS + && GET_CODE (XEXP (xfoob, 0)) == REG + && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM + && CONSTANT_P (XEXP (xfoob, 1)) + && INTVAL (XEXP (xfoob,1)) == -2; + + case POST_MODIFY: + /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ + return GET_CODE (XEXP (operand, 0)) == REG + && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM + && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS + && GET_CODE (XEXP (xfoob, 0)) == REG + && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM + && CONSTANT_P (XEXP (xfoob, 1)) + && INTVAL (XEXP (xfoob,1)) == 2; + + case MEM: + /* handle another level of indirection ! */ + xfoob = XEXP (operand, 0); + + /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently + also forbidden for float, because we have to handle this + in output_move_double and/or output_move_quad() - we could + do it, but currently it's not worth it!!! + now that DFmode cannot go into CPU register file, + maybe I should allow float ... + but then I have to handle memory-to-memory moves in movdf ?? */ + if (GET_MODE_BITSIZE(mode) > 16) + return false; + + /* accept @address */ + if (CONSTANT_ADDRESS_P (xfoob)) + return true; + + switch (GET_CODE (xfoob)) + { + case REG: + /* accept @(R0) - which is @0(R0) */ + return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob)); + + case PLUS: + /* accept @X(R0) */ + return GET_CODE (XEXP (xfoob, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))) + && CONSTANT_ADDRESS_P (XEXP (xfoob, 1)); + + case PRE_DEC: + /* accept @-(R0) */ + return GET_CODE (XEXP (xfoob, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); + + case POST_INC: + /* accept @(R0)+ */ + return GET_CODE (XEXP (xfoob, 0)) == REG + && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); + + default: + /* anything else is invalid */ + return false; + } + + default: + /* anything else is invalid */ + return false; + } +} + +/* Return the class number of the smallest class containing + reg number REGNO. */ +enum reg_class +pdp11_regno_reg_class (int regno) +{ + if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) + return GENERAL_REGS; + else if (regno > AC3_REGNUM) + return NO_LOAD_FPU_REGS; + else if (regno >= AC0_REGNUM) + return LOAD_FPU_REGS; + else if (regno & 1) + return MUL_REGS; + else + return GENERAL_REGS; +} + + +static int +pdp11_sp_frame_offset (void) +{ + int offset = 0, regno; + offset = get_frame_size(); + for (regno = 0; regno <= PC_REGNUM; regno++) + if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) + offset += 2; + for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) + if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) + offset += 8; + + return offset; +} + +/* Return the offset between two registers, one to be eliminated, and the other + its replacement, at the start of a routine. */ + +int +pdp11_initial_elimination_offset (int from, int to) +{ + int spoff; + + if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) + return 4; + else if (from == FRAME_POINTER_REGNUM + && to == HARD_FRAME_POINTER_REGNUM) + return 0; + else + { + gcc_assert (to == STACK_POINTER_REGNUM); + + /* Get the size of the register save area. */ + spoff = pdp11_sp_frame_offset (); + if (from == FRAME_POINTER_REGNUM) + return spoff; + + gcc_assert (from == ARG_POINTER_REGNUM); + + /* If there is a frame pointer, that is saved too. */ + if (frame_pointer_needed) + spoff += 2; + + /* Account for the saved PC in the function call. */ + return spoff + 2; + } +} + +/* A copy of output_addr_const modified for pdp11 expression syntax. + output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't + use, and for debugging output, which we don't support with this port either. + So this copy should get called whenever needed. +*/ +void +output_addr_const_pdp11 (FILE *file, rtx x) +{ + char buf[256]; + int i; + + restart: + switch (GET_CODE (x)) + { + case PC: + gcc_assert (flag_pic); + putc ('.', file); + break; + + case SYMBOL_REF: + assemble_name (file, XSTR (x, 0)); + break; + + case LABEL_REF: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (file, buf); + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (file, buf); + break; + + case CONST_INT: + i = INTVAL (x); + if (i < 0) + { + i = -i; + fprintf (file, "-"); + } + fprintf (file, "%#o", i & 0xffff); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_addr_const_pdp11 (file, XEXP (x, 0)); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %o if the number is one word and positive. */ + gcc_assert (!CONST_DOUBLE_HIGH (x)); + fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (e.g. masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_addr_const_pdp11 (file, XEXP (x, 1)); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_addr_const_pdp11 (file, XEXP (x, 0)); + } + else + { + output_addr_const_pdp11 (file, XEXP (x, 0)); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_addr_const_pdp11 (file, XEXP (x, 1)); + } + break; + + case MINUS: + /* Avoid outputting things like x-x or x+5-x, + since some assemblers can't handle that. */ + x = simplify_subtraction (x); + if (GET_CODE (x) != MINUS) + goto restart; + + output_addr_const_pdp11 (file, XEXP (x, 0)); + if (GET_CODE (XEXP (x, 1)) != CONST_INT + || INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "-"); + output_addr_const_pdp11 (file, XEXP (x, 1)); + break; + + case ZERO_EXTEND: + case SIGN_EXTEND: + output_addr_const_pdp11 (file, XEXP (x, 0)); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* Worker function for TARGET_RETURN_IN_MEMORY. */ + +static bool +pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) +{ + /* Integers 32 bits and under, and scalar floats (if FPU), are returned + in registers. The rest go into memory. */ + return (TYPE_MODE (type) == DImode + || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0) + || TREE_CODE (type) == VECTOR_TYPE + || COMPLEX_MODE_P (TYPE_MODE (type))); +} + +/* Worker function for TARGET_FUNCTION_VALUE. + + On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */ + +static rtx +pdp11_function_value (const_tree valtype, + const_tree fntype_or_decl ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) +{ + return gen_rtx_REG (TYPE_MODE (valtype), + BASE_RETURN_VALUE_REG(TYPE_MODE(valtype))); +} + +/* Worker function for TARGET_LIBCALL_VALUE. */ + +static rtx +pdp11_libcall_value (enum machine_mode mode, + const_rtx fun ATTRIBUTE_UNUSED) +{ + return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode)); +} + +/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. + + On the pdp, the first "output" reg is the only register thus used. + + maybe ac0 ? - as option someday! */ + +static bool +pdp11_function_value_regno_p (const unsigned int regno) +{ + return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM)); +} + +/* Worker function for TARGET_TRAMPOLINE_INIT. + + trampoline - how should i do it in separate i+d ? + have some allocate_trampoline magic??? + + the following should work for shared I/D: + + MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM + JMP @#FUNCTION 000137 0x0000 <- FUNCTION +*/ + +static void +pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) +{ + rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); + rtx mem; + + gcc_assert (!TARGET_SPLIT); + + mem = adjust_address (m_tramp, HImode, 0); + emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM)); + mem = adjust_address (m_tramp, HImode, 2); + emit_move_insn (mem, chain_value); + mem = adjust_address (m_tramp, HImode, 4); + emit_move_insn (mem, GEN_INT (000137)); + emit_move_insn (mem, fnaddr); +} + +/* Worker function for TARGET_FUNCTION_ARG. + + Determine where to put an argument to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +static rtx +pdp11_function_arg (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + const_tree type ATTRIBUTE_UNUSED, + bool named ATTRIBUTE_UNUSED) +{ + return NULL_RTX; +} + +/* Worker function for TARGET_FUNCTION_ARG_ADVANCE. + + Update the data in CUM to advance over an argument of mode MODE and + data type TYPE. (TYPE is null for libcalls where that information + may not be available.) */ + +static void +pdp11_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, + const_tree type, bool named ATTRIBUTE_UNUSED) +{ + *cum += (mode != BLKmode + ? GET_MODE_SIZE (mode) + : int_size_in_bytes (type)); +} + +/* Make sure everything's fine if we *don't* have an FPU. + This assumes that putting a register in fixed_regs will keep the + compiler's mitts completely off it. We don't bother to zero it out + of register classes. Also fix incompatible register naming with + the UNIX assembler. */ + +static void +pdp11_conditional_register_usage (void) +{ + int i; + HARD_REG_SET x; + if (!TARGET_FPU) + { + COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) + if (TEST_HARD_REG_BIT (x, i)) + fixed_regs[i] = call_used_regs[i] = 1; + } + + if (TARGET_AC0) + call_used_regs[AC0_REGNUM] = 1; + if (TARGET_UNIX_ASM) + { + /* Change names of FPU registers for the UNIX assembler. */ + reg_names[8] = "fr0"; + reg_names[9] = "fr1"; + reg_names[10] = "fr2"; + reg_names[11] = "fr3"; + reg_names[12] = "fr4"; + reg_names[13] = "fr5"; + } +} + +static section * +pdp11_function_section (tree decl ATTRIBUTE_UNUSED, + enum node_frequency freq ATTRIBUTE_UNUSED, + bool startup ATTRIBUTE_UNUSED, + bool exit ATTRIBUTE_UNUSED) +{ + return NULL; +} + +struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h new file mode 100644 index 000000000..fc36f5b67 --- /dev/null +++ b/gcc/config/pdp11/pdp11.h @@ -0,0 +1,685 @@ +/* Definitions of target machine for GNU compiler, for the pdp-11 + Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2004, 2005, + 2006, 2007, 2008, 2010 Free Software Foundation, Inc. + Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#define CONSTANT_POOL_BEFORE_FUNCTION 0 + +/* check whether load_fpu_reg or not */ +#define LOAD_FPU_REG_P(x) ((x) >= AC0_REGNUM && (x) <= AC3_REGNUM) +#define NO_LOAD_FPU_REG_P(x) ((x) == AC4_REGNUM || (x) == AC5_REGNUM) +#define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) +#define CPU_REG_P(x) ((x) <= PC_REGNUM) + +/* Names to predefine in the preprocessor for this target machine. */ + +#define TARGET_CPU_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("pdp11"); \ + } \ + while (0) + +/* Print subsidiary information on the compiler version in use. */ +#define TARGET_VERSION fprintf (stderr, " (pdp11)"); + + +/* Generate DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + +#define TARGET_40_PLUS (TARGET_40 || TARGET_45) +#define TARGET_10 (! TARGET_40_PLUS) + +#define TARGET_UNIX_ASM_DEFAULT 0 + +#define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0) + + + +/* TYPE SIZES */ +#define SHORT_TYPE_SIZE 16 +#define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) +#define LONG_TYPE_SIZE 32 +#define LONG_LONG_TYPE_SIZE 64 + +/* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit + of saving core for huge arrays - the definitions are + already in md - but floats can never reside in + an FPU register - we keep the FPU in double float mode + all the time !! */ +#define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64) +#define DOUBLE_TYPE_SIZE 64 +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* machine types from ansi */ +#define SIZE_TYPE "unsigned int" /* definition of size_t */ +#define WCHAR_TYPE "int" /* or long int???? */ +#define WCHAR_TYPE_SIZE 16 + +#define PTRDIFF_TYPE "int" + +/* target machine storage layout */ + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. */ +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is first. */ +#define WORDS_BIG_ENDIAN 1 + +/* Define that floats are in VAX order, not high word first as for ints. */ +#define FLOAT_WORDS_BIG_ENDIAN 0 + +/* Width of a word, in units (bytes). + + UNITS OR BYTES - seems like units */ +#define UNITS_PER_WORD 2 + +/* This machine doesn't use IEEE floats. */ +/* Because the pdp11 (at least Unix) convention for 32-bit ints is + big endian, opposite for what you need for float, the vax float + conversion routines aren't actually used directly. But the underlying + format is indeed the vax/pdp11 float format. */ +extern const struct real_format pdp11_f_format; +extern const struct real_format pdp11_d_format; + +/* Maximum sized of reasonable data type + DImode or Dfmode ...*/ +#define MAX_FIXED_MODE_SIZE 64 + +/* Allocation boundary (in *bits*) for storing pointers in memory. */ +#define POINTER_BOUNDARY 16 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 16 + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 16 + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY 16 + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY 16 + +/* No data type wants to be aligned rounder than this. */ +#define BIGGEST_ALIGNMENT 16 + +/* Define this if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 1 + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + we have 8 integer registers, plus 6 float + (don't use scratch float !) */ + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + + On the pdp, these are: + Reg 7 = pc; + reg 6 = sp; + reg 5 = fp; not necessarily! +*/ + +#define FIXED_REGISTERS \ +{0, 0, 0, 0, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0, 0, 1, 1 } + + + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +/* don't know about fp */ +#define CALL_USED_REGISTERS \ +{1, 1, 0, 0, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0, 0, 1, 1 } + + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. +*/ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ +((REGNO <= PC_REGNUM)? \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ + :1) + + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the pdp, the cpu registers can hold any mode other than float + (because otherwise we may end up being asked to move from CPU to FPU + register, which isn't a valid operation on the PDP11). + For CPU registers, check alignment. + + FPU accepts SF and DF but actually holds a DF - simplifies life! +*/ +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ +(((REGNO) <= PC_REGNUM)? \ + ((GET_MODE_BITSIZE(MODE) <= 16) \ + || (GET_MODE_BITSIZE(MODE) >= 32 && \ + !((REGNO) & 1) && !FLOAT_MODE_P (MODE))) \ + :FLOAT_MODE_P (MODE)) + + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ +#define MODES_TIEABLE_P(MODE1, MODE2) 0 + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* Register in which static-chain is passed to a function. */ +/* ??? - i don't want to give up a reg for this! */ +#define STATIC_CHAIN_REGNUM 4 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +/* The pdp has a couple of classes: + +MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication + (even numbered do 32-bit multiply) +LMUL_REGS long multiply registers (even numbered regs ) + (don't need them, all 32-bit regs are even numbered!) +GENERAL_REGS is all cpu +LOAD_FPU_REGS is the first four cpu regs, they are easier to load +NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them +FPU_REGS is all fpu regs +*/ + +enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES }; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* have to allow this till cmpsi/tstsi are fixed in a better way !! */ +#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true + +/* Since GENERAL_REGS is the same class as ALL_REGS, + don't give it a different class number; just make it an alias. */ + +/* #define GENERAL_REGS ALL_REGS */ + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0xc0ff}, {0x0f00}, {0x3000}, {0x3f00}, {0xffff}} + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +#define REGNO_REG_CLASS(REGNO) pdp11_regno_reg_class (REGNO) + +/* The class value for index registers, and the one for base regs. */ +#define INDEX_REG_CLASS GENERAL_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES { GENERAL_REGS, FPU_REGS, LIM_REG_CLASSES } + +/* Hook for testing if memory is needed for moving between registers. */ +#define SECONDARY_MEMORY_NEEDED(class1, class2, m) \ + pdp11_secondary_memory_needed (class1, class2, m) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ +((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ + 1 \ +) + +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + pdp11_cannot_change_mode_class (FROM, TO, CLASS) + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this to nonzero if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. +*/ +#define FRAME_GROWS_DOWNWARD 1 + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On the pdp11, the stack is on an even boundary */ +#define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1) + +/* current_first_parm_offset stores the # of registers pushed on the + stack */ +extern int current_first_parm_offset; + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 0 + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ +#define BASE_RETURN_VALUE_REG(MODE) \ + (FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM) + +/* 1 if N is a possible register number for function argument passing. + - not used on pdp */ + +#define FUNCTION_ARG_REGNO_P(N) 0 + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + +*/ + +#define CUMULATIVE_ARGS int + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + ...., the offset normally starts at 0, but starts at 1 word + when the function gets a structure-value-address as an + invisible first argument. */ + +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ + ((CUM) = 0) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ + gcc_unreachable (); + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + +extern int may_call_alloca; + +#define EXIT_IGNORE_STACK 1 + +/* Definitions for register eliminations. + + This is an array of structures. Each structure initializes one pair + of eliminable registers. The "from" register number is given first, + followed by "to". Eliminations of the same "from" register are listed + in order of preference. + + There are two registers that can always be eliminated on the pdp11. + The frame pointer and the arg pointer can be replaced by either the + hard frame pointer or to the stack pointer, depending upon the + circumstances. The hard frame pointer is not used before reload and + so it is not eligible for elimination. */ + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ + ((OFFSET) = pdp11_initial_elimination_offset ((FROM), (TO))) + + +/* Addressing modes, and classification of registers for them. */ + +#define HAVE_POST_INCREMENT 1 + +#define HAVE_PRE_DECREMENT 1 + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + ((REGNO) <= PC_REGNUM || (unsigned) reg_renumber[REGNO] <= PC_REGNUM || \ + (REGNO) == ARG_POINTER_REGNUM || (REGNO) == FRAME_POINTER_REGNUM) + +#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P (REGNO) + +/* Now macros that check whether X is a register and also, + strictly, whether it is in a specified class. +*/ + + + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 1 + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) \ + (GET_CODE (X) != CONST_DOUBLE || legitimate_const_double_p (X)) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ +#define REG_OK_FOR_INDEX_P(X) (1) +/* Nonzero if X is a hard reg that can be used as a base reg + or if it is a pseudo reg. */ +#define REG_OK_FOR_BASE_P(X) (1) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + +#endif + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE HImode + +/* Define this if a raw index is all that is needed for a + `tablejump' insn. */ +#define CASE_TAKES_INDEX_RAW + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. +*/ + +#define MOVE_MAX 2 + +/* Nonzero if access to memory by byte is slow and undesirable. - +*/ +#define SLOW_BYTE_ACCESS 0 + +/* Do not break .stabs pseudos into continuations. */ +#define DBX_CONTIN_LENGTH 0 + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, + return the mode to be used for the comparison. For floating-point, CCFPmode + should be used. */ + +#define SELECT_CC_MODE(OP,X,Y) \ +(GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode) + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode HImode + +/* A function address in a call instruction + is a word address (for indexing purposes) + so give the MEM rtx a word's mode. */ +#define FUNCTION_MODE HImode + +/* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on machines where ordinary constants are expensive + but a CALL with constant address is cheap. */ +/* #define NO_FUNCTION_CSE */ + + +/* Tell emit-rtl.c how to initialize special values on a per-function base. */ +extern struct rtx_def *cc0_reg_rtx; + +#define CC_STATUS_MDEP rtx + +#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +#define CC_IN_FPU 04000 + +/* Do UPDATE_CC if EXP is a set, used in + NOTICE_UPDATE_CC + + floats only do compare correctly, else nullify ... + + get cc0 out soon ... +*/ + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ +{ if (GET_CODE (EXP) == SET) \ + { \ + notice_update_cc_on_set(EXP, INSN); \ + } \ + else if (GET_CODE (EXP) == PARALLEL \ + && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ + { \ + notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \ + } \ + else if (GET_CODE (EXP) == CALL) \ + { /* all bets are off */ CC_STATUS_INIT; } \ + if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ + && cc_status.value2 \ + && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ + { \ + printf ("here!\n"); \ + cc_status.value2 = 0; \ + } \ +} + +/* Control the assembler format that we output. */ + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP "\t.text\n" + +/* Output before writable data. */ + +#define DATA_SECTION_ASM_OP "\t.data\n" + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +#define REGISTER_NAMES \ +{"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ + "ac0", "ac1", "ac2", "ac3", "ac4", "ac5", "fp", "ap" } + +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.globl " + +/* The prefix to add to user-visible assembler symbols. */ + +#define USER_LABEL_PREFIX "_" + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*%s_%lu", PREFIX, (unsigned long)(NUM)) + +#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ + output_ascii (FILE, P, SIZE) + +/* This is how to output an element of a case-vector that is absolute. */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE) + +/* This is how to output an element of a case-vector that is relative. + Don't define this if it is not supported. */ + +/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. + + who needs this???? +*/ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + switch (LOG) \ + { \ + case 0: \ + break; \ + case 1: \ + fprintf (FILE, "\t.even\n"); \ + break; \ + default: \ + gcc_unreachable (); \ + } + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.=.+ %#ho\n", (unsigned short)(SIZE)) + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ + pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, true) + + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ + pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, false) + +/* Print a memory address as an operand to reference that memory location. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + print_operand_address (FILE, ADDR) + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ +( \ + fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \ +) + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ +( \ + fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \ +) + +#define TRAMPOLINE_SIZE 8 +#define TRAMPOLINE_ALIGNMENT 16 + +/* there is no point in avoiding branches on a pdp, + since branches are really cheap - I just want to find out + how much difference the BRANCH_COST macro makes in code */ +#define BRANCH_COST(speed_p, predictable_p) (TARGET_BRANCH_CHEAP ? 0 : 1) + + +#define COMPARE_FLAG_MODE HImode diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md new file mode 100644 index 000000000..1c6542685 --- /dev/null +++ b/gcc/config/pdp11/pdp11.md @@ -0,0 +1,1386 @@ +;;- Machine description for the pdp11 for GNU C compiler +;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2004, 2005 +;; 2007, 2008, 2010 Free Software Foundation, Inc. +;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(include "predicates.md") +(include "constraints.md") + +(define_constants + [ + ;; Register numbers + (R0_REGNUM 0) + (RETVAL_REGNUM 0) + (HARD_FRAME_POINTER_REGNUM 5) + (STACK_POINTER_REGNUM 6) + (PC_REGNUM 7) + (AC0_REGNUM 8) + (AC3_REGNUM 11) + (AC4_REGNUM 12) + (AC5_REGNUM 13) + ;; The next two are not physical registers but are used for addressing + ;; arguments. + (FRAME_POINTER_REGNUM 14) + (ARG_POINTER_REGNUM 15) + (FIRST_PSEUDO_REGISTER 16) + ;; Branch offset limits, as byte offsets from instruction address + (MIN_BRANCH -254) + (MAX_BRANCH 256) + (MIN_SOB -126) + (MAX_SOB 0)]) + +;; HI is 16 bit +;; QI is 8 bit + +;; Integer modes supported on the PDP11, with a mapping from machine mode +;; to mnemonic suffix. SImode and DImode always are special cases. +(define_mode_iterator PDPint [QI HI]) +(define_mode_attr isfx [(QI "b") (HI "")]) + +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. + +;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code +;;- updates for most instructions. + +;;- Operand classes for the register allocator: + +;; Compare instructions. + +;; currently we only support df floats, which saves us quite some +;; hassle switching the FP mode! +;; we assume that CPU is always in long float mode, and +;; 16 bit integer mode - currently, the prologue for main does this, +;; but maybe we should just set up a NEW crt0 properly, +;; -- and what about signal handling code? +;; (we don't even let sf floats in the register file, so +;; we only should have to worry about truncating and widening +;; when going to memory) + +;; abort() call by g++ - must define libfunc for cmp_optab +;; and ucmp_optab for mode SImode, because we don't have that!!! +;; - yet since no libfunc is there, we abort () + +;; The only thing that remains to be done then is output +;; the floats in a way the assembler can handle it (and +;; if you're really into it, use a PDP11 float emulation +;; library to do floating point constant folding - but +;; I guess you'll get reasonable results even when not +;; doing this) +;; the last thing to do is fix the UPDATE_CC macro to check +;; for floating point condition codes, and set cc_status +;; properly, also setting the CC_IN_FCCR flag. + +;; define attributes +;; currently type is only fpu or arith or unknown, maybe branch later ? +;; default is arith +(define_attr "type" "unknown,arith,fp" (const_string "arith")) + +;; length default is 2 bytes each +(define_attr "length" "" (const_int 2)) + +;; a user's asm statement +(define_asm_attributes + [(set_attr "type" "unknown") +; length for asm is the max length per statement. That would be +; 3 words, for a two-operand instruction with extra word addressing +; modes for both operands. + (set_attr "length" "6")]) + +;; define function units + +;; arithmetic - values here immediately when next insn issued +;; or does it mean the number of cycles after this insn was issued? +;; how do I say that fpu insns use cpu also? (pre-interaction phase) + +;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0) +;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0) + +;; compare +(define_insn "*cmpdf" + [(set (cc0) + (compare (match_operand:DF 0 "general_operand" "fR,fR,Q,QF") + (match_operand:DF 1 "register_or_const0_operand" "G,a,G,a")))] + "TARGET_FPU" + "* +{ + cc_status.flags = CC_IN_FPU; + if (which_alternative == 0 || which_alternative == 2) + return \"{tstd|tstf} %0\;cfcc\"; + else + return \"{cmpd|cmpf} %0, %1\;cfcc\"; +}" + [(set_attr "length" "4,4,6,6")]) + +(define_insn "*cmp<mode>" + [(set (cc0) + (compare (match_operand:PDPint 0 "general_operand" "rR,rR,rR,Q,Qi,Qi") + (match_operand:PDPint 1 "general_operand" "N,rR,Qi,N,rR,Qi")))] + "" + "@ + tst<PDPint:isfx> %0 + cmp<PDPint:isfx> %0,%1 + cmp<PDPint:isfx> %0,%1 + tst<PDPint:isfx> %0 + cmp<PDPint:isfx> %0,%1 + cmp<PDPint:isfx> %0,%1" + [(set_attr "length" "2,2,4,4,4,6")]) + +;; sob instruction - we need an assembler which can make this instruction +;; valid under _all_ circumstances! + +(define_insn "" + [(set (pc) + (if_then_else + (ne (plus:HI (match_operand:HI 0 "register_operand" "+r") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:HI (match_dup 0) + (const_int -1)))] + "TARGET_40_PLUS" + "* +{ + static int labelcount = 0; + static char buf[1000]; + + if (get_attr_length (insn) == 2) + return \"sob %0, %l1\"; + + /* emulate sob */ + output_asm_insn (\"dec %0\", operands); + + sprintf (buf, \"bge LONG_SOB%d\", labelcount); + output_asm_insn (buf, NULL); + + output_asm_insn (\"jmp %l1\", operands); + + sprintf (buf, \"LONG_SOB%d:\", labelcount++); + output_asm_insn (buf, NULL); + + return \"\"; +}" + [(set (attr "length") (if_then_else (ior (lt (minus (match_dup 0) + (pc)) + (const_int MIN_SOB)) + (gt (minus (match_dup 0) + (pc)) + (const_int MAX_SOB))) + (const_int 8) + (const_int 2)))]) + +;; These control RTL generation for conditional jump insns +;; and match them for register allocation. + +(define_expand "cbranchdf4" + [(set (cc0) + (compare (match_operand:DF 1 "general_operand") + (match_operand:DF 2 "register_or_const0_operand"))) + (set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(cc0) (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_FPU" + "") + +(define_expand "cbranch<mode>4" + [(set (cc0) + (compare (match_operand:PDPint 1 "general_operand") + (match_operand:PDPint 2 "general_operand"))) + (set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(cc0) (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" + "") + +;; problem with too short jump distance! we need an assembler which can +;; make this valid for all jump distances! +;; e.g. gas! + +;; these must be changed to check for CC_IN_FCCR if float is to be +;; enabled + +(define_insn "*branch" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(cc0) (const_int 0)]) + (label_ref (match_operand 1 "" "")) + (pc)))] + "" + "* return output_jump(GET_CODE (operands[0]), 0, get_attr_length(insn));" + [(set (attr "length") (if_then_else (ior (lt (minus (match_dup 1) + (pc)) + (const_int MIN_BRANCH)) + (gt (minus (match_dup 1) + (pc)) + (const_int MAX_BRANCH))) + (const_int 6) + (const_int 2)))]) + + +;; These match inverted jump insns for register allocation. + +(define_insn "*branch_inverted" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(cc0) (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "* return output_jump(GET_CODE (operands[0]), 1, get_attr_length(insn));" + [(set (attr "length") (if_then_else (ior (lt (minus (match_dup 1) + (pc)) + (const_int MIN_BRANCH)) + (gt (minus (match_dup 1) + (pc)) + (const_int MAX_BRANCH))) + (const_int 6) + (const_int 2)))]) + +;; Move instructions + +(define_insn "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,g") + (match_operand:DI 1 "general_operand" "rN,g"))] + "" + "* return output_move_multiple (operands);" +;; what's the mose expensive code - say twice movsi = 16 + [(set_attr "length" "16,32")]) + +(define_insn "movsi" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,g,g") + (match_operand:SI 1 "general_operand" "rN,IJ,IJ,g"))] + "" + "* return output_move_multiple (operands);" +;; what's the most expensive code ? - I think 8! +;; we could split it up and make several sub-cases... + [(set_attr "length" "4,6,8,16")]) + +(define_insn "mov<mode>" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (match_operand:PDPint 1 "general_operand" "rRN,Qi,rRN,Qi"))] + "" + "* +{ + if (operands[1] == const0_rtx) + return \"clr<PDPint:isfx> %0\"; + + return \"mov<PDPint:isfx> %1, %0\"; +}" + [(set_attr "length" "2,4,4,6")]) + +(define_insn "movdf" + [(set (match_operand:DF 0 "float_nonimm_operand" "=a,fR,a,Q,g") + (match_operand:DF 1 "float_operand" "fR,a,FQ,a,g"))] + "TARGET_FPU" + "* if (which_alternative ==0 || which_alternative == 2) + return \"ldd %1, %0\"; + else if (which_alternative == 1 || which_alternative == 3) + return \"std %1, %0\"; + else + return output_move_multiple (operands); " +;; last one is worst-case + [(set_attr "length" "2,2,4,4,24")]) + +(define_insn "movsf" + [(set (match_operand:SF 0 "float_nonimm_operand" "=a,fR,a,Q,g") + (match_operand:SF 1 "float_operand" "fR,a,FQ,a,g"))] + "TARGET_FPU" + "* if (which_alternative ==0 || which_alternative == 2) + return \"{ldcfd|movof} %1, %0\"; + else if (which_alternative == 1 || which_alternative == 3) + return \"{stcdf|movfo} %1, %0\"; + else + return output_move_multiple (operands); " +;; last one is worst-case + [(set_attr "length" "2,2,4,4,12")]) + +;; maybe fiddle a bit with move_ratio, then +;; let constraints only accept a register ... + +(define_expand "movmemhi" + [(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g") + (match_operand:BLK 1 "general_operand" "g,g")) + (use (match_operand:HI 2 "general_operand" "n,mr")) + (use (match_operand:HI 3 "immediate_operand" "i,i")) + (clobber (match_scratch:HI 4 "=&r,X")) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_dup 2))])] + "(TARGET_BCOPY_BUILTIN)" + " +{ + operands[0] + = replace_equiv_address (operands[0], + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); + operands[1] + = replace_equiv_address (operands[1], + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); + + operands[5] = XEXP (operands[0], 0); + operands[6] = XEXP (operands[1], 0); +}") + + +(define_insn "movmemhi1" + [(set (mem:BLK (match_operand:HI 0 "register_operand" "r,r")) + (mem:BLK (match_operand:HI 1 "register_operand" "r,r"))) + (use (match_operand:HI 2 "general_operand" "n,r")) + (use (match_operand:HI 3 "immediate_operand" "i,i")) + (clobber (match_scratch:HI 4 "=&r,X")) + (clobber (match_dup 0)) + (clobber (match_dup 1)) + (clobber (match_dup 2))] + "(TARGET_BCOPY_BUILTIN)" + "* return output_block_move (operands);" +;;; just a guess + [(set_attr "length" "80")]) + + + +;;- truncation instructions + +(define_insn "truncdfsf2" + [(set (match_operand:SF 0 "float_nonimm_operand" "=f,R,Q") + (float_truncate:SF (match_operand:DF 1 "register_operand" "f,a,a")))] + "TARGET_FPU" + "* if (which_alternative ==0) + { + return \"\"; + } + else if (which_alternative == 1) + return \"{stcdf|movfo} %1, %0\"; + else + return \"{stcdf|movfo} %1, %0\"; + " + [(set_attr "length" "0,2,4")]) + + +(define_expand "truncsihi2" + [(set (match_operand:HI 0 "nonimmediate_operand" "=g") + (subreg:HI + (match_operand:SI 1 "general_operand" "or") + 0))] + "" + "") + + +;;- zero extension instructions + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (zero_extend:HI (match_operand:QI 1 "general_operand" "0,0")))] + "" + "bic $0177400, %0" + [(set_attr "length" "4,6")]) + +(define_expand "zero_extendhisi2" + [(set (subreg:HI + (match_dup 0) + 2) + (match_operand:HI 1 "register_operand" "r")) + (set (subreg:HI + (match_operand:SI 0 "register_operand" "=r") + 0) + (const_int 0))] + "" + "/* operands[1] = make_safe_from (operands[1], operands[0]); */") + + +;;- sign extension instructions + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "register_operand" "=f,a,a") + (float_extend:DF (match_operand:SF 1 "float_operand" "f,R,Q")))] + "TARGET_FPU" + "@ + /* nothing */ + {ldcfd|movof} %1, %0 + {ldcfd|movof} %1, %0" + [(set_attr "length" "0,2,4")]) + +;; does movb sign extend in register-to-register move? +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))] + "" + "movb %1, %0" + [(set_attr "length" "2,4")]) + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (sign_extend:SI (match_operand:QI 1 "general_operand" "rR,Q")))] + "TARGET_40_PLUS" + "* +{ + rtx latehalf[2]; + + /* make register pair available */ + latehalf[0] = operands[0]; + operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+ 1); + + output_asm_insn(\"movb %1, %0\", operands); + output_asm_insn(\"sxt %0\", latehalf); + + return \"\"; +}" + [(set_attr "length" "4,6")]) + +;; maybe we have to use define_expand to say that we have the instruction, +;; unconditionally, and then match dependent on CPU type: + +(define_expand "extendhisi2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=g") + (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] + "" + "") + +(define_insn "" ; "extendhisi2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=o,<,r") + (sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))] + "TARGET_40_PLUS" + "* +{ + rtx latehalf[2]; + + /* we don't want to mess with auto increment */ + + switch (which_alternative) + { + case 0: + + latehalf[0] = operands[0]; + operands[0] = adjust_address(operands[0], HImode, 2); + + output_asm_insn(\"mov %1, %0\", operands); + output_asm_insn(\"sxt %0\", latehalf); + + return \"\"; + + case 1: + + /* - auto-decrement - right direction ;-) */ + output_asm_insn(\"mov %1, %0\", operands); + output_asm_insn(\"sxt %0\", operands); + + return \"\"; + + case 2: + + /* make register pair available */ + latehalf[0] = operands[0]; + operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + + output_asm_insn(\"mov %1, %0\", operands); + output_asm_insn(\"sxt %0\", latehalf); + + return \"\"; + + default: + + gcc_unreachable (); + } +}" + [(set_attr "length" "10,6,6")]) + + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "general_operand" "0")))] + "(! TARGET_40_PLUS)" + "* +{ + static int count = 0; + char buf[100]; + rtx lateoperands[2]; + + lateoperands[0] = operands[0]; + operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + + output_asm_insn(\"tst %0\", operands); + sprintf(buf, \"bge extendhisi%d\", count); + output_asm_insn(buf, NULL); + output_asm_insn(\"mov -1, %0\", lateoperands); + sprintf(buf, \"bne extendhisi%d\", count+1); + output_asm_insn(buf, NULL); + sprintf(buf, \"\\nextendhisi%d:\", count); + output_asm_insn(buf, NULL); + output_asm_insn(\"clr %0\", lateoperands); + sprintf(buf, \"\\nextendhisi%d:\", count+1); + output_asm_insn(buf, NULL); + + count += 2; + + return \"\"; +}" + [(set_attr "length" "12")]) + +;; make float to int and vice versa +;; using the cc_status.flag field we could probably cut down +;; on seti and setl +;; assume that we are normally in double and integer mode - +;; what do pdp library routines do to fpu mode ? + +(define_insn "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "=a,a,a") + (float:DF (match_operand:SI 1 "general_operand" "r,R,Q")))] + "TARGET_FPU" + "* if (which_alternative ==0) + { + rtx latehalf[2]; + + latehalf[0] = NULL; + latehalf[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1); + output_asm_insn(\"mov %1, -(sp)\", latehalf); + output_asm_insn(\"mov %1, -(sp)\", operands); + + output_asm_insn(\"setl\", operands); + output_asm_insn(\"{ldcld|movif} (sp)+, %0\", operands); + output_asm_insn(\"seti\", operands); + return \"\"; + } + else if (which_alternative == 1) + return \"setl\;{ldcld|movif} %1, %0\;seti\"; + else + return \"setl\;{ldcld|movif} %1, %0\;seti\"; + " + [(set_attr "length" "10,6,8")]) + +(define_insn "floathidf2" + [(set (match_operand:DF 0 "register_operand" "=a,a") + (float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))] + "TARGET_FPU" + "{ldcid|movif} %1, %0" + [(set_attr "length" "2,4")]) + +;; cut float to int +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,R,Q") + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))] + "TARGET_FPU" + "* if (which_alternative ==0) + { + output_asm_insn(\"setl\", operands); + output_asm_insn(\"{stcdl|movfi} %1, -(sp)\", operands); + output_asm_insn(\"seti\", operands); + output_asm_insn(\"mov (sp)+, %0\", operands); + operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + output_asm_insn(\"mov (sp)+, %0\", operands); + return \"\"; + } + else if (which_alternative == 1) + return \"setl\;{stcdl|movfi} %1, %0\;seti\"; + else + return \"setl\;{stcdl|movfi} %1, %0\;seti\"; + " + [(set_attr "length" "10,6,8")]) + +(define_insn "fix_truncdfhi2" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))] + "TARGET_FPU" + "{stcdi|movfi} %1, %0" + [(set_attr "length" "2,4")]) + + +;;- arithmetic instructions +;;- add instructions + +(define_insn "adddf3" + [(set (match_operand:DF 0 "register_operand" "=a,a") + (plus:DF (match_operand:DF 1 "register_operand" "%0,0") + (match_operand:DF 2 "general_operand" "fR,QF")))] + "TARGET_FPU" + "{addd|addf} %2, %0" + [(set_attr "length" "2,4")]) + +(define_insn "adddi3" + [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,o") + (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0") + (match_operand:DI 2 "general_operand" "r,on,r,on")))] + "" + "* +{ + rtx inops[2]; + rtx exops[4][2]; + + inops[0] = operands[0]; + inops[1] = operands[2]; + pdp11_expand_operands (inops, exops, 2, NULL, either); + + if (!CONSTANT_P (exops[0][1]) || INTVAL (exops[0][1]) != 0) + output_asm_insn (\"add %1, %0\", exops[0]); + if (!CONSTANT_P (exops[1][1]) || INTVAL (exops[1][1]) != 0) + { + output_asm_insn (\"add %1, %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + } + if (!CONSTANT_P (exops[2][1]) || INTVAL (exops[2][1]) != 0) + { + output_asm_insn (\"add %1, %0\", exops[2]); + output_asm_insn (\"adc %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + } + if (!CONSTANT_P (exops[3][1]) || INTVAL (exops[3][1]) != 0) + { + output_asm_insn (\"add %1, %0\", exops[3]); + output_asm_insn (\"adc %0\", exops[2]); + output_asm_insn (\"adc %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + } + + return \"\"; +}" + [(set_attr "length" "20,28,40,48")]) + +;; Note that the register operand is not marked earlyclobber. +;; The reason is that SI values go in register pairs, so they +;; can't partially overlap. They can be either disjoint, or +;; source and destination can be equal. The latter case is +;; handled properly because of the ordering of the individual +;; instructions used. Specifically, carry from the low to the +;; high word is added at the end, so the adding of the high parts +;; will always used the original high part and not a high part +;; modified by carry (which would amount to double carry). +(define_insn "addsi3" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o") + (plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0") + (match_operand:SI 2 "general_operand" "r,on,r,on")))] + "" + "* +{ + rtx inops[2]; + rtx exops[2][2]; + + inops[0] = operands[0]; + inops[1] = operands[2]; + pdp11_expand_operands (inops, exops, 2, NULL, either); + + if (!CONSTANT_P (exops[0][1]) || INTVAL (exops[0][1]) != 0) + output_asm_insn (\"add %1, %0\", exops[0]); + if (!CONSTANT_P (exops[1][1]) || INTVAL (exops[1][1]) != 0) + { + output_asm_insn (\"add %1, %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + } + + return \"\"; +}" + [(set_attr "length" "6,10,12,16")]) + +(define_insn "addhi3" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") + (match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL(operands[2]) == 1) + return \"inc %0\"; + else if (INTVAL(operands[2]) == -1) + return \"dec %0\"; + } + + return \"add %2, %0\"; +}" + [(set_attr "length" "2,4,4,6")]) + + +;;- subtract instructions +;; we don't have to care for constant second +;; args, since they are canonical plus:xx now! +;; also for minus:DF ?? + +(define_insn "subdf3" + [(set (match_operand:DF 0 "register_operand" "=a,a") + (minus:DF (match_operand:DF 1 "register_operand" "0,0") + (match_operand:DF 2 "general_operand" "fR,Q")))] + "TARGET_FPU" + "{subd|subf} %2, %0" + [(set_attr "length" "2,4")]) + +(define_insn "subdi3" + [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,o") + (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0") + (match_operand:DI 2 "general_operand" "r,on,r,on")))] + "" + "* +{ + rtx inops[2]; + rtx exops[4][2]; + + inops[0] = operands[0]; + inops[1] = operands[2]; + pdp11_expand_operands (inops, exops, 2, NULL, either); + + if (!CONSTANT_P (exops[0][1]) || INTVAL (exops[0][1]) != 0) + output_asm_insn (\"sub %1, %0\", exops[0]); + if (!CONSTANT_P (exops[1][1]) || INTVAL (exops[1][1]) != 0) + { + output_asm_insn (\"sub %1, %0\", exops[1]); + output_asm_insn (\"sbc %0\", exops[0]); + } + if (!CONSTANT_P (exops[2][1]) || INTVAL (exops[2][1]) != 0) + { + output_asm_insn (\"sub %1, %0\", exops[2]); + output_asm_insn (\"sbc %0\", exops[1]); + output_asm_insn (\"sbc %0\", exops[0]); + } + if (!CONSTANT_P (exops[3][1]) || INTVAL (exops[3][1]) != 0) + { + output_asm_insn (\"sub %1, %0\", exops[3]); + output_asm_insn (\"sbc %0\", exops[2]); + output_asm_insn (\"sbc %0\", exops[1]); + output_asm_insn (\"sbc %0\", exops[0]); + } + + return \"\"; +}" + [(set_attr "length" "20,28,40,48")]) + +(define_insn "subsi3" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o") + (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") + (match_operand:SI 2 "general_operand" "r,on,r,on")))] + "" + "* +{ + rtx inops[2]; + rtx exops[2][2]; + + inops[0] = operands[0]; + inops[1] = operands[2]; + pdp11_expand_operands (inops, exops, 2, NULL, either); + + if (!CONSTANT_P (exops[0][1]) || INTVAL (exops[0][1]) != 0) + output_asm_insn (\"sub %1, %0\", exops[0]); + if (!CONSTANT_P (exops[1][1]) || INTVAL (exops[1][1]) != 0) + { + output_asm_insn (\"sub %1, %0\", exops[1]); + output_asm_insn (\"sbc %0\", exops[0]); + } + + return \"\"; +}" + [(set_attr "length" "6,10,12,16")]) + +(define_insn "subhi3" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") + (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))] + "" + "* +{ + gcc_assert (GET_CODE (operands[2]) != CONST_INT); + + return \"sub %2, %0\"; +}" + [(set_attr "length" "2,4,4,6")]) + +;;;;- and instructions +;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn. + +(define_expand "and<mode>3" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "") + (and:PDPint (not:PDPint (match_operand:PDPint 1 "general_operand" "")) + (match_operand:PDPint 2 "general_operand" "")))] + "" + " +{ + rtx op1 = operands[1]; + + /* If there is a constant argument, complement that one. + Similarly, if one of the inputs is the same as the output, + complement the other input. */ + if ((CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) || + rtx_equal_p (operands[0], operands[1])) + { + operands[1] = operands[2]; + operands[2] = op1; + op1 = operands[1]; + } + + if (CONST_INT_P (op1)) + operands[1] = GEN_INT (~INTVAL (op1)); + else + operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); +}") + +(define_insn "*bic<mode>" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (and:PDPint + (not: PDPint (match_operand:PDPint 1 "general_operand" "rR,Qi,rR,Qi")) + (match_operand:PDPint 2 "general_operand" "0,0,0,0")))] + "" + "bic<PDPint:isfx> %1, %0" + [(set_attr "length" "2,4,4,6")]) + +;;- Bit set (inclusive or) instructions +(define_insn "ior<mode>3" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (ior:PDPint (match_operand:PDPint 1 "general_operand" "%0,0,0,0") + (match_operand:PDPint 2 "general_operand" "rR,Qi,rR,Qi")))] + "" + "bis<PDPint:isfx> %2, %0" + [(set_attr "length" "2,4,4,6")]) + +;;- xor instructions +(define_insn "xorhi3" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (xor:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "register_operand" "r,r")))] + "TARGET_40_PLUS" + "xor %2, %0" + [(set_attr "length" "2,4")]) + +;;- one complement instructions + +(define_insn "one_cmpl<mode>2" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,Q") + (not:PDPint (match_operand:PDPint 1 "general_operand" "0,0")))] + "" + "com<PDPint:isfx> %0" + [(set_attr "length" "2,4")]) + +;;- arithmetic shift instructions +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (ashift:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:HI 2 "general_operand" "rR,Qi")))] + "TARGET_40_PLUS" + "ashc %2,%0" + [(set_attr "length" "2,4")]) + +;; Arithmetic right shift on the pdp works by negating the shift count. +(define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + " +{ + operands[2] = negate_rtx (HImode, operands[2]); +}") + +;; define asl aslb asr asrb - ashc missing! + +;; asl +(define_insn "" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (ashift:HI (match_operand:HI 1 "general_operand" "0,0") + (const_int 1)))] + "" + "asl %0" + [(set_attr "length" "2,4")]) + +;; and another possibility for asr is << -1 +;; might cause problems since -1 can also be encoded as 65535! +;; not in gcc2 ??? + +;; asr +(define_insn "" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (ashift:HI (match_operand:HI 1 "general_operand" "0,0") + (const_int -1)))] + "" + "asr %0" + [(set_attr "length" "2,4")]) + +;; lsr +(define_insn "lsrhi1" + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") + (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0") + (const_int 1)))] + "" + "clc\;ror %0" + [(set_attr "length" "2,4")]) + +(define_insn "lsrsi1" + [(set (match_operand:SI 0 "register_operand" "=r") + (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") + (const_int 1)))] + "" +{ + + rtx lateoperands[2]; + + lateoperands[0] = operands[0]; + operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + + lateoperands[1] = operands[1]; + operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]) + 1); + + output_asm_insn (\"clc\", operands); + output_asm_insn (\"ror %0\", lateoperands); + output_asm_insn (\"ror %0\", operands); + + return \"\"; +} + [(set_attr "length" "10")]) + +(define_expand "lshrsi3" + [(match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "")] + "" + " +{ + rtx r; + + if (!TARGET_40_PLUS && + (GET_CODE (operands[2]) != CONST_INT || + (unsigned) INTVAL (operands[2]) > 3)) + FAIL; + emit_insn (gen_lsrsi1 (operands[0], operands[1])); + if (GET_CODE (operands[2]) != CONST_INT) + { + r = gen_reg_rtx (HImode); + emit_insn (gen_addhi3 (r, operands [2], GEN_INT (-1))); + emit_insn (gen_ashrsi3 (operands[0], operands[0], r)); + } + else if ((unsigned) INTVAL (operands[2]) != 1) + { + emit_insn (gen_ashlsi3 (operands[0], operands[0], + GEN_INT (1 - INTVAL (operands[2])))); + } + DONE; +} +" +) + +;; shift is by arbitrary count is expensive, +;; shift by one cheap - so let's do that, if +;; space doesn't matter +(define_insn "" + [(set (match_operand:HI 0 "nonimmediate_operand" "=r") + (ashift:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "expand_shift_operand" "O")))] + "! optimize_size" + "* +{ + register int i; + + for (i = 1; i <= abs(INTVAL(operands[2])); i++) + if (INTVAL(operands[2]) < 0) + output_asm_insn(\"asr %0\", operands); + else + output_asm_insn(\"asl %0\", operands); + + return \"\"; +}" +;; longest is 4 + [(set (attr "length") (const_int 8))]) + +;; aslb +(define_insn "" + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,o") + (ashift:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:HI 2 "const_int_operand" "n,n")))] + "" + "* +{ /* allowing predec or post_inc is possible, but hairy! */ + int i, cnt; + + cnt = INTVAL(operands[2]) & 0x0007; + + for (i=0 ; i < cnt ; i++) + output_asm_insn(\"aslb %0\", operands); + + return \"\"; +}" +;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!! + [(set_attr_alternative "length" + [(const_int 14) + (const_int 28)])]) + +;;; asr +;(define_insn "" +; [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") +; (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0") +; (const_int 1)))] +; "" +; "asr %0" +; [(set_attr "length" "2,4")]) + +;; asrb +(define_insn "" + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,o") + (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:HI 2 "const_int_operand" "n,n")))] + "" + "* +{ /* allowing predec or post_inc is possible, but hairy! */ + int i, cnt; + + cnt = INTVAL(operands[2]) & 0x0007; + + for (i=0 ; i < cnt ; i++) + output_asm_insn(\"asrb %0\", operands); + + return \"\"; +}" + [(set_attr_alternative "length" + [(const_int 14) + (const_int 28)])]) + +;; the following is invalid - too complex!!! - just say 14 !!! +; [(set (attr "length") (plus (and (match_dup 2) +; (const_int 14)) +; (and (match_dup 2) +; (const_int 14))))]) + + + +;; can we get +-1 in the next pattern? should +;; have been caught by previous patterns! + +(define_insn "ashlhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (ashift:HI (match_operand:HI 1 "register_operand" "0,0") + (match_operand:HI 2 "general_operand" "rR,Qi")))] + "TARGET_40_PLUS" + "* +{ + if (GET_CODE(operands[2]) == CONST_INT) + { + if (INTVAL(operands[2]) == 1) + return \"asl %0\"; + else if (INTVAL(operands[2]) == -1) + return \"asr %0\"; + } + + return \"ash %2,%0\"; +}" + [(set_attr "length" "2,4")]) + +;; Arithmetic right shift on the pdp works by negating the shift count. +(define_expand "ashrhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (ashift:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + " +{ + operands[2] = negate_rtx (HImode, operands[2]); +}") + +(define_expand "lshrhi3" + [(match_operand:HI 0 "register_operand" "") + (match_operand:HI 1 "register_operand" "") + (match_operand:HI 2 "general_operand" "")] + "" + " +{ + rtx r; + + if (!TARGET_40_PLUS && + (GET_CODE (operands[2]) != CONST_INT || + (unsigned) INTVAL (operands[2]) > 3)) + FAIL; + emit_insn (gen_lsrhi1 (operands[0], operands[1])); + if (GET_CODE (operands[2]) != CONST_INT) + { + r = gen_reg_rtx (HImode); + emit_insn (gen_addhi3 (r, operands [2], GEN_INT (-1))); + emit_insn (gen_ashrhi3 (operands[0], operands[0], r)); + } + else if ((unsigned) INTVAL (operands[2]) != 1) + { + emit_insn (gen_ashlhi3 (operands[0], operands[0], + GEN_INT (1 - INTVAL (operands[2])))); + } + DONE; +} +" +) + +;; absolute + +(define_insn "absdf2" + [(set (match_operand:DF 0 "nonimmediate_operand" "=fR,Q") + (abs:DF (match_operand:DF 1 "general_operand" "0,0")))] + "TARGET_FPU" + "{absd|absf} %0" + [(set_attr "length" "2,4")]) + + +;; negate insns + +(define_insn "negdf2" + [(set (match_operand:DF 0 "float_nonimm_operand" "=fR,Q") + (neg:DF (match_operand:DF 1 "register_operand" "0,0")))] + "TARGET_FPU" + "{negd|negf} %0" + [(set_attr "length" "2,4")]) + +(define_insn "negdi2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") + (neg:DI (match_operand:DI 1 "general_operand" "0,0")))] + "" +{ + rtx exops[4][2]; + + pdp11_expand_operands (operands, exops, 1, NULL, either); + + output_asm_insn (\"com %0\", exops[3]); + output_asm_insn (\"com %0\", exops[2]); + output_asm_insn (\"com %0\", exops[1]); + output_asm_insn (\"com %0\", exops[0]); + output_asm_insn (\"add $1, %0\", exops[3]); + output_asm_insn (\"adc %0\", exops[2]); + output_asm_insn (\"adc %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + + return \"\"; +} +[(set_attr "length" "18,34")]) + +(define_insn "negsi2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,o") + (neg:SI (match_operand:SI 1 "general_operand" "0,0")))] + "" +{ + rtx exops[2][2]; + + pdp11_expand_operands (operands, exops, 1, NULL, either); + + output_asm_insn (\"com %0\", exops[1]); + output_asm_insn (\"com %0\", exops[0]); + output_asm_insn (\"add $1, %0\", exops[1]); + output_asm_insn (\"adc %0\", exops[0]); + + return \"\"; +} +[(set_attr "length" "12,20")]) + +(define_insn "neg<mode>2" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,Q") + (neg:PDPint (match_operand:PDPint 1 "general_operand" "0,0")))] + "" + "neg<isfx> %0" + [(set_attr "length" "2,4")]) + + +;; Unconditional and other jump instructions +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "* +{ + if (get_attr_length (insn) == 2) + return \"br %l0\"; + return \"jmp %l0\"; +}" + [(set (attr "length") (if_then_else (ior (lt (minus (match_dup 0) + (pc)) + (const_int MIN_BRANCH)) + (gt (minus (match_dup 0) + (pc)) + (const_int MAX_BRANCH))) + (const_int 4) + (const_int 2)))]) + +(define_insn "" + [(set (pc) + (label_ref (match_operand 0 "" ""))) + (clobber (const_int 1))] + "" + "jmp %l0" + [(set_attr "length" "4")]) + +(define_insn "tablejump" + [(set (pc) (match_operand:HI 0 "general_operand" "r,R,Q")) + (use (label_ref (match_operand 1 "" "")))] + "" + "@ + jmp (%0) + jmp %@%0 + jmp %@%0" + [(set_attr "length" "2,2,4")]) + +;; indirect jump - let's be conservative! +;; allow only register_operand, even though we could also +;; allow labels etc. + +(define_insn "indirect_jump" + [(set (pc) (match_operand:HI 0 "register_operand" "r"))] + "" + "jmp (%0)") + +;;- jump to subroutine + +(define_insn "call" + [(call (match_operand:HI 0 "general_operand" "rR,Q") + (match_operand:HI 1 "general_operand" "g,g")) +;; (use (reg:HI 0)) what was that ??? + ] + ;;- Don't use operand 1 for most machines. + "" + "jsr pc, %0" + [(set_attr "length" "2,4")]) + +;;- jump to subroutine +(define_insn "call_value" + [(set (match_operand 0 "" "") + (call (match_operand:HI 1 "general_operand" "rR,Q") + (match_operand:HI 2 "general_operand" "g,g"))) +;; (use (reg:HI 0)) - what was that ???? + ] + ;;- Don't use operand 2 for most machines. + "" + "jsr pc, %1" + [(set_attr "length" "2,4")]) + +;;- nop instruction +(define_insn "nop" + [(const_int 0)] + "" + "nop") + + +;;- multiply + +(define_insn "muldf3" + [(set (match_operand:DF 0 "register_operand" "=a,a") + (mult:DF (match_operand:DF 1 "register_operand" "%0,0") + (match_operand:DF 2 "float_operand" "fR,QF")))] + "TARGET_FPU" + "{muld|mulf} %2, %0" + [(set_attr "length" "2,4")]) + +;; 16 bit result multiply: +;; currently we multiply only into odd registers, so we don't use two +;; registers - but this is a bit inefficient at times. If we define +;; a register class for each register, then we can specify properly +;; which register need which scratch register .... + +(define_insn "mulhi3" + [(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs + (mult:HI (match_operand:HI 1 "register_operand" "%0,0") + (match_operand:HI 2 "float_operand" "rR,Qi")))] + "TARGET_40_PLUS" + "mul %2, %0" + [(set_attr "length" "2,4")]) + +;; 32 bit result +(define_expand "mulhisi3" + [(set (match_dup 3) + (match_operand:HI 1 "nonimmediate_operand" "g,g")) + (set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! + (mult:SI (truncate:HI + (match_dup 0)) + (match_operand:HI 2 "general_operand" "rR,Qi")))] + "TARGET_40_PLUS" + "operands[3] = gen_lowpart(HImode, operands[1]);") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! + (mult:SI (truncate:HI + (match_operand:SI 1 "register_operand" "%0,0")) + (match_operand:HI 2 "general_operand" "rR,Qi")))] + "TARGET_40_PLUS" + "mul %2, %0" + [(set_attr "length" "2,4")]) + +;(define_insn "mulhisi3" +; [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! +; (mult:SI (truncate:HI +; (match_operand:SI 1 "register_operand" "%0,0")) +; (match_operand:HI 2 "general_operand" "rR,Qi")))] +; "TARGET_40_PLUS" +; "mul %2, %0" +; [(set_attr "length" "2,4")]) + +;;- divide +(define_insn "divdf3" + [(set (match_operand:DF 0 "register_operand" "=a,a") + (div:DF (match_operand:DF 1 "register_operand" "0,0") + (match_operand:DF 2 "general_operand" "fR,QF")))] + "TARGET_FPU" + "{divd|divf} %2, %0" + [(set_attr "length" "2,4")]) + + +(define_expand "divhi3" + [(set (subreg:HI (match_dup 1) 0) + (div:HI (match_operand:SI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "g"))) + (set (match_operand:HI 0 "register_operand" "=r") + (subreg:HI (match_dup 1) 0))] + "TARGET_40_PLUS" + "") + +(define_insn "" + [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 0) + (div:HI (match_operand:SI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "TARGET_40_PLUS" + "div %2,%0" + [(set_attr "length" "4")]) + +(define_expand "modhi3" + [(set (subreg:HI (match_dup 1) 2) + (mod:HI (match_operand:SI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "g"))) + (set (match_operand:HI 0 "register_operand" "=r") + (subreg:HI (match_dup 1) 2))] + "TARGET_40_PLUS" + "") + +(define_insn "" + [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 2) + (mod:HI (match_operand:SI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "TARGET_40_PLUS" + "div %2,%0" + [(set_attr "length" "4")]) + +;(define_expand "divmodhi4" +; [(parallel [(set (subreg:HI (match_dup 1) 0) +; (div:HI (match_operand:SI 1 "register_operand" "0") +; (match_operand:HI 2 "general_operand" "g"))) +; (set (subreg:HI (match_dup 1) 2) +; (mod:HI (match_dup 1) +; (match_dup 2)))]) +; (set (match_operand:HI 3 "register_operand" "=r") +; (subreg:HI (match_dup 1) 2)) +; (set (match_operand:HI 0 "register_operand" "=r") +; (subreg:HI (match_dup 1) 0))] +; "TARGET_40_PLUS" +; "") +; +;(define_insn "" +; [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 0) +; (div:HI (match_operand:SI 1 "general_operand" "0") +; (match_operand:HI 2 "general_operand" "g"))) +; (set (subreg:HI (match_dup 0) 2) +; (mod:HI (match_dup 1) +; (match_dup 2)))] +; "TARGET_40_PLUS" +; "div %2, %0") +; + +;; is rotate doing the right thing to be included here ???? diff --git a/gcc/config/pdp11/pdp11.opt b/gcc/config/pdp11/pdp11.opt new file mode 100644 index 000000000..9c427a3f8 --- /dev/null +++ b/gcc/config/pdp11/pdp11.opt @@ -0,0 +1,87 @@ +; Options for the PDP11 port of the compiler. + +; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +; for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. + +m10 +Target RejectNegative +Generate code for an 11/10 + +m40 +Target Report Mask(40) +Generate code for an 11/40 + +m45 +Target Report Mask(45) +Generate code for an 11/45 + +mac0 +Target Report Mask(AC0) +Return floating-point results in ac0 (fr0 in Unix assembler syntax) + +mbcopy +Target RejectNegative Report Mask(BCOPY) +Do not use inline patterns for copying memory + +mbcopy-builtin +Target RejectNegative Report InverseMask(BCOPY, BCOPY_BUILTIN) +Use inline patterns for copying memory + +mbranch-cheap +Target RejectNegative Report InverseMask(BRANCH_EXPENSIVE, BRANCH_CHEAP) +Do not pretend that branches are expensive + +mbranch-expensive +Target RejectNegative Report Mask(BRANCH_EXPENSIVE) +Pretend that branches are expensive + +mdec-asm +Target RejectNegative Report InverseMask(UNIX_ASM) +Use the DEC assembler syntax + +mfloat32 +Target Report Mask(FLOAT32) +Use 32 bit float + +mfloat64 +Target Report InverseMask(FLOAT32, FLOAT64) +Use 64 bit float + +mfpu +Target RejectNegative Report Mask(FPU) +Use hardware floating point + +mint16 +Target Report InverseMask(INT32, INT16) +Use 16 bit int + +mint32 +Target Report Mask(INT32) +Use 32 bit int + +msoft-float +Target RejectNegative Report InverseMask(FPU, SOFT_FLOAT) +Do not use hardware floating point + +msplit +Target Report Mask(SPLIT) +Target has split I&D + +munix-asm +Target RejectNegative Report Mask(UNIX_ASM) +Use UNIX assembler syntax diff --git a/gcc/config/pdp11/predicates.md b/gcc/config/pdp11/predicates.md new file mode 100644 index 000000000..8b24ba4fc --- /dev/null +++ b/gcc/config/pdp11/predicates.md @@ -0,0 +1,55 @@ +;;- Predicate definitions for the pdp11 for GNU C compiler +;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2004, 2005 +;; 2007, 2008, 2010 Free Software Foundation, Inc. +;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; Match CONST_DOUBLE zero for tstd/tstf. +(define_predicate "register_or_const0_operand" + (ior (match_operand 0 "register_operand") + (match_test "op == CONST0_RTX (GET_MODE (op))"))) + +;; Accept integer arguments in the range -4..-2 and 2..4, which are the +;; shift counts for which we unroll a shift. This matches the rule for +;; the "O" constraint. +(define_predicate "expand_shift_operand" + (match_code "const_int") +{ + int sh; + + sh = INTVAL (op); + return (abs (sh) > 1 && abs (sh) <= 4); +}) + +;; Accept anything general_operand accepts, except that registers must +;; be FPU registers. +(define_predicate "float_operand" + (if_then_else (match_code "reg") + (ior + (match_test "REGNO_REG_CLASS (REGNO (op)) == LOAD_FPU_REGS") + (match_test "REGNO_REG_CLASS (REGNO (op)) == NO_LOAD_FPU_REGS")) + (match_test "general_operand (op, mode)"))) + +;; Accept anything nonimmediate_operand accepts, except that registers must +;; be FPU registers. +(define_predicate "float_nonimm_operand" + (if_then_else (match_code "reg") + (ior + (match_test "REGNO_REG_CLASS (REGNO (op)) == LOAD_FPU_REGS") + (match_test "REGNO_REG_CLASS (REGNO (op)) == NO_LOAD_FPU_REGS")) + (match_test "nonimmediate_operand (op, mode)"))) diff --git a/gcc/config/pdp11/t-pdp11 b/gcc/config/pdp11/t-pdp11 new file mode 100644 index 000000000..67441a0d2 --- /dev/null +++ b/gcc/config/pdp11/t-pdp11 @@ -0,0 +1,44 @@ +# Copyright (C) 1995, 1997, 1998, 2001, 2002, +# 2004, 2010 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +TARGET_LIBGCC2_CFLAGS = -O2 -mfloat32 +LIB2FUNCS_EXTRA = $(srcdir)/config/udivmod.c $(srcdir)/config/udivmodsi4.c \ + $(srcdir)/config/memcmp.c $(srcdir)/config/memcpy.c \ + $(srcdir)/config/memmove.c $(srcdir)/config/memset.c +# floating point emulation libraries + +FPBIT = fp-bit.c +DPBIT = dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +MULTILIB_OPTIONS = msoft-float + +# Because the pdp11 POINTER_SIZE is only 16, in dwarf2out.c, +# DWARF_ARANGES_PAD_SIZE is 0, thus a loop in output_aranges that checks +# (i < (unsigned) DWARF_ARANGES_PAD_SIZE) elicits a warning that the +# comparison is always false. +# We could say "-Werror -Wno-error=type-limits", alas, not all supported +# gcc bootstrap compilers support the latter option. +dwarf2out.o-warn = -Wno-error |