diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/sh')
38 files changed, 1187 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/sh/20080410-1.c b/gcc/testsuite/gcc.target/sh/20080410-1.c new file mode 100644 index 000000000..0ba7792c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/20080410-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target "sh-*-*" } } */ +/* { dg-options "-O0 -m4 -ml" } */ +/* { dg-final { scan-assembler-not "add\tr0,r0" } } */ + +/* This test checks that chain reloads conflict. I they don't + conflict, the same hard register R0 is used for the both reloads + but in this case the second reload needs an intermediate register + (which is the reload register). As the result we have the + following code + + mov #4,r0 -- first reload + mov r14,r0 -- second reload + add r0,r0 -- second reload + + The right code should be + + mov #4,r0 -- first reload + mov r14,r1 -- second reload + add r0,r1 -- second reload + +*/ + +_Complex float foo_float (); + +void bar_float () +{ + __real foo_float (); +} diff --git a/gcc/testsuite/gcc.target/sh/mfmovd.c b/gcc/testsuite/gcc.target/sh/mfmovd.c new file mode 100644 index 000000000..c8e0094f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/mfmovd.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mfmovd" } */ +/* { dg-skip-if "No double precision FPU support" { "sh*-*-*" } "-m2a-nofpu -m2a-single-only -m4-nofpu -m4-single-only -m4a-nofpu -m4a-single-only" { "" } } */ +/* { dg-final { scan-assembler "fmov.d"} } */ + +extern double g; + +void +f (double d) +{ + g = d; +} + diff --git a/gcc/testsuite/gcc.target/sh/pr21255-1.c b/gcc/testsuite/gcc.target/sh/pr21255-1.c new file mode 100644 index 000000000..5d5b6d7f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr21255-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ +/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh-*-* } } } */ +/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh[1234lb]*-*-* } } } */ +/* { dg-final { scan-assembler "mov fr0,fr.; mov fr1,fr." { target sh[56]*-*-* } } } */ +double +f (double d) +{ + double r; + +#if defined (__SH_FPU_DOUBLE__) + asm ("mov %S1,%S0; mov %R1,%R0" : "=f" (r) : "f" (d)); +#else + asm ("mov fr4,fr4; mov fr5,fr5"); +#endif + return r; +} diff --git a/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c b/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c new file mode 100644 index 000000000..ac2ce687e --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mb -O2 -fomit-frame-pointer" } */ +/* { dg-final { scan-assembler "mov @r.,r.; mov @\\(4,r.\\),r." } } */ +double d; + +double +f (void) +{ + double r; + +/* If -ml from the target options is passed after -mb from dg-options, we + end up with th reverse endianness. */ +#if TARGET_SHMEDIA || defined (__LITTLE_ENDIAN__) + asm ("mov @r1,r3; mov @(4,r1),r4"); +#else + asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d)); +#endif + return r; +} diff --git a/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c new file mode 100644 index 000000000..c63a573ea --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-ml -O2 -fomit-frame-pointer" } */ +/* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */ +double d; + +double +f (void) +{ + double r; + +/* If -mb from the target options is passed after -ml from dg-options, we + end up with th reverse endianness. */ +#if TARGET_SHMEDIA || defined (__BIG_ENDIAN__) + asm ("mov @(4,r1),r4; mov @r1,r3"); +#else + asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d)); +#endif + return r; +} diff --git a/gcc/testsuite/gcc.target/sh/pr21255-3.c b/gcc/testsuite/gcc.target/sh/pr21255-3.c new file mode 100644 index 000000000..7edd8cb7c --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr21255-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ +/* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */ +/* { dg-final { scan-assembler "mov #?1077149696,r.*; mov #?0,r" } } */ +double +f () +{ + double r; + + asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (20)); + asm ("mov %S1,%S0; mov %R1,%R0" : "+r" (r) : "i" (20.)); + return r; +} diff --git a/gcc/testsuite/gcc.target/sh/pr21255-4.c b/gcc/testsuite/gcc.target/sh/pr21255-4.c new file mode 100644 index 000000000..c848c26c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr21255-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { sh*-*-* && nonpic } } } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +double +f () +{ + double r; + + asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (f)); +/* { dg-error "invalid operand to %S" "" {target "sh*-*-*" } 9 } */ +/* { dg-error "invalid operand to %R" "" {target "sh*-*-*" } 9 } */ + return r; +} diff --git a/gcc/testsuite/gcc.target/sh/pr43417.c b/gcc/testsuite/gcc.target/sh/pr43417.c new file mode 100644 index 000000000..081ff46b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr43417.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m4" } */ + +int pid_count = 0; +main (int argc, char *argv[]) +{ + unsigned int c; + unsigned long long maxbytes = 0; + extern char *optarg; + int i; + int pid_cntr; + int pid; + int pid_list[1000]; + while ((c = getopt (argc, argv, "c:b:p:wvh")) != (-1)) + { + switch ((char) c) + { + case 'b': + maxbytes = atoll (optarg); + } + } + pid = fork (); + while ((pid != 0) && (maxbytes > 1024 * 1024 * 1024)) + { + maxbytes = maxbytes - (1024 * 1024 * 1024); + pid = fork (); + if (pid != 0) + pid_cntr++; + pid_list[i] = pid; + } + while ((pid_count < pid_cntr)) + { + } + kill (pid_list[i], 9); +} + diff --git a/gcc/testsuite/gcc.target/sh/rte-delay-slot.c b/gcc/testsuite/gcc.target/sh/rte-delay-slot.c new file mode 100644 index 000000000..eca5db943 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/rte-delay-slot.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target "sh-*-*" } } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m1 -m2*" } */ +/* { dg-final { scan-assembler-not "\trte\t\n\tmov.l\t@r15\\+" } } */ + +/* This test checks if the compiler generates a pop instruction + in the delay slot after rte. For the sh and sh2, the rte + instruction reads the return pc from the stack and any pop + in the delay slot crashes the hardware. + + Incorrect code generated + mov.l @r15+,r1 + rte + mov.l @r15+,r14 + + The right code should be + + mov.l @r15+,r1 + mov.l @r15+,r14 + rte + nop +*/ +void INT_MTU2_1_TGIA1 (void) + __attribute__ ((interrupt_handler)); +void +INT_MTU2_1_TGIA1 (void) +{ + volatile int i = 0; + volatile int x, y; + + for (i = 0; i < 10; i++) + y = y + x; +} diff --git a/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c b/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c new file mode 100644 index 000000000..f8c2ffef4 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c @@ -0,0 +1,5 @@ +/* Check that -mrelax produces the correct error message. */ +/* { dg-do compile { target { sh-*-vxworks* && nonpic } } } */ +/* { dg-error "-mrelax is only supported for RTP PIC" "" { target *-*-* } 0 } */ +/* { dg-options "-O1 -mrelax" } */ +int x; diff --git a/gcc/testsuite/gcc.target/sh/sh-relax.c b/gcc/testsuite/gcc.target/sh/sh-relax.c new file mode 100644 index 000000000..54422de46 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh-relax.c @@ -0,0 +1,41 @@ +/* Check that -mrelax works. */ +/* { dg-do run { target { { sh-*-* sh?-*-* } && { ! { sh*-*-vxworks* && nonpic } } } } } */ +/* { dg-options "-O1 -mrelax" } */ + +extern void abort (void); +extern int qwerty (int); + +int +f (int i) +{ + return qwerty (i) + 1; +} + +int +qwerty (int i) +{ + switch (i) + { + case 1: + return 'q'; + case 2: + return 'w'; + case 3: + return 'e'; + case 4: + return 'r'; + case 5: + return 't'; + case 6: + return 'y'; + } +} + +int +main () +{ + if (f (1) != 'q' + 1 || f (2) != 'w' + 1 || f (3) != 'e' + 1 + || f(4) != 'r' + 1 || f (5) != 't' + 1 || f (6) != 'y' + 1) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh.exp b/gcc/testsuite/gcc.target/sh/sh.exp new file mode 100644 index 000000000..9389d4455 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh.exp @@ -0,0 +1,41 @@ +# Copyright (C) 2007 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a sh target. +if ![istarget sh*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/sh/sh2a-band.c b/gcc/testsuite/gcc.target/sh/sh2a-band.c new file mode 100644 index 000000000..34862b725 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-band.c @@ -0,0 +1,91 @@ +/* Testcase to check generation of a SH2A specific instruction for + "BAND.B #imm3, @(disp12, Rn)". */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1 -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "band.b"} } */ + +volatile struct +{ + union + { + unsigned char BYTE; + struct + { + unsigned char BIT7:1; + unsigned char BIT6:1; + unsigned char BIT5:1; + unsigned char BIT4:1; + unsigned char BIT3:1; + unsigned char BIT2:1; + unsigned char BIT1:1; + unsigned char BIT0:1; + } + BIT; + } + ICR0; +} +USRSTR; + +volatile union t_IOR +{ + unsigned short WORD; + struct + { + unsigned char IOR15:1; + unsigned char IOR14:1; + unsigned char IOR13:1; + unsigned char IOR12:1; + unsigned char IOR11:1; + unsigned char IOR10:1; + unsigned char IOR9:1; + unsigned char IOR8:1; + unsigned char IOR7:1; + unsigned char IOR6:1; + unsigned char IOR5:1; + unsigned char IOR4:1; + unsigned char IOR3:1; + unsigned char IOR2:1; + unsigned char IOR1:1; + unsigned char IOR0:1; + } + BIT; +} +PORT; + +int +main () +{ + volatile unsigned char a; + + /* Instruction generated is BAND.B #imm3, @(disp12, Rn) */ + USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; + USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 & USRSTR.ICR0.BIT.BIT6; + USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; + USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 & USRSTR.ICR0.BIT.BIT3; + + a = USRSTR.ICR0.BIT.BIT0 & USRSTR.ICR0.BIT.BIT1; + a = USRSTR.ICR0.BIT.BIT5 & USRSTR.ICR0.BIT.BIT7; + a = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT6; + + PORT.BIT.IOR13 = PORT.BIT.IOR0 & USRSTR.ICR0.BIT.BIT7; + PORT.BIT.IOR15 = PORT.BIT.IOR6 & USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR3 = PORT.BIT.IOR2 & USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR1 = PORT.BIT.IOR13 & USRSTR.ICR0.BIT.BIT1; + + PORT.BIT.IOR1 = PORT.BIT.IOR2 & USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR11 = PORT.BIT.IOR9 & USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR8 = PORT.BIT.IOR14 & USRSTR.ICR0.BIT.BIT5; + + PORT.BIT.IOR10 &= USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR1 &= USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR5 &= USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; + + /* Instruction generated on using size optimization option "-Os". */ + a = a & USRSTR.ICR0.BIT.BIT1; + a = a & USRSTR.ICR0.BIT.BIT4; + a = a & USRSTR.ICR0.BIT.BIT0; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bclr.c b/gcc/testsuite/gcc.target/sh/sh2a-bclr.c new file mode 100644 index 000000000..d4e11f952 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bclr.c @@ -0,0 +1,57 @@ +/* Testcase to check generation of a SH2A specific instruction + 'BCLR #imm3,Rn'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bclr"} } */ + +struct a +{ + char a, b; + short c; +}; + +/* This function generates the instruction "BCLR #imm3,Rn" only + on using optimization option "-O1" and above. */ + +int +a2 () +{ + volatile int j; + volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2}; + + if (j > 1) + return (x.a == y.a && (x.b & ~1) == y.b); + if (j > 2) + return (x.a == y.a && (x.b & ~2) == y.b); + if (j > 3) + return (x.a == y.a && (x.b & ~4) == y.b); + if (j > 4) + return (x.a == y.a && (x.b & ~8) == y.b); + if (j > 5) + return (x.a == y.a && (x.b & ~16) == y.b); + if (j > 6) + return (x.a == y.a && (x.b & ~32) == y.b); + if (j > 7) + return (x.a == y.a && (x.b & ~64) == y.b); + if (j > 8) + return (x.a == y.a && (x.b & ~128) == y.b); +} + +int +main () +{ + volatile unsigned char x; + + x &= 0xFE; + x &= 0xFD; + x &= 0xFB; + x &= 0xF7; + x &= 0xEF; + x &= 0xDF; + x &= 0xBF; + x &= 0x7F; + + if (!a2 ()) + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c new file mode 100644 index 000000000..41cb3bdfe --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c @@ -0,0 +1,55 @@ +/* Testcase to check generation of a SH2A specific instruction + "BCLR #imm3,@(disp12,Rn)". */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O2 -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bclr"} } */ +/* { dg-final { scan-assembler "bclr.b"} } */ + +volatile union un_paddr +{ + unsigned char BYTE; + struct + { + unsigned char B15:1; + unsigned char B14:1; + unsigned char B13:1; + unsigned char B12:1; + unsigned char B11:1; + unsigned char B10:1; + unsigned char B9:1; + unsigned char B8:1; + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } + BIT; +} +PADDR; + +int +main () +{ + PADDR.BIT.B0 = 0; + PADDR.BIT.B3 = 0; + PADDR.BIT.B6 = 0; + + PADDR.BIT.B1 &= 0; + PADDR.BIT.B4 &= 0; + PADDR.BIT.B7 &= 0; + + PADDR.BIT.B10 = 0; + PADDR.BIT.B13 = 0; + PADDR.BIT.B15 = 0; + + PADDR.BIT.B9 &= 0; + PADDR.BIT.B12 &= 0; + PADDR.BIT.B14 &= 0; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bld.c b/gcc/testsuite/gcc.target/sh/sh2a-bld.c new file mode 100644 index 000000000..1cf56fe27 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bld.c @@ -0,0 +1,43 @@ +/* A testcase to check generation of the following SH2A specific + instructions. + + BLD #imm3, Rn + BLD.B #imm3, @(disp12, Rn) + */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-Os -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bld"} } */ +/* { dg-final { scan-assembler "bld.b"} } */ + +volatile struct +{ + union + { + unsigned char BYTE; + struct + { + unsigned char BIT7:1; + unsigned char BIT6:1; + unsigned char BIT5:1; + unsigned char BIT4:1; + unsigned char BIT3:1; + unsigned char BIT2:1; + unsigned char BIT1:1; + unsigned char BIT0:1; + } + BIT; + } + ICR0; +} +USRSTR; + +int +main () +{ + volatile unsigned char a, b, c; + USRSTR.ICR0.BIT.BIT6 &= a; + USRSTR.ICR0.BIT.BIT5 |= b; + USRSTR.ICR0.BIT.BIT4 ^= c; + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bor.c b/gcc/testsuite/gcc.target/sh/sh2a-bor.c new file mode 100644 index 000000000..c3803c6b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bor.c @@ -0,0 +1,91 @@ +/* Testcase to check generation of a SH2A specific instruction for + "BOR.B #imm3, @(disp12, Rn)". */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1 -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bor.b"} } */ + +volatile struct +{ + union + { + unsigned char BYTE; + struct + { + unsigned char BIT7:1; + unsigned char BIT6:1; + unsigned char BIT5:1; + unsigned char BIT4:1; + unsigned char BIT3:1; + unsigned char BIT2:1; + unsigned char BIT1:1; + unsigned char BIT0:1; + } + BIT; + } + ICR0; +} +USRSTR; + +volatile union t_IOR +{ + unsigned short WORD; + struct + { + unsigned char IOR15:1; + unsigned char IOR14:1; + unsigned char IOR13:1; + unsigned char IOR12:1; + unsigned char IOR11:1; + unsigned char IOR10:1; + unsigned char IOR9:1; + unsigned char IOR8:1; + unsigned char IOR7:1; + unsigned char IOR6:1; + unsigned char IOR5:1; + unsigned char IOR4:1; + unsigned char IOR3:1; + unsigned char IOR2:1; + unsigned char IOR1:1; + unsigned char IOR0:1; + } + BIT; +} +PORT; + +int +main () +{ + volatile unsigned char a; + + /* Instruction generated is BOR.B #imm3, @(disp12, Rn) */ + USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; + USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 | USRSTR.ICR0.BIT.BIT6; + USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; + USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 | USRSTR.ICR0.BIT.BIT3; + + a = USRSTR.ICR0.BIT.BIT0 | USRSTR.ICR0.BIT.BIT1; + a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7; + a = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT6; + + PORT.BIT.IOR13 = PORT.BIT.IOR0 | USRSTR.ICR0.BIT.BIT7; + PORT.BIT.IOR15 = PORT.BIT.IOR6 | USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR3 = PORT.BIT.IOR2 | USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR1 = PORT.BIT.IOR13 | USRSTR.ICR0.BIT.BIT1; + + PORT.BIT.IOR1 = PORT.BIT.IOR2 | USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR11 = PORT.BIT.IOR9 | USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR8 = PORT.BIT.IOR14 | USRSTR.ICR0.BIT.BIT5; + + PORT.BIT.IOR10 |= USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR1 |= USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR5 |= USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; + + /* Instruction generated on using size optimization option "-Os". */ + a = a & USRSTR.ICR0.BIT.BIT1; + a = a & USRSTR.ICR0.BIT.BIT4; + a = a & USRSTR.ICR0.BIT.BIT0; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bset.c b/gcc/testsuite/gcc.target/sh/sh2a-bset.c new file mode 100644 index 000000000..b64852b4c --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bset.c @@ -0,0 +1,57 @@ +/* Testcase to check generation of a SH2A specific instruction + 'BSET #imm3,Rn'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bset"} } */ + +struct a +{ + char a, b; + short c; +}; + +/* This function generates the instruction "BSET #imm3,Rn" only + on using optimization option "-O1" and above. */ + +int +a2 () +{ + volatile int j; + volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2}; + + if (j > 1) + return (x.a == y.a && (x.b | 1) == y.b); + if (j > 2) + return (x.a == y.a && (x.b | 2) == y.b); + if (j > 3) + return (x.a == y.a && (x.b | 4) == y.b); + if (j > 4) + return (x.a == y.a && (x.b | 8) == y.b); + if (j > 5) + return (x.a == y.a && (x.b | 16) == y.b); + if (j > 6) + return (x.a == y.a && (x.b | 32) == y.b); + if (j > 7) + return (x.a == y.a && (x.b | 64) == y.b); + if (j > 8) + return (x.a == y.a && (x.b | 128) == y.b); +} + +int +main () +{ + volatile unsigned char x; + + x |= 0x1; + x |= 0x2; + x |= 0x4; + x |= 0x8; + x |= 0x16; + x |= 0x32; + x |= 0x64; + x |= 0x128; + + if (!a2 ()) + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c new file mode 100644 index 000000000..b0ebf0851 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c @@ -0,0 +1,55 @@ +/* Testcase to check generation of a SH2A specific instruction + "BSET #imm3,@(disp12,Rn)". */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O2 -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bset"} } */ +/* { dg-final { scan-assembler "bset.b"} } */ + +volatile union un_paddr +{ + unsigned char BYTE; + struct + { + unsigned char B15:1; + unsigned char B14:1; + unsigned char B13:1; + unsigned char B12:1; + unsigned char B11:1; + unsigned char B10:1; + unsigned char B9:1; + unsigned char B8:1; + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } + BIT; +} +PADDR; + +int +main () +{ + PADDR.BIT.B0 = 1; + PADDR.BIT.B3 = 1; + PADDR.BIT.B6 = 1; + + PADDR.BIT.B1 |= 1; + PADDR.BIT.B4 |= 1; + PADDR.BIT.B7 |= 1; + + PADDR.BIT.B10 = 1; + PADDR.BIT.B13 = 1; + PADDR.BIT.B15 = 1; + + PADDR.BIT.B9 |= 1; + PADDR.BIT.B12 |= 1; + PADDR.BIT.B14 |= 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-bxor.c b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c new file mode 100644 index 000000000..afe0a5ec9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-bxor.c @@ -0,0 +1,91 @@ +/* Testcase to check generation of a SH2A specific instruction for + "BXOR.B #imm3, @(disp12, Rn)". */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1 -mbitops" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "bxor.b"} } */ + +volatile struct +{ + union + { + unsigned char BYTE; + struct + { + unsigned char BIT7:1; + unsigned char BIT6:1; + unsigned char BIT5:1; + unsigned char BIT4:1; + unsigned char BIT3:1; + unsigned char BIT2:1; + unsigned char BIT1:1; + unsigned char BIT0:1; + } + BIT; + } + ICR0; +} +USRSTR; + +volatile union t_IOR +{ + unsigned short WORD; + struct + { + unsigned char IOR15:1; + unsigned char IOR14:1; + unsigned char IOR13:1; + unsigned char IOR12:1; + unsigned char IOR11:1; + unsigned char IOR10:1; + unsigned char IOR9:1; + unsigned char IOR8:1; + unsigned char IOR7:1; + unsigned char IOR6:1; + unsigned char IOR5:1; + unsigned char IOR4:1; + unsigned char IOR3:1; + unsigned char IOR2:1; + unsigned char IOR1:1; + unsigned char IOR0:1; + } + BIT; +} +PORT; + +int +main () +{ + volatile unsigned char a; + + /* Instruction generated is BXOR.B #imm3, @(disp12, Rn) */ + USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1; + USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 ^ USRSTR.ICR0.BIT.BIT6; + USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4; + USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 ^ USRSTR.ICR0.BIT.BIT3; + + a = USRSTR.ICR0.BIT.BIT0 ^ USRSTR.ICR0.BIT.BIT1; + a = USRSTR.ICR0.BIT.BIT5 ^ USRSTR.ICR0.BIT.BIT7; + a = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT6; + + PORT.BIT.IOR13 = PORT.BIT.IOR0 ^ USRSTR.ICR0.BIT.BIT7; + PORT.BIT.IOR15 = PORT.BIT.IOR6 ^ USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR3 = PORT.BIT.IOR2 ^ USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR1 = PORT.BIT.IOR13 ^ USRSTR.ICR0.BIT.BIT1; + + PORT.BIT.IOR1 = PORT.BIT.IOR2 ^ USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR11 = PORT.BIT.IOR9 ^ USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR8 = PORT.BIT.IOR14 ^ USRSTR.ICR0.BIT.BIT5; + + PORT.BIT.IOR10 ^= USRSTR.ICR0.BIT.BIT1; + PORT.BIT.IOR1 ^= USRSTR.ICR0.BIT.BIT2; + PORT.BIT.IOR5 ^= USRSTR.ICR0.BIT.BIT5; + PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4; + + /* Instruction generated on using size optimization option "-Os". */ + a = a ^ USRSTR.ICR0.BIT.BIT1; + a = a ^ USRSTR.ICR0.BIT.BIT4; + a = a ^ USRSTR.ICR0.BIT.BIT0; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c b/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c new file mode 100644 index 000000000..9b9b92cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c @@ -0,0 +1,15 @@ +/* Testcase to check generation of a SH2A specific instruction for + 'JSR/N @Rm'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O0" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "jsr/n"} } */ + +void foo(void) +{ +} + +void bar() +{ + foo(); +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c b/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c new file mode 100644 index 000000000..55d2f665b --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c @@ -0,0 +1,14 @@ +/* Testcase to check generation of 'MOVI20S #imm20, Rn'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O0" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "movi20s"} } */ + +volatile long la; + +void +testfun (void) +{ + la = -134217728; + la = 134217216; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-movrt.c b/gcc/testsuite/gcc.target/sh/sh2a-movrt.c new file mode 100644 index 000000000..9df9f4ba9 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-movrt.c @@ -0,0 +1,15 @@ +/* Testcase to check generation of a SH2A specific instruction for + 'MOVRT Rn'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O1" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "movrt"} } */ + +int +foo (void) +{ + int a, b, g, stop; + if (stop = ((a + b) % 2 != g)) + ; + return stop; +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c b/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c new file mode 100644 index 000000000..e0c9a0d7d --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c @@ -0,0 +1,34 @@ +/* Testcase to check generation of a SH2A specific instruction PREF @Rm. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O0" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "pref"} } */ + +void +opt (void) +{ + int *p, wk; + int data[100]; + + /* data prefetch , instructions hit the cache. */ + + __builtin_prefetch (&data[0], 0, 0); + __builtin_prefetch (&data[0], 0, 1); + __builtin_prefetch (&data[0], 0, 2); + __builtin_prefetch (&data[0], 0, 3); + __builtin_prefetch (&data[0], 1, 0); + __builtin_prefetch (&data[0], 1, 1); + __builtin_prefetch (&data[0], 1, 2); + __builtin_prefetch (&data[0], 1, 3); + + + for (p = &data[0]; p < &data[9]; p++) + { + if (*p > *(p + 1)) + { + wk = *p; + *p = *(p + 1); + *(p + 1) = wk; + } + } +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-resbank.c b/gcc/testsuite/gcc.target/sh/sh2a-resbank.c new file mode 100644 index 000000000..aab6852f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-resbank.c @@ -0,0 +1,12 @@ +/* Test for resbank attribute. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "resbank" } } */ + +extern void bar(void); + +void foo(void) __attribute__((interrupt_handler, resbank)); +void foo(void) +{ + bar(); +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c b/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c new file mode 100644 index 000000000..2601ced5c --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c @@ -0,0 +1,11 @@ +/* Testcase to check generation of a SH2A specific instruction for + 'RTS/N'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "-O0" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler "rts/n"} } */ + +void +bar (void) +{ +} diff --git a/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c b/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c new file mode 100644 index 000000000..8029b03dd --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c @@ -0,0 +1,22 @@ +/* Testcase to check generation of a SH2A specific, + TBR relative jump instruction - 'JSR @@(disp8,TBR)'. */ +/* { dg-do assemble {target sh*-*-*}} */ +/* { dg-options "" } */ +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */ +/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */ +/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(72,tbr\\)" 1} } */ + +extern void foo1 (void) __attribute__ ((function_vector(10))); +extern void foo2 (void); +extern int bar1 (void) __attribute__ ((function_vector(18))); +extern int bar2 (void); + +int +bar() +{ + foo1(); + foo2(); + + bar1(); + bar2(); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c new file mode 100644 index 000000000..761c7b0b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c @@ -0,0 +1,73 @@ +/* Verify that we generate movua to load unaligned 32-bit values. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler-times "\tmovua\\.l\t" 6 } } */ + +#ifdef __SH4A__ +/* Aligned. */ +struct s0 { long long d : 32; } x0; +long long f0() { + return x0.d; +} + +/* Unaligned load. */ +struct s1 { long long c : 8; long long d : 32; } x1; +long long f1() { + return x1.d; +} + +/* Unaligned load. */ +struct s2 { long long c : 16; long long d : 32; } x2; +long long f2() { + return x2.d; +} + +/* Unaligned load. */ +struct s3 { long long c : 24; long long d : 32; } x3; +long long f3() { + return x3.d; +} + +/* Aligned. */ +struct s4 { long long c : 32; long long d : 32; } x4; +long long f4() { + return x4.d; +} + +/* Aligned. */ +struct u0 { unsigned long long d : 32; } y_0; +unsigned long long g0() { + return y_0.d; +} + +/* Unaligned load. */ +struct u1 { long long c : 8; unsigned long long d : 32; } y_1; +unsigned long long g1() { + return y_1.d; +} + +/* Unaligned load. */ +struct u2 { long long c : 16; unsigned long long d : 32; } y2; +unsigned long long g2() { + return y2.d; +} + +/* Unaligned load. */ +struct u3 { long long c : 24; unsigned long long d : 32; } y3; +unsigned long long g3() { + return y3.d; +} + +/* Aligned. */ +struct u4 { long long c : 32; unsigned long long d : 32; } y4; +unsigned long long g4() { + return y4.d; +} +#else +asm ("movua.l\t"); +asm ("movua.l\t"); +asm ("movua.l\t"); +asm ("movua.l\t"); +asm ("movua.l\t"); +asm ("movua.l\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-cos.c b/gcc/testsuite/gcc.target/sh/sh4a-cos.c new file mode 100644 index 000000000..198d41f86 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-cos.c @@ -0,0 +1,13 @@ +/* Verify that we generate single-precision sine and cosine approximate + (fsca) in fast math mode. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler "\tfsca\t" } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +double test(double f) { return cos(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-cosf.c b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c new file mode 100644 index 000000000..f78c140d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-cosf.c @@ -0,0 +1,13 @@ +/* Verify that we generate single-precision sine and cosine approximate + (fsca) in fast math mode. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler "\tfsca\t" } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +float test(float f) { return cosf(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-fprun.c b/gcc/testsuite/gcc.target/sh/sh4a-fprun.c new file mode 100644 index 000000000..40c2b05aa --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-fprun.c @@ -0,0 +1,37 @@ +/* Verify that fsca and fssra yield reasonable results. */ +/* This test calls the sinf and cosf library functions for targets other + than sh4a, but the VxWorks kernel doesn't have those functions. */ +/* { dg-do run { target { "sh*-*-*" && { ! vxworks_kernel } } } } */ +/* { dg-options "-O -ffast-math" } */ + +#include <math.h> +#include <stdlib.h> + +float sqrt_arg = 4.0f, sqrt_res = 2.0f; +float dg2rad_f; +double dg2rad_d; + +void check_f (float res, float expected) { + if (res >= expected - 0.001f && res <= expected + 0.001f) + return; + + abort (); +} + +void check_d (double res, double expected) { + if (res >= expected - 0.001 && res <= expected + 0.001) + return; + + abort (); +} + +int main() { + check_f (sqrtf(sqrt_arg), sqrt_res); + dg2rad_f = dg2rad_d = atan(1) / 45; + check_f (sinf(90*dg2rad_f), 1); + check_f (cosf(90*dg2rad_f), 0); + check_d (sin(-90*dg2rad_d), -1); + check_d (cos(180*dg2rad_d), -1); + check_d (sin(-45*dg2rad_d) * cosf(135*dg2rad_f), 0.5); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c new file mode 100644 index 000000000..c8f04e4d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c @@ -0,0 +1,13 @@ +/* Verify that we generate single-precision square root reciprocal + approximate (fsrra) in fast math mode. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler "\tfsrra\t" } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +float test(float f) { return 1 / sqrtf(f); } +#else +asm ("fsrra\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c new file mode 100644 index 000000000..359dd8feb --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c @@ -0,0 +1,17 @@ +/* Verify that we generate movua to copy unaligned memory regions to + 32-bit-aligned addresses. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler-times "\tmovua\\.l\t" 2 } } */ + +#ifdef __SH4A__ +#include <string.h> + +struct s { int i; char a[10], b[10]; } x; +int f() { + memcpy(x.a, x.b, 10); +} +#else +asm ("movua.l\t+"); +asm ("movua.l\t+"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sin.c b/gcc/testsuite/gcc.target/sh/sh4a-sin.c new file mode 100644 index 000000000..9f46f6007 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-sin.c @@ -0,0 +1,13 @@ +/* Verify that we generate single-precision sine and cosine approximate + (fsca) in fast math mode. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler "\tfsca\t" } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +double test(double f) { return sin(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sincos.c b/gcc/testsuite/gcc.target/sh/sh4a-sincos.c new file mode 100644 index 000000000..f42937975 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-sincos.c @@ -0,0 +1,14 @@ +/* Verify that we generate a single single-precision sine and cosine + approximate (fsca) in fast math mode when a function computes both + sine and cosine. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +double test(double f) { return sin(f) + cos(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c new file mode 100644 index 000000000..42913dbd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c @@ -0,0 +1,14 @@ +/* Verify that we generate a single single-precision sine and cosine + approximate (fsca) in fast math mode when a function computes both + sine and cosine. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +float test(float f) { return sinf(f) + cosf(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/sh4a-sinf.c b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c new file mode 100644 index 000000000..2a2343fd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/sh4a-sinf.c @@ -0,0 +1,13 @@ +/* Verify that we generate single-precision sine and cosine approximate + (fsca) in fast math mode. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O -ffast-math" } */ +/* { dg-final { scan-assembler "\tfsca\t" } } */ + +#if defined __SH4A__ && ! defined __SH4_NOFPU__ +#include <math.h> + +float test(float f) { return sinf(f); } +#else +asm ("fsca\t"); +#endif diff --git a/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c b/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c new file mode 100644 index 000000000..effd13d19 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c @@ -0,0 +1,26 @@ +/* Verify that we don't generate fame related insn against stack adjustment + for the object sent partially in registers. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-g" } */ +/* { dg-final { scan-assembler-not "\t.cfi_def_cfa_offset 16" } } */ + +typedef struct +{ + unsigned short A1; + unsigned short A2; +} A_t; + +typedef struct +{ + A_t C13[10]; +} C_t; + +void +Store (C_t Par) +{ + unsigned char *ptr; + unsigned int test; + + ptr = (unsigned char*) 0x12345678; + ptr++; +} |