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-rw-r--r--libgcc/config/lm32/_ashlsi3.S114
-rw-r--r--libgcc/config/lm32/_ashrsi3.S110
-rw-r--r--libgcc/config/lm32/_divsi3.c99
-rw-r--r--libgcc/config/lm32/_lshrsi3.S109
-rw-r--r--libgcc/config/lm32/_modsi3.c71
-rw-r--r--libgcc/config/lm32/_mulsi3.c48
-rw-r--r--libgcc/config/lm32/_udivmodsi4.c53
-rw-r--r--libgcc/config/lm32/_udivsi3.c49
-rw-r--r--libgcc/config/lm32/_umodsi3.c49
-rw-r--r--libgcc/config/lm32/crti.S40
-rw-r--r--libgcc/config/lm32/crtn.S37
-rw-r--r--libgcc/config/lm32/libgcc_lm32.h43
-rw-r--r--libgcc/config/lm32/t-elf12
-rw-r--r--libgcc/config/lm32/t-lm3210
-rw-r--r--libgcc/config/lm32/t-uclinux2
15 files changed, 846 insertions, 0 deletions
diff --git a/libgcc/config/lm32/_ashlsi3.S b/libgcc/config/lm32/_ashlsi3.S
new file mode 100644
index 000000000..1f8f48d93
--- /dev/null
+++ b/libgcc/config/lm32/_ashlsi3.S
@@ -0,0 +1,114 @@
+# _ashlsi3.S for Lattice Mico32
+# Contributed by Jon Beniston <jon@beniston.com> and Richard Henderson.
+#
+# Copyright (C) 2009 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+#
+
+/* Arithmetic left shift. */
+
+ .text
+
+ .global __ashlsi3
+ .type __ashlsi3,@function
+
+ .align 4
+__ashlsi3:
+ /* Only use 5 LSBs, as that's all the h/w shifter uses. */
+ andi r2, r2, 0x1f
+ /* Get address of offset into unrolled shift loop to jump to. */
+#ifdef __PIC__
+ lw r3, (gp+got(__ashlsi3_0))
+#else
+ mvhi r3, hi(__ashlsi3_0)
+ ori r3, r3, lo(__ashlsi3_0)
+#endif
+ add r2, r2, r2
+ add r2, r2, r2
+ sub r3, r3, r2
+ b r3
+
+__ashlsi3_31:
+ add r1, r1, r1
+__ashlsi3_30:
+ add r1, r1, r1
+__ashlsi3_29:
+ add r1, r1, r1
+__ashlsi3_28:
+ add r1, r1, r1
+__ashlsi3_27:
+ add r1, r1, r1
+__ashlsi3_26:
+ add r1, r1, r1
+__ashlsi3_25:
+ add r1, r1, r1
+__ashlsi3_24:
+ add r1, r1, r1
+__ashlsi3_23:
+ add r1, r1, r1
+__ashlsi3_22:
+ add r1, r1, r1
+__ashlsi3_21:
+ add r1, r1, r1
+__ashlsi3_20:
+ add r1, r1, r1
+__ashlsi3_19:
+ add r1, r1, r1
+__ashlsi3_18:
+ add r1, r1, r1
+__ashlsi3_17:
+ add r1, r1, r1
+__ashlsi3_16:
+ add r1, r1, r1
+__ashlsi3_15:
+ add r1, r1, r1
+__ashlsi3_14:
+ add r1, r1, r1
+__ashlsi3_13:
+ add r1, r1, r1
+__ashlsi3_12:
+ add r1, r1, r1
+__ashlsi3_11:
+ add r1, r1, r1
+__ashlsi3_10:
+ add r1, r1, r1
+__ashlsi3_9:
+ add r1, r1, r1
+__ashlsi3_8:
+ add r1, r1, r1
+__ashlsi3_7:
+ add r1, r1, r1
+__ashlsi3_6:
+ add r1, r1, r1
+__ashlsi3_5:
+ add r1, r1, r1
+__ashlsi3_4:
+ add r1, r1, r1
+__ashlsi3_3:
+ add r1, r1, r1
+__ashlsi3_2:
+ add r1, r1, r1
+__ashlsi3_1:
+ add r1, r1, r1
+__ashlsi3_0:
+ ret
+
+ \ No newline at end of file
diff --git a/libgcc/config/lm32/_ashrsi3.S b/libgcc/config/lm32/_ashrsi3.S
new file mode 100644
index 000000000..393cbeb54
--- /dev/null
+++ b/libgcc/config/lm32/_ashrsi3.S
@@ -0,0 +1,110 @@
+# _ashrsi3.S for Lattice Mico32
+# Contributed by Jon Beniston <jon@beniston.com> and Richard Henderson.
+#
+# Copyright (C) 2009 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+#
+
+/* Arithmetic right shift. */
+
+ .global __ashrsi3
+ .type __ashrsi3,@function
+
+__ashrsi3:
+ /* Only use 5 LSBs, as that's all the h/w shifter uses. */
+ andi r2, r2, 0x1f
+ /* Get address of offset into unrolled shift loop to jump to. */
+#ifdef __PIC__
+ lw r3, (gp+got(__ashrsi3_0))
+#else
+ mvhi r3, hi(__ashrsi3_0)
+ ori r3, r3, lo(__ashrsi3_0)
+#endif
+ add r2, r2, r2
+ add r2, r2, r2
+ sub r3, r3, r2
+ b r3
+
+__ashrsi3_31:
+ sri r1, r1, 1
+__ashrsi3_30:
+ sri r1, r1, 1
+__ashrsi3_29:
+ sri r1, r1, 1
+__ashrsi3_28:
+ sri r1, r1, 1
+__ashrsi3_27:
+ sri r1, r1, 1
+__ashrsi3_26:
+ sri r1, r1, 1
+__ashrsi3_25:
+ sri r1, r1, 1
+__ashrsi3_24:
+ sri r1, r1, 1
+__ashrsi3_23:
+ sri r1, r1, 1
+__ashrsi3_22:
+ sri r1, r1, 1
+__ashrsi3_21:
+ sri r1, r1, 1
+__ashrsi3_20:
+ sri r1, r1, 1
+__ashrsi3_19:
+ sri r1, r1, 1
+__ashrsi3_18:
+ sri r1, r1, 1
+__ashrsi3_17:
+ sri r1, r1, 1
+__ashrsi3_16:
+ sri r1, r1, 1
+__ashrsi3_15:
+ sri r1, r1, 1
+__ashrsi3_14:
+ sri r1, r1, 1
+__ashrsi3_13:
+ sri r1, r1, 1
+__ashrsi3_12:
+ sri r1, r1, 1
+__ashrsi3_11:
+ sri r1, r1, 1
+__ashrsi3_10:
+ sri r1, r1, 1
+__ashrsi3_9:
+ sri r1, r1, 1
+__ashrsi3_8:
+ sri r1, r1, 1
+__ashrsi3_7:
+ sri r1, r1, 1
+__ashrsi3_6:
+ sri r1, r1, 1
+__ashrsi3_5:
+ sri r1, r1, 1
+__ashrsi3_4:
+ sri r1, r1, 1
+__ashrsi3_3:
+ sri r1, r1, 1
+__ashrsi3_2:
+ sri r1, r1, 1
+__ashrsi3_1:
+ sri r1, r1, 1
+__ashrsi3_0:
+ ret
+ \ No newline at end of file
diff --git a/libgcc/config/lm32/_divsi3.c b/libgcc/config/lm32/_divsi3.c
new file mode 100644
index 000000000..1a5dda093
--- /dev/null
+++ b/libgcc/config/lm32/_divsi3.c
@@ -0,0 +1,99 @@
+/* _divsi3 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Signed integer division. */
+
+static const UQItype __divsi3_table[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 4, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 5, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 6, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 7, 3, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 8, 4, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 9, 4, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+ 0, 10, 5, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ 0, 11, 5, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
+ 0, 12, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 13, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
+ 0, 14, 7, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0,
+ 0, 15, 7, 5, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+};
+
+SItype
+__divsi3 (SItype a, SItype b)
+{
+ int neg = 0;
+ SItype res;
+ int cfg;
+
+ if (b == 0)
+ {
+ /* Raise divide by zero exception. */
+ int eba, sr;
+ /* Save interrupt enable. */
+ __asm__ __volatile__ ("rcsr %0, IE":"=r" (sr));
+ sr = (sr & 1) << 1;
+ __asm__ __volatile__ ("wcsr IE, %0"::"r" (sr));
+ /* Branch to exception handler. */
+ __asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
+ eba += 32 * 5;
+ __asm__ __volatile__ ("mv ea, ra");
+ __asm__ __volatile__ ("b %0"::"r" (eba));
+ __builtin_unreachable ();
+ }
+
+ if (((USItype) (a | b)) < 16)
+ res = __divsi3_table[(a << 4) + b];
+ else
+ {
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0)
+ {
+ b = -b;
+ neg = !neg;
+ }
+
+ __asm__ ("rcsr %0, CFG":"=r" (cfg));
+ if (cfg & 2)
+ __asm__ ("divu %0, %1, %2": "=r" (res):"r" (a), "r" (b));
+ else
+ res = __udivmodsi4 (a, b, 0);
+
+ if (neg)
+ res = -res;
+ }
+
+ return res;
+}
diff --git a/libgcc/config/lm32/_lshrsi3.S b/libgcc/config/lm32/_lshrsi3.S
new file mode 100644
index 000000000..706fd003a
--- /dev/null
+++ b/libgcc/config/lm32/_lshrsi3.S
@@ -0,0 +1,109 @@
+# _lshrsi3.S for Lattice Mico32
+# Contributed by Jon Beniston <jon@beniston.com> and Richard Henderson.
+#
+# Copyright (C) 2009 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+#
+
+/* Logical right shift. */
+
+ .global __lshrsi3
+ .type __lshrsi3,@function
+
+__lshrsi3:
+ /* Only use 5 LSBs, as that's all the h/w shifter uses. */
+ andi r2, r2, 0x1f
+ /* Get address of offset into unrolled shift loop to jump to. */
+#ifdef __PIC__
+ lw r3, (gp+got(__lshrsi3_0))
+#else
+ mvhi r3, hi(__lshrsi3_0)
+ ori r3, r3, lo(__lshrsi3_0)
+#endif
+ add r2, r2, r2
+ add r2, r2, r2
+ sub r3, r3, r2
+ b r3
+
+__lshrsi3_31:
+ srui r1, r1, 1
+__lshrsi3_30:
+ srui r1, r1, 1
+__lshrsi3_29:
+ srui r1, r1, 1
+__lshrsi3_28:
+ srui r1, r1, 1
+__lshrsi3_27:
+ srui r1, r1, 1
+__lshrsi3_26:
+ srui r1, r1, 1
+__lshrsi3_25:
+ srui r1, r1, 1
+__lshrsi3_24:
+ srui r1, r1, 1
+__lshrsi3_23:
+ srui r1, r1, 1
+__lshrsi3_22:
+ srui r1, r1, 1
+__lshrsi3_21:
+ srui r1, r1, 1
+__lshrsi3_20:
+ srui r1, r1, 1
+__lshrsi3_19:
+ srui r1, r1, 1
+__lshrsi3_18:
+ srui r1, r1, 1
+__lshrsi3_17:
+ srui r1, r1, 1
+__lshrsi3_16:
+ srui r1, r1, 1
+__lshrsi3_15:
+ srui r1, r1, 1
+__lshrsi3_14:
+ srui r1, r1, 1
+__lshrsi3_13:
+ srui r1, r1, 1
+__lshrsi3_12:
+ srui r1, r1, 1
+__lshrsi3_11:
+ srui r1, r1, 1
+__lshrsi3_10:
+ srui r1, r1, 1
+__lshrsi3_9:
+ srui r1, r1, 1
+__lshrsi3_8:
+ srui r1, r1, 1
+__lshrsi3_7:
+ srui r1, r1, 1
+__lshrsi3_6:
+ srui r1, r1, 1
+__lshrsi3_5:
+ srui r1, r1, 1
+__lshrsi3_4:
+ srui r1, r1, 1
+__lshrsi3_3:
+ srui r1, r1, 1
+__lshrsi3_2:
+ srui r1, r1, 1
+__lshrsi3_1:
+ srui r1, r1, 1
+__lshrsi3_0:
+ ret
diff --git a/libgcc/config/lm32/_modsi3.c b/libgcc/config/lm32/_modsi3.c
new file mode 100644
index 000000000..a4a3d320a
--- /dev/null
+++ b/libgcc/config/lm32/_modsi3.c
@@ -0,0 +1,71 @@
+/* _modsi3 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Signed integer modulus. */
+
+SItype
+__modsi3 (SItype a, SItype b)
+{
+ int neg = 0;
+ SItype res;
+ int cfg;
+
+ if (b == 0)
+ {
+ /* Raise divide by zero exception. */
+ int eba, sr;
+ /* Save interrupt enable. */
+ __asm__ __volatile__ ("rcsr %0, IE":"=r" (sr));
+ sr = (sr & 1) << 1;
+ __asm__ __volatile__ ("wcsr IE, %0"::"r" (sr));
+ /* Branch to exception handler. */
+ __asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
+ eba += 32 * 5;
+ __asm__ __volatile__ ("mv ea, ra");
+ __asm__ __volatile__ ("b %0"::"r" (eba));
+ __builtin_unreachable ();
+ }
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+__asm__ ("rcsr %0, CFG":"=r" (cfg));
+ if (cfg & 2)
+ __asm__ ("modu %0, %1, %2": "=r" (res):"r" (a), "r" (b));
+ else
+ res = __udivmodsi4 (a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
diff --git a/libgcc/config/lm32/_mulsi3.c b/libgcc/config/lm32/_mulsi3.c
new file mode 100644
index 000000000..5b2646b45
--- /dev/null
+++ b/libgcc/config/lm32/_mulsi3.c
@@ -0,0 +1,48 @@
+/* _mulsi3 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Integer multiplication. */
+
+USItype
+__mulsi3 (USItype a, USItype b)
+{
+ USItype result;
+
+ result = 0;
+
+ if (a == 0)
+ return 0;
+
+ while (b != 0)
+ {
+ if (b & 1)
+ result += a;
+ a <<= 1;
+ b >>= 1;
+ }
+
+ return result;
+}
diff --git a/libgcc/config/lm32/_udivmodsi4.c b/libgcc/config/lm32/_udivmodsi4.c
new file mode 100644
index 000000000..1d067630e
--- /dev/null
+++ b/libgcc/config/lm32/_udivmodsi4.c
@@ -0,0 +1,53 @@
+/* _udivmodsi4 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Unsigned integer division/modulus. */
+
+USItype
+__udivmodsi4 (USItype num, USItype den, int modwanted)
+{
+ USItype bit = 1;
+ USItype res = 0;
+
+ while (den < num && bit && !(den & (1L << 31)))
+ {
+ den <<= 1;
+ bit <<= 1;
+ }
+ while (bit)
+ {
+ if (num >= den)
+ {
+ num -= den;
+ res |= bit;
+ }
+ bit >>= 1;
+ den >>= 1;
+ }
+ if (modwanted)
+ return num;
+ return res;
+}
diff --git a/libgcc/config/lm32/_udivsi3.c b/libgcc/config/lm32/_udivsi3.c
new file mode 100644
index 000000000..284fef6cc
--- /dev/null
+++ b/libgcc/config/lm32/_udivsi3.c
@@ -0,0 +1,49 @@
+/* _udivsi3 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Unsigned integer division. */
+
+USItype
+__udivsi3 (USItype a, USItype b)
+{
+ if (b == 0)
+ {
+ /* Raise divide by zero exception. */
+ int eba, sr;
+ /* Save interrupt enable. */
+ __asm__ __volatile__ ("rcsr %0, IE":"=r" (sr));
+ sr = (sr & 1) << 1;
+ __asm__ __volatile__ ("wcsr IE, %0"::"r" (sr));
+ /* Branch to exception handler. */
+ __asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
+ eba += 32 * 5;
+ __asm__ __volatile__ ("mv ea, ra");
+ __asm__ __volatile__ ("b %0"::"r" (eba));
+ __builtin_unreachable ();
+ }
+
+ return __udivmodsi4 (a, b, 0);
+}
diff --git a/libgcc/config/lm32/_umodsi3.c b/libgcc/config/lm32/_umodsi3.c
new file mode 100644
index 000000000..d4af217e6
--- /dev/null
+++ b/libgcc/config/lm32/_umodsi3.c
@@ -0,0 +1,49 @@
+/* _umodsi3 for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "libgcc_lm32.h"
+
+/* Unsigned modulus. */
+
+USItype
+__umodsi3 (USItype a, USItype b)
+{
+ if (b == 0)
+ {
+ /* Raise divide by zero exception. */
+ int eba, sr;
+ /* Save interrupt enable. */
+ __asm__ __volatile__ ("rcsr %0, IE":"=r" (sr));
+ sr = (sr & 1) << 1;
+ __asm__ __volatile__ ("wcsr IE, %0"::"r" (sr));
+ /* Branch to exception handler. */
+ __asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
+ eba += 32 * 5;
+ __asm__ __volatile__ ("mv ea, ra");
+ __asm__ __volatile__ ("b %0"::"r" (eba));
+ __builtin_unreachable ();
+ }
+
+ return __udivmodsi4 (a, b, 1);
+}
diff --git a/libgcc/config/lm32/crti.S b/libgcc/config/lm32/crti.S
new file mode 100644
index 000000000..6e6455b9f
--- /dev/null
+++ b/libgcc/config/lm32/crti.S
@@ -0,0 +1,40 @@
+# crti.S for Lattice Mico32
+# Contributed by Jon Beniston <jon@beniston.com>
+#
+# Copyright (C) 2009 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+#
+
+ .section .init
+ .global _init
+ .type _init,@function
+ .align 4
+_init:
+ addi sp, sp, -4
+ sw (sp+4), ra
+
+ .section .fini
+ .global _fini
+ .type _fini,@function
+ .align 4
+_fini:
+ addi sp, sp, -4
+ sw (sp+4), ra
diff --git a/libgcc/config/lm32/crtn.S b/libgcc/config/lm32/crtn.S
new file mode 100644
index 000000000..aa6321565
--- /dev/null
+++ b/libgcc/config/lm32/crtn.S
@@ -0,0 +1,37 @@
+# crtn.S for Lattice Mico32
+# Contributed by Jon Beniston <jon@beniston.com>
+#
+# Copyright (C) 2009 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+#
+
+ .section .init
+
+ lw ra, (sp+4)
+ addi sp, sp, 4
+ ret
+
+ .section .fini
+
+ lw ra, (sp+4)
+ addi sp, sp, 4
+ ret
+
diff --git a/libgcc/config/lm32/libgcc_lm32.h b/libgcc/config/lm32/libgcc_lm32.h
new file mode 100644
index 000000000..4a9a6e675
--- /dev/null
+++ b/libgcc/config/lm32/libgcc_lm32.h
@@ -0,0 +1,43 @@
+/* Integer arithmetic support for Lattice Mico32.
+ Contributed by Jon Beniston <jon@beniston.com>
+
+ Copyright (C) 2009 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef LIBGCC_LM32_H
+#define LIBGCC_LM32_H
+
+/* Types. */
+
+typedef unsigned char UQItype __attribute__ ((mode (QI)));
+typedef long SItype __attribute__ ((mode (SI)));
+typedef unsigned long USItype __attribute__ ((mode (SI)));
+
+/* Prototypes. */
+
+USItype __mulsi3 (USItype a, USItype b);
+USItype __udivmodsi4 (USItype num, USItype den, int modwanted);
+SItype __divsi3 (SItype a, SItype b);
+SItype __modsi3 (SItype a, SItype b);
+USItype __udivsi3 (USItype a, USItype b);
+USItype __umodsi3 (USItype a, USItype b);
+
+#endif /* LIBGCC_LM32_H */
diff --git a/libgcc/config/lm32/t-elf b/libgcc/config/lm32/t-elf
new file mode 100644
index 000000000..679f00711
--- /dev/null
+++ b/libgcc/config/lm32/t-elf
@@ -0,0 +1,12 @@
+# Assemble startup files.
+
+$(T)crti.o: $(srcdir)/config/lm32/crti.S $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/lm32/crti.S
+
+$(T)crtn.o: $(srcdir)/config/lm32/crtn.S $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/lm32/crtn.S
+
+CRTSTUFF_T_CFLAGS = -G 0 -msign-extend-enabled
+HOST_LIBGCC2_CFLAGS = -G 0 -msign-extend-enabled
diff --git a/libgcc/config/lm32/t-lm32 b/libgcc/config/lm32/t-lm32
new file mode 100644
index 000000000..725e09a79
--- /dev/null
+++ b/libgcc/config/lm32/t-lm32
@@ -0,0 +1,10 @@
+LIB2ADD += \
+ $(srcdir)/config/lm32/_ashlsi3.S \
+ $(srcdir)/config/lm32/_ashrsi3.S \
+ $(srcdir)/config/lm32/_lshrsi3.S \
+ $(srcdir)/config/lm32/_mulsi3.c \
+ $(srcdir)/config/lm32/_udivmodsi4.c \
+ $(srcdir)/config/lm32/_divsi3.c \
+ $(srcdir)/config/lm32/_modsi3.c \
+ $(srcdir)/config/lm32/_udivsi3.c \
+ $(srcdir)/config/lm32/_umodsi3.c
diff --git a/libgcc/config/lm32/t-uclinux b/libgcc/config/lm32/t-uclinux
new file mode 100644
index 000000000..d388f56c3
--- /dev/null
+++ b/libgcc/config/lm32/t-uclinux
@@ -0,0 +1,2 @@
+CRTSTUFF_T_CFLAGS = -fPIC -msign-extend-enabled
+HOST_LIBGCC2_CFLAGS = -fPIC -msign-extend-enabled
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 09:38:15 +0000