1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
;; Scheduling description for IBM PowerPC 440 processor.
;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; PPC440 Embedded PowerPC controller
;; dual issue
;; i_pipe - complex integer / compare / branch
;; j_pipe - simple integer arithmetic
;; l_pipe - load-store
;; f_pipe - floating point arithmetic
(define_automaton "ppc440_core,ppc440_apu")
(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
(define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
load_l,store_c,sync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
(and (eq_attr "type" "imul2,imul3")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-idiv" 34
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe*33")
(define_insn_reservation "ppc440-branch" 1
(and (eq_attr "type" "branch,jmpreg,isync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
(and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-fpcompare" 3 ; 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
(define_insn_reservation "ppc440-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*15")
(define_insn_reservation "ppc440-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*29")
(define_insn_reservation "ppc440-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
|
