summaryrefslogtreecommitdiff
path: root/gcc/config/rs6000/603.md
blob: a042729a1daa57fe201e64beacfcdc61c3fe6acb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
;; Scheduling description for PowerPC 603 processor.
;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
;;
;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

(define_automaton "ppc603,ppc603fp")
(define_cpu_unit "iu_603" "ppc603")
(define_cpu_unit "fpu_603" "ppc603fp")
(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")

;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
;; Max issue 3 insns/clock cycle (includes 1 branch)

;; Branches go straight to the BPU.  All other insns are handled
;; by a dispatch unit which can issue a max of 2 insns per cycle.

;; The PPC603e user's manual recommends that to reduce branch mispredictions,
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them; separation by more than 9 insns ensures that the CR
;; bits will be immediately available for execution.
;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.

;; CR insns get executed in the SRU.  Not modelled.

(define_insn_reservation "ppc603-load" 2
  (and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l")
       (eq_attr "cpu" "ppc603"))
  "lsu_603")

(define_insn_reservation "ppc603-store" 2
  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
       (eq_attr "cpu" "ppc603"))
  "lsu_603*2")

(define_insn_reservation "ppc603-fpload" 2
  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
       (eq_attr "cpu" "ppc603"))
  "lsu_603")

(define_insn_reservation "ppc603-storec" 8
  (and (eq_attr "type" "store_c")
       (eq_attr "cpu" "ppc603"))
  "lsu_603")

(define_insn_reservation "ppc603-integer" 1
  (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
                        var_shift_rotate,cntlz,exts,isel")
       (eq_attr "cpu" "ppc603"))
  "iu_603")

(define_insn_reservation "ppc603-two" 1
  (and (eq_attr "type" "two")
       (eq_attr "cpu" "ppc603"))
  "iu_603,iu_603")

(define_insn_reservation "ppc603-three" 1
  (and (eq_attr "type" "three")
       (eq_attr "cpu" "ppc603"))
  "iu_603,iu_603,iu_603")

; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
  (and (eq_attr "type" "imul,imul_compare")
       (eq_attr "cpu" "ppc603"))
  "iu_603*2")

(define_insn_reservation "ppc603-imul2" 2
  (and (eq_attr "type" "imul2,imul3")
       (eq_attr "cpu" "ppc603"))
  "iu_603*2")

(define_insn_reservation "ppc603-idiv" 37
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppc603"))
  "iu_603*37")

(define_insn_reservation "ppc603-compare" 3
  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
                        var_delayed_compare")
       (eq_attr "cpu" "ppc603"))
  "iu_603,nothing,bpu_603")

(define_insn_reservation "ppc603-fpcompare" 3
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "ppc603"))
  "(fpu_603+iu_603*2),bpu_603")

(define_insn_reservation "ppc603-fp" 3
  (and (eq_attr "type" "fp")
       (eq_attr "cpu" "ppc603"))
  "fpu_603")

(define_insn_reservation "ppc603-dmul" 4
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "ppc603"))
  "fpu_603*2")

; Divides are not pipelined
(define_insn_reservation "ppc603-sdiv" 18
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppc603"))
  "fpu_603*18")

(define_insn_reservation "ppc603-ddiv" 33
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "ppc603"))
  "fpu_603*33")

(define_insn_reservation "ppc603-crlogical" 2
  (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
       (eq_attr "cpu" "ppc603"))
  "sru_603")

(define_insn_reservation "ppc603-mtjmpr" 4
  (and (eq_attr "type" "mtjmpr")
       (eq_attr "cpu" "ppc603"))
  "sru_603")

(define_insn_reservation "ppc603-mfjmpr" 2
  (and (eq_attr "type" "mfjmpr,isync,sync")
       (eq_attr "cpu" "ppc603"))
  "sru_603")

(define_insn_reservation "ppc603-jmpreg" 1
  (and (eq_attr "type" "jmpreg,branch")
       (eq_attr "cpu" "ppc603"))
  "bpu_603")