summaryrefslogtreecommitdiff
path: root/gcc/config/rx/predicates.md
blob: 82cac42dadfbc57ea26b69d938c758d4ca9bf301 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
;; Predicate definitions for Renesas RX.
;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
;; Contributed by Red Hat.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.



;; Check that the operand is suitable for a call insn.
;; Only registers and symbol refs are allowed.

(define_predicate "rx_call_operand"
  (match_code "symbol_ref,reg")
)

;; For sibcall operations we can only use a symbolic address.

(define_predicate "rx_symbolic_call_operand"
  (match_code "symbol_ref")
)

;; Check that the operand is suitable for a shift insn
;; Only small integers or a value in a register are permitted.

(define_predicate "rx_shift_operand"
  (ior (match_operand 0 "register_operand")
       (and (match_code "const_int")
	    (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
)

(define_predicate "rx_constshift_operand"
  (and (match_code "const_int")
       (match_test "IN_RANGE (INTVAL (op), 0, 31)"))
)

(define_predicate "rx_restricted_mem_operand"
  (and (match_code "mem")
       (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)"))
)

;; Check that the operand is suitable as the source operand
;; for a logic or arithmeitc instruction.  Registers, integers
;; and a restricted subset of memory addresses are allowed.

(define_predicate "rx_source_operand"
  (ior (match_operand 0 "register_operand")
       (match_operand 0 "immediate_operand")
       (match_operand 0 "rx_restricted_mem_operand"))
)

;; Check that the operand is suitable as the source operand
;; for a comparison instruction.  This is the same as
;; rx_source_operand except that SUBREGs are allowed but
;; CONST_INTs are not.

(define_predicate "rx_compare_operand"
  (ior (match_operand 0 "register_operand")
       (match_operand 0 "rx_restricted_mem_operand"))
)

;; Return true if OP is a store multiple operation.  This looks like:
;;
;;   [(set (SP) (MINUS (SP) (INT)))
;;    (set (MEM (SP)) (REG))
;;    (set (MEM (MINUS (SP) (INT))) (REG)) {optionally repeated}
;;   ]

(define_special_predicate "rx_store_multiple_vector"
  (match_code "parallel")
{
  int count = XVECLEN (op, 0);
  unsigned int src_regno;
  rtx element;
  int i;

  /* Perform a quick check so we don't blow up below.  */
  if (count <= 2)
    return false;

  /* Check that the first element of the vector is the stack adjust.  */
  element = XVECEXP (op, 0, 0);
  if (   ! SET_P (element)
      || ! REG_P (SET_DEST (element))
      ||   REGNO (SET_DEST (element)) != SP_REG
      ||   GET_CODE (SET_SRC (element)) != MINUS
      || ! REG_P (XEXP (SET_SRC (element), 0))
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
    return false;
	 
  /* Check that the next element is the first push.  */
  element = XVECEXP (op, 0, 1);
  if (   ! SET_P (element)
      || ! REG_P (SET_SRC (element))
      || GET_MODE (SET_SRC (element)) != SImode
      || ! MEM_P (SET_DEST (element))
      || GET_MODE (SET_DEST (element)) != SImode
      || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
      || ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
      ||   REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
      || ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
      || INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
        != GET_MODE_SIZE (SImode))
    return false;

  src_regno = REGNO (SET_SRC (element));

  /* Check that the remaining elements use SP-<disp>
     addressing and decreasing register numbers.  */
  for (i = 2; i < count; i++)
    {
      element = XVECEXP (op, 0, i);

      if (   ! SET_P (element)
	  || ! REG_P (SET_SRC (element))
	  || GET_MODE (SET_SRC (element)) != SImode
	  || REGNO (SET_SRC (element)) != src_regno - (i - 1)
	  || ! MEM_P (SET_DEST (element))
	  || GET_MODE (SET_DEST (element)) != SImode
	  || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
          || ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
          ||   REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
	  || ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
	  || INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
	     != i * GET_MODE_SIZE (SImode))
	return false;
    }
  return true;
})

;; Return true if OP is a load multiple operation.
;; This looks like:
;;  [(set (SP) (PLUS (SP) (INT)))
;;   (set (REG) (MEM (SP)))
;;   (set (REG) (MEM (PLUS (SP) (INT)))) {optionally repeated}
;;  ]

(define_special_predicate "rx_load_multiple_vector"
  (match_code "parallel")
{
  int count = XVECLEN (op, 0);
  unsigned int dest_regno;
  rtx element;
  int i;

  /* Perform a quick check so we don't blow up below.  */
  if (count <= 2)
    return false;

  /* Check that the first element of the vector is the stack adjust.  */
  element = XVECEXP (op, 0, 0);
  if (   ! SET_P (element)
      || ! REG_P (SET_DEST (element))
      ||   REGNO (SET_DEST (element)) != SP_REG
      ||   GET_CODE (SET_SRC (element)) != PLUS
      || ! REG_P (XEXP (SET_SRC (element), 0))
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
    return false;
	 
  /* Check that the next element is the first push.  */
  element = XVECEXP (op, 0, 1);
  if (   ! SET_P (element)
      || ! REG_P (SET_DEST (element))
      || ! MEM_P (SET_SRC (element))
      || ! REG_P (XEXP (SET_SRC (element), 0))
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
    return false;

  dest_regno = REGNO (SET_DEST (element));

  /* Check that the remaining elements use SP+<disp>
     addressing and incremental register numbers.  */
  for (i = 2; i < count; i++)
    {
      element = XVECEXP (op, 0, i);

      if (   ! SET_P (element)
	  || ! REG_P (SET_DEST (element))
	  || GET_MODE (SET_DEST (element)) != SImode
	  || REGNO (SET_DEST (element)) != dest_regno + (i - 1)
	  || ! MEM_P (SET_SRC (element))
	  || GET_MODE (SET_SRC (element)) != SImode
	  || GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
          || ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
          ||   REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
	  || ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
	  || INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
	     != (i - 1) * GET_MODE_SIZE (SImode))
	return false;
    }
  return true;
})

;; Return true if OP is a pop-and-return load multiple operation.
;; This looks like:
;;  [(set (SP) (PLUS (SP) (INT)))
;;   (set (REG) (MEM (SP)))
;;   (set (REG) (MEM (PLUS (SP) (INT)))) {optional and possibly repeated}
;;   (return)
;;  ]

(define_special_predicate "rx_rtsd_vector"
  (match_code "parallel")
{
  int count = XVECLEN (op, 0);
  unsigned int dest_regno;
  rtx element;
  int i;

  /* Perform a quick check so we don't blow up below.  */
  if (count <= 2)
    return false;

  /* Check that the first element of the vector is the stack adjust.  */
  element = XVECEXP (op, 0, 0);
  if (   ! SET_P (element)
      || ! REG_P (SET_DEST (element))
      ||   REGNO (SET_DEST (element)) != SP_REG
      ||   GET_CODE (SET_SRC (element)) != PLUS
      || ! REG_P (XEXP (SET_SRC (element), 0))
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
    return false;
	 
  /* Check that the next element is the first push.  */
  element = XVECEXP (op, 0, 1);
  if (   ! SET_P (element)
      || ! REG_P (SET_DEST (element))
      || ! MEM_P (SET_SRC (element))
      || ! REG_P (XEXP (SET_SRC (element), 0))
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
    return false;

  dest_regno = REGNO (SET_DEST (element));

  /* Check that the remaining elements, if any, and except
     for the last one, use SP+<disp> addressing and incremental
     register numbers.  */
  for (i = 2; i < count - 1; i++)
    {
      element = XVECEXP (op, 0, i);

      if (   ! SET_P (element)
	  || ! REG_P (SET_DEST (element))
	  || GET_MODE (SET_DEST (element)) != SImode
	  || REGNO (SET_DEST (element)) != dest_regno + (i - 1)
	  || ! MEM_P (SET_SRC (element))
	  || GET_MODE (SET_SRC (element)) != SImode
	  || GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
          || ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
          ||   REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
	  || ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
	  || INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
	     != (i - 1) * GET_MODE_SIZE (SImode))
	return false;
    }

  /* The last element must be a RETURN.  */    
  element = XVECEXP (op, 0, count - 1);
  return GET_CODE (element) == RETURN;
})

(define_predicate "label_ref_operand"
  (match_code "label_ref")
)

(define_predicate "rx_z_comparison_operator"
  (match_code "eq,ne")
)

(define_predicate "rx_zs_comparison_operator"
  (match_code "eq,ne")
)

;; GT and LE omitted due to operand swap required.
(define_predicate "rx_fp_comparison_operator"
  (match_code "eq,ne,lt,ge,ordered,unordered")
)

(define_predicate "rshift_operator"
  (match_code "ashiftrt,lshiftrt")
)