added riscv target-specific (code generation) definitions.

5 files changed, 39 insertions, 0 deletions

diff --git a/project/codegen.mk b/project/codegen.mk
index 35bed11..1fc71bf 100644
--- a/project/codegen.mk
+++ b/project/codegen.mk
@@ -15,18 +15,21 @@ clean-gen:
 		rm -f $(GEN_BE_DIR_IA32)/emitter.tag
 		rm -f $(GEN_BE_DIR_MIPS)/emitter.tag
 		rm -f $(GEN_BE_DIR_SPARC)/emitter.tag
+		rm -f $(GEN_BE_DIR_RISCV)/emitter.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/emitter.tag
 		rm -f $(GEN_BE_DIR_ARM)/opcodes.tag
 		rm -f $(GEN_BE_DIR_AMD64)/opcodes.tag
 		rm -f $(GEN_BE_DIR_IA32)/opcodes.tag
 		rm -f $(GEN_BE_DIR_MIPS)/opcodes.tag
 		rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag
+		rm -f $(GEN_BE_DIR_RISCV)/opcodes.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag
 		rm -f $(GEN_BE_DIR_ARM)/regalloc.tag
 		rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag
 		rm -f $(GEN_BE_DIR_IA32)/regalloc.tag
 		rm -f $(GEN_BE_DIR_MIPS)/regalloc.tag
 		rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag
+		rm -f $(GEN_BE_DIR_RISCV)/regalloc.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag
 
 GEN_ALL 	= $(GEN_IR_SRCS) \
@@ -45,6 +48,7 @@ GEN_BE_DIR_AMD64	= build/gen/ir/be/amd64
 GEN_BE_DIR_IA32		= build/gen/ir/be/ia32
 GEN_BE_DIR_MIPS		= build/gen/ir/be/mips
 GEN_BE_DIR_SPARC	= build/gen/ir/be/sparc
+GEN_BE_DIR_RISCV	= build/gen/ir/be/riscv
 GEN_BE_DIR_TEMPLATE	= build/gen/ir/be/TEMPLATE
 
 GEN_SPEC_ARM		= $(SOURCE_DIR)/ir/be/arm/arm_spec.pl
@@ -52,6 +56,7 @@ GEN_SPEC_AMD64		= $(SOURCE_DIR)/ir/be/amd64/amd64_spec.pl
 GEN_SPEC_IA32		= $(SOURCE_DIR)/ir/be/ia32/ia32_spec.pl
 GEN_SPEC_MIPS		= $(SOURCE_DIR)/ir/be/mips/mips_spec.pl
 GEN_SPEC_SPARC		= $(SOURCE_DIR)/ir/be/sparc/sparc_spec.pl
+GEN_SPEC_RISCV		= $(SOURCE_DIR)/ir/be/riscv/riscv_spec.pl
 GEN_SPEC_TEMPLATE	= $(SOURCE_DIR)/ir/be/TEMPLATE/TEMPLATE_spec.pl
 
 
@@ -105,6 +110,11 @@ $(GEN_BE_DIR_SPARC)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) tree.tag
 	touch $@
 
 
+$(GEN_BE_DIR_RISCV)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_RISCV) tree.tag
+	$(GEN_EMITTER_TOOL) $(GEN_SPEC_RISCV) $(GEN_BE_DIR_RISCV)
+	touch $@
+
+
 $(GEN_BE_DIR_TEMPLATE)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
 	$(GEN_EMITTER_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
 	touch $@
@@ -126,6 +136,9 @@ $(GEN_BE_DIR_MIPS)/gen_mips_emitter.h:		$(GEN_BE_DIR_MIPS)/emitter.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.c:	$(GEN_BE_DIR_SPARC)/emitter.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.h:	$(GEN_BE_DIR_SPARC)/emitter.tag
 
+$(GEN_BE_DIR_RISCV)/gen_riscv_emitter.c:	$(GEN_BE_DIR_RISCV)/emitter.tag
+$(GEN_BE_DIR_RISCV)/gen_riscv_emitter.h:	$(GEN_BE_DIR_RISCV)/emitter.tag
+
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.c:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_emitter.h:	$(GEN_BE_DIR_TEMPLATE)/emitter.tag
 
@@ -160,6 +173,11 @@ $(GEN_BE_DIR_SPARC)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) tree.tag
 	touch $@
 
 
+$(GEN_BE_DIR_RISCV)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_RISCV) tree.tag
+	$(GEN_OPCODES_TOOL) $(GEN_SPEC_RISCV) $(GEN_BE_DIR_RISCV)
+	touch $@
+
+
 $(GEN_BE_DIR_TEMPLATE)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
 	$(GEN_OPCODES_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
 	touch $@
@@ -181,6 +199,9 @@ $(GEN_BE_DIR_MIPS)/gen_mips_new_nodes.h:	$(GEN_BE_DIR_MIPS)/opcodes.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.c:	$(GEN_BE_DIR_SPARC)/opcodes.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.h:	$(GEN_BE_DIR_SPARC)/opcodes.tag
 
+$(GEN_BE_DIR_RISCV)/gen_riscv_new_nodes.c:	$(GEN_BE_DIR_RISCV)/opcodes.tag
+$(GEN_BE_DIR_RISCV)/gen_riscv_new_nodes.h:	$(GEN_BE_DIR_RISCV)/opcodes.tag
+
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.c:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.h:	$(GEN_BE_DIR_TEMPLATE)/opcodes.tag
 
@@ -215,6 +236,11 @@ $(GEN_BE_DIR_SPARC)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) tree.ta
 	touch $@
 
 
+$(GEN_BE_DIR_RISCV)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_RISCV) tree.tag
+	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_RISCV) $(GEN_BE_DIR_RISCV)
+	touch $@
+
+
 $(GEN_BE_DIR_TEMPLATE)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) tree.tag
 	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE)
 	touch $@
@@ -236,6 +262,9 @@ $(GEN_BE_DIR_MIPS)/gen_mips_regalloc_if.h:	$(GEN_BE_DIR_MIPS)/regalloc.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c:	$(GEN_BE_DIR_SPARC)/regalloc.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h:	$(GEN_BE_DIR_SPARC)/regalloc.tag
 
+$(GEN_BE_DIR_RISCV)/gen_riscv_regalloc_if.c:	$(GEN_BE_DIR_RISCV)/regalloc.tag
+$(GEN_BE_DIR_RISCV)/gen_riscv_regalloc_if.h:	$(GEN_BE_DIR_RISCV)/regalloc.tag
+
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.c:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
 $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.h:	$(GEN_BE_DIR_TEMPLATE)/regalloc.tag
 
diff --git a/project/common.mk b/project/common.mk
index fda2ae7..ffbf88d 100644
--- a/project/common.mk
+++ b/project/common.mk
@@ -20,6 +20,7 @@ GEN_EMITTER_SRCS = \
 	build/gen/ir/be/ia32/gen_ia32_emitter.c \
 	build/gen/ir/be/mips/gen_mips_emitter.c \
 	build/gen/ir/be/sparc/gen_sparc_emitter.c \
+	build/gen/ir/be/riscv/gen_riscv_emitter.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.c \
 
 GEN_OPCODES_SRCS = \
@@ -28,6 +29,7 @@ GEN_OPCODES_SRCS = \
 	build/gen/ir/be/ia32/gen_ia32_new_nodes.c \
 	build/gen/ir/be/mips/gen_mips_new_nodes.c \
 	build/gen/ir/be/sparc/gen_sparc_new_nodes.c \
+	build/gen/ir/be/riscv/gen_riscv_new_nodes.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \
 
 GEN_REGALLOC_SRCS = \
@@ -36,6 +38,7 @@ GEN_REGALLOC_SRCS = \
 	build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \
 	build/gen/ir/be/mips/gen_mips_regalloc_if.c \
 	build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \
+	build/gen/ir/be/riscv/gen_riscv_regalloc_if.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \
 
 
diff --git a/project/extras.mk b/project/extras.mk
index ea7d110..e292314 100644
--- a/project/extras.mk
+++ b/project/extras.mk
@@ -33,6 +33,7 @@ CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/amd64
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/ia32
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/mips
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/sparc
+CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/riscv
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/TEMPLATE
 
 CFLAGS_COMMON += -Ibuild/gen/ir/be/arm
@@ -40,6 +41,7 @@ CFLAGS_COMMON += -Ibuild/gen/ir/be/amd64
 CFLAGS_COMMON += -Ibuild/gen/ir/be/ia32
 CFLAGS_COMMON += -Ibuild/gen/ir/be/mips
 CFLAGS_COMMON += -Ibuild/gen/ir/be/sparc
+CFLAGS_COMMON += -Ibuild/gen/ir/be/riscv
 CFLAGS_COMMON += -Ibuild/gen/ir/be/TEMPLATE
 
 install-headers-custom:
diff --git a/project/headers.mk b/project/headers.mk
index 6c11dea..5cb1061 100644
--- a/project/headers.mk
+++ b/project/headers.mk
@@ -9,6 +9,7 @@ GEN_EMITTER_HEADERS = \
 	build/gen/ir/be/ia32/gen_ia32_emitter.h \
 	build/gen/ir/be/mips/gen_mips_emitter.h \
 	build/gen/ir/be/sparc/gen_sparc_emitter.h \
+	build/gen/ir/be/riscv/gen_riscv_emitter.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.h \
 
 GEN_OPCODES_HEADERS = \
@@ -17,6 +18,7 @@ GEN_OPCODES_HEADERS = \
 	build/gen/ir/be/ia32/gen_ia32_new_nodes.h \
 	build/gen/ir/be/mips/gen_mips_new_nodes.h \
 	build/gen/ir/be/sparc/gen_sparc_new_nodes.h \
+	build/gen/ir/be/riscv/gen_riscv_new_nodes.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.h \
 
 GEN_REGALLOC_HEADERS = \
@@ -25,6 +27,7 @@ GEN_REGALLOC_HEADERS = \
 	build/gen/ir/be/ia32/gen_ia32_regalloc_if.h \
 	build/gen/ir/be/mips/gen_mips_regalloc_if.h \
 	build/gen/ir/be/sparc/gen_sparc_regalloc_if.h \
+	build/gen/ir/be/riscv/gen_riscv_regalloc_if.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.h \
 
 
diff --git a/project/tree.mk b/project/tree.mk
index 330c875..bb279fb 100644
--- a/project/tree.mk
+++ b/project/tree.mk
@@ -11,12 +11,14 @@ tree.tag:
 		mkdir -p build/gen/ir/be/ia32
 		mkdir -p build/gen/ir/be/mips
 		mkdir -p build/gen/ir/be/sparc
+		mkdir -p build/gen/ir/be/riscv
 		mkdir -p build/gen/ir/be/TEMPLATE
 		mkdir -p ir/be/arm
 		mkdir -p ir/be/amd64
 		mkdir -p ir/be/ia32
 		mkdir -p ir/be/mips
 		mkdir -p ir/be/sparc
+		mkdir -p ir/be/riscv
 		mkdir -p ir/be/TEMPLATE
 		mkdir -p ir/adt
 		mkdir -p ir/ana