diff options
author | midipix <writeonce@midipix.org> | 2016-11-01 22:53:38 -0400 |
---|---|---|
committer | midipix <writeonce@midipix.org> | 2016-11-01 22:56:37 -0400 |
commit | 9b9d84f3dee31626118ac4d779f6c6d23bf7bb26 (patch) | |
tree | 17465f8ac64160010354db981171f991814de7a8 /project | |
parent | e685cdb96e478470912f03c85e5c1ba7aa8bae45 (diff) | |
download | bfirm-9b9d84f3dee31626118ac4d779f6c6d23bf7bb26.tar.bz2 bfirm-9b9d84f3dee31626118ac4d779f6c6d23bf7bb26.tar.xz |
build system: code generation: added the gen-regalloc build target.
Diffstat (limited to 'project')
-rw-r--r-- | project/codegen.mk | 62 | ||||
-rw-r--r-- | project/common.mk | 7 | ||||
-rw-r--r-- | project/headers.mk | 7 |
3 files changed, 74 insertions, 2 deletions
diff --git a/project/codegen.mk b/project/codegen.mk index ee8dfa8..72d6000 100644 --- a/project/codegen.mk +++ b/project/codegen.mk @@ -8,6 +8,8 @@ clean-gen: rm -f $(GEN_EMITTER_HEADERS) rm -f $(GEN_OPCODES_SRCS) rm -f $(GEN_OPCODES_HEADERS) + rm -f $(GEN_REGALLOC_SRCS) + rm -f $(GEN_REGALLOC_HEADERS) rm -f $(GEN_BE_DIR_ARM)/emitter.tag rm -f $(GEN_BE_DIR_AMD64)/emitter.tag rm -f $(GEN_BE_DIR_IA32)/emitter.tag @@ -18,6 +20,11 @@ clean-gen: rm -f $(GEN_BE_DIR_IA32)/opcodes.tag rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag + rm -f $(GEN_BE_DIR_ARM)/regalloc.tag + rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag + rm -f $(GEN_BE_DIR_IA32)/regalloc.tag + rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag + rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag GEN_ALL = $(GEN_IR_SRCS) \ $(GEN_IR_HEADERS) \ @@ -25,6 +32,8 @@ GEN_ALL = $(GEN_IR_SRCS) \ $(GEN_EMITTER_HEADERS) \ $(GEN_OPCODES_SRCS) \ $(GEN_OPCODES_HEADERS) \ + $(GEN_REGALLOC_SRCS) \ + $(GEN_REGALLOC_HEADERS) \ # build/gen/ir/be @@ -156,6 +165,53 @@ $(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_new_nodes.h: $(GEN_BE_DIR_TEMPLATE)/opcodes. +# gen-regalloc +GEN_REGALLOC_TOOL = $(SOURCE_DIR)/ir/be/scripts/generate_regalloc_if.pl + + +$(GEN_BE_DIR_ARM)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) + $(GEN_REGALLOC_TOOL) $(GEN_SPEC_ARM) $(GEN_BE_DIR_ARM) + touch $@ + + +$(GEN_BE_DIR_AMD64)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) + $(GEN_REGALLOC_TOOL) $(GEN_SPEC_AMD64) $(GEN_BE_DIR_AMD64) + touch $@ + + +$(GEN_BE_DIR_IA32)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) + $(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) $(GEN_BE_DIR_IA32) + touch $@ + + +$(GEN_BE_DIR_SPARC)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) + $(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC) + touch $@ + + +$(GEN_BE_DIR_TEMPLATE)/regalloc.tag: $(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) + $(GEN_REGALLOC_TOOL) $(GEN_SPEC_TEMPLATE) $(GEN_BE_DIR_TEMPLATE) + touch $@ + + + +$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.c: $(GEN_BE_DIR_ARM)/regalloc.tag +$(GEN_BE_DIR_ARM)/gen_arm_regalloc_if.h: $(GEN_BE_DIR_ARM)/regalloc.tag + +$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.c: $(GEN_BE_DIR_AMD64)/regalloc.tag +$(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.h: $(GEN_BE_DIR_AMD64)/regalloc.tag + +$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.c: $(GEN_BE_DIR_IA32)/regalloc.tag +$(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.h: $(GEN_BE_DIR_IA32)/regalloc.tag + +$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c: $(GEN_BE_DIR_SPARC)/regalloc.tag +$(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h: $(GEN_BE_DIR_SPARC)/regalloc.tag + +$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.c: $(GEN_BE_DIR_TEMPLATE)/regalloc.tag +$(GEN_BE_DIR_TEMPLATE)/gen_TEMPLATE_regalloc_if.h: $(GEN_BE_DIR_TEMPLATE)/regalloc.tag + + + # gen-all gen-ir: $(GEN_IR_SRCS) $(GEN_IR_HEADERS) @@ -163,7 +219,9 @@ gen-emitter: $(GEN_EMITTER_SRCS) $(GEN_EMITTER_HEADERS) gen-opcodes: $(GEN_OPCODES_SRCS) $(GEN_OPCODES_HEADERS) -gen-all: gen-ir gen-emitter gen-opcodes +gen-regalloc: $(GEN_REGALLOC_SRCS) $(GEN_REGALLOC_HEADERS) + +gen-all: gen-ir gen-emitter gen-opcodes gen-regalloc gen.tag: $(GEN_ALL) touch gen.tag @@ -173,4 +231,4 @@ gen: gen.tag .PHONY: clean-gen \ gen gen-all \ - gen-ir gen-emitter gen-opcodes + gen-ir gen-emitter gen-opcodes gen-regalloc diff --git a/project/common.mk b/project/common.mk index a964d23..24b24c3 100644 --- a/project/common.mk +++ b/project/common.mk @@ -15,3 +15,10 @@ GEN_OPCODES_SRCS = \ build/gen/ir/be/ia32/gen_ia32_new_nodes.c \ build/gen/ir/be/sparc/gen_sparc_new_nodes.c \ build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \ + +GEN_REGALLOC_SRCS = \ + build/gen/ir/be/arm/gen_arm_regalloc_if.c \ + build/gen/ir/be/amd64/gen_amd64_regalloc_if.c \ + build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \ + build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \ + build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \ diff --git a/project/headers.mk b/project/headers.mk index 8d770cb..4caca62 100644 --- a/project/headers.mk +++ b/project/headers.mk @@ -16,3 +16,10 @@ GEN_OPCODES_HEADERS = \ build/gen/ir/be/ia32/gen_ia32_new_nodes.h \ build/gen/ir/be/sparc/gen_sparc_new_nodes.h \ build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.h \ + +GEN_REGALLOC_HEADERS = \ + build/gen/ir/be/arm/gen_arm_regalloc_if.h \ + build/gen/ir/be/amd64/gen_amd64_regalloc_if.h \ + build/gen/ir/be/ia32/gen_ia32_regalloc_if.h \ + build/gen/ir/be/sparc/gen_sparc_regalloc_if.h \ + build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.h \ |