project: added MIPS target definitions.

5 files changed, 39 insertions, 0 deletions

diff --git a/project/codegen.mk b/project/codegen.mk
index 19c6ebe..35bed11 100644
--- a/project/codegen.mk
+++ b/project/codegen.mk
@@ -13,16 +13,19 @@ clean-gen:
 		rm -f $(GEN_BE_DIR_ARM)/emitter.tag
 		rm -f $(GEN_BE_DIR_AMD64)/emitter.tag
 		rm -f $(GEN_BE_DIR_IA32)/emitter.tag
+		rm -f $(GEN_BE_DIR_MIPS)/emitter.tag
 		rm -f $(GEN_BE_DIR_SPARC)/emitter.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/emitter.tag
 		rm -f $(GEN_BE_DIR_ARM)/opcodes.tag
 		rm -f $(GEN_BE_DIR_AMD64)/opcodes.tag
 		rm -f $(GEN_BE_DIR_IA32)/opcodes.tag
+		rm -f $(GEN_BE_DIR_MIPS)/opcodes.tag
 		rm -f $(GEN_BE_DIR_SPARC)/opcodes.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/opcodes.tag
 		rm -f $(GEN_BE_DIR_ARM)/regalloc.tag
 		rm -f $(GEN_BE_DIR_AMD64)/regalloc.tag
 		rm -f $(GEN_BE_DIR_IA32)/regalloc.tag
+		rm -f $(GEN_BE_DIR_MIPS)/regalloc.tag
 		rm -f $(GEN_BE_DIR_SPARC)/regalloc.tag
 		rm -f $(GEN_BE_DIR_TEMPLATE)/regalloc.tag
 
@@ -40,12 +43,14 @@ GEN_ALL 	= $(GEN_IR_SRCS) \
 GEN_BE_DIR_ARM		= build/gen/ir/be/arm
 GEN_BE_DIR_AMD64	= build/gen/ir/be/amd64
 GEN_BE_DIR_IA32		= build/gen/ir/be/ia32
+GEN_BE_DIR_MIPS		= build/gen/ir/be/mips
 GEN_BE_DIR_SPARC	= build/gen/ir/be/sparc
 GEN_BE_DIR_TEMPLATE	= build/gen/ir/be/TEMPLATE
 
 GEN_SPEC_ARM		= $(SOURCE_DIR)/ir/be/arm/arm_spec.pl
 GEN_SPEC_AMD64		= $(SOURCE_DIR)/ir/be/amd64/amd64_spec.pl
 GEN_SPEC_IA32		= $(SOURCE_DIR)/ir/be/ia32/ia32_spec.pl
+GEN_SPEC_MIPS		= $(SOURCE_DIR)/ir/be/mips/mips_spec.pl
 GEN_SPEC_SPARC		= $(SOURCE_DIR)/ir/be/sparc/sparc_spec.pl
 GEN_SPEC_TEMPLATE	= $(SOURCE_DIR)/ir/be/TEMPLATE/TEMPLATE_spec.pl
 
@@ -90,6 +95,11 @@ $(GEN_BE_DIR_IA32)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_IA32) tree.tag
 	touch $@
 
 
+$(GEN_BE_DIR_MIPS)/emitter.tag:		$(GEN_EMITTER_TOOL) $(GEN_SPEC_MIPS) tree.tag
+	$(GEN_EMITTER_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
+	touch $@
+
+
 $(GEN_BE_DIR_SPARC)/emitter.tag:	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) tree.tag
 	$(GEN_EMITTER_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
 	touch $@
@@ -110,6 +120,9 @@ $(GEN_BE_DIR_AMD64)/gen_amd64_emitter.h:	$(GEN_BE_DIR_AMD64)/emitter.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_emitter.c:		$(GEN_BE_DIR_IA32)/emitter.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_emitter.h:		$(GEN_BE_DIR_IA32)/emitter.tag
 
+$(GEN_BE_DIR_MIPS)/gen_mips_emitter.c:		$(GEN_BE_DIR_MIPS)/emitter.tag
+$(GEN_BE_DIR_MIPS)/gen_mips_emitter.h:		$(GEN_BE_DIR_MIPS)/emitter.tag
+
 $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.c:	$(GEN_BE_DIR_SPARC)/emitter.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_emitter.h:	$(GEN_BE_DIR_SPARC)/emitter.tag
 
@@ -137,6 +150,11 @@ $(GEN_BE_DIR_IA32)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_IA32) tree.tag
 	touch $@
 
 
+$(GEN_BE_DIR_MIPS)/opcodes.tag:		$(GEN_OPCODES_TOOL) $(GEN_SPEC_MIPS) tree.tag
+	$(GEN_OPCODES_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
+	touch $@
+
+
 $(GEN_BE_DIR_SPARC)/opcodes.tag:	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) tree.tag
 	$(GEN_OPCODES_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
 	touch $@
@@ -157,6 +175,9 @@ $(GEN_BE_DIR_AMD64)/gen_amd64_new_nodes.h:	$(GEN_BE_DIR_AMD64)/opcodes.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.c:	$(GEN_BE_DIR_IA32)/opcodes.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_new_nodes.h:	$(GEN_BE_DIR_IA32)/opcodes.tag
 
+$(GEN_BE_DIR_MIPS)/gen_mips_new_nodes.c:	$(GEN_BE_DIR_MIPS)/opcodes.tag
+$(GEN_BE_DIR_MIPS)/gen_mips_new_nodes.h:	$(GEN_BE_DIR_MIPS)/opcodes.tag
+
 $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.c:	$(GEN_BE_DIR_SPARC)/opcodes.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_new_nodes.h:	$(GEN_BE_DIR_SPARC)/opcodes.tag
 
@@ -184,6 +205,11 @@ $(GEN_BE_DIR_IA32)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_IA32) tree.tag
 	touch $@
 
 
+$(GEN_BE_DIR_MIPS)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_MIPS) tree.tag
+	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_MIPS) $(GEN_BE_DIR_MIPS)
+	touch $@
+
+
 $(GEN_BE_DIR_SPARC)/regalloc.tag:	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) tree.tag
 	$(GEN_REGALLOC_TOOL) $(GEN_SPEC_SPARC) $(GEN_BE_DIR_SPARC)
 	touch $@
@@ -204,6 +230,9 @@ $(GEN_BE_DIR_AMD64)/gen_amd64_regalloc_if.h:	$(GEN_BE_DIR_AMD64)/regalloc.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.c:	$(GEN_BE_DIR_IA32)/regalloc.tag
 $(GEN_BE_DIR_IA32)/gen_ia32_regalloc_if.h:	$(GEN_BE_DIR_IA32)/regalloc.tag
 
+$(GEN_BE_DIR_MIPS)/gen_mips_regalloc_if.c:	$(GEN_BE_DIR_MIPS)/regalloc.tag
+$(GEN_BE_DIR_MIPS)/gen_mips_regalloc_if.h:	$(GEN_BE_DIR_MIPS)/regalloc.tag
+
 $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.c:	$(GEN_BE_DIR_SPARC)/regalloc.tag
 $(GEN_BE_DIR_SPARC)/gen_sparc_regalloc_if.h:	$(GEN_BE_DIR_SPARC)/regalloc.tag
 
diff --git a/project/common.mk b/project/common.mk
index bb68f90..fda2ae7 100644
--- a/project/common.mk
+++ b/project/common.mk
@@ -18,6 +18,7 @@ GEN_EMITTER_SRCS = \
 	build/gen/ir/be/arm/gen_arm_emitter.c \
 	build/gen/ir/be/amd64/gen_amd64_emitter.c \
 	build/gen/ir/be/ia32/gen_ia32_emitter.c \
+	build/gen/ir/be/mips/gen_mips_emitter.c \
 	build/gen/ir/be/sparc/gen_sparc_emitter.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.c \
 
@@ -25,6 +26,7 @@ GEN_OPCODES_SRCS = \
 	build/gen/ir/be/arm/gen_arm_new_nodes.c \
 	build/gen/ir/be/amd64/gen_amd64_new_nodes.c \
 	build/gen/ir/be/ia32/gen_ia32_new_nodes.c \
+	build/gen/ir/be/mips/gen_mips_new_nodes.c \
 	build/gen/ir/be/sparc/gen_sparc_new_nodes.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \
 
@@ -32,6 +34,7 @@ GEN_REGALLOC_SRCS = \
 	build/gen/ir/be/arm/gen_arm_regalloc_if.c \
 	build/gen/ir/be/amd64/gen_amd64_regalloc_if.c \
 	build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \
+	build/gen/ir/be/mips/gen_mips_regalloc_if.c \
 	build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \
 
diff --git a/project/extras.mk b/project/extras.mk
index 6004f95..ea7d110 100644
--- a/project/extras.mk
+++ b/project/extras.mk
@@ -31,12 +31,14 @@ CFLAGS_COMMON += -Ibuild/gen/ir/ir
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/arm
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/amd64
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/ia32
+CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/mips
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/sparc
 CFLAGS_COMMON += -I$(SOURCE_DIR)/ir/be/TEMPLATE
 
 CFLAGS_COMMON += -Ibuild/gen/ir/be/arm
 CFLAGS_COMMON += -Ibuild/gen/ir/be/amd64
 CFLAGS_COMMON += -Ibuild/gen/ir/be/ia32
+CFLAGS_COMMON += -Ibuild/gen/ir/be/mips
 CFLAGS_COMMON += -Ibuild/gen/ir/be/sparc
 CFLAGS_COMMON += -Ibuild/gen/ir/be/TEMPLATE
 
diff --git a/project/headers.mk b/project/headers.mk
index ac03934..6c11dea 100644
--- a/project/headers.mk
+++ b/project/headers.mk
@@ -7,6 +7,7 @@ GEN_EMITTER_HEADERS = \
 	build/gen/ir/be/arm/gen_arm_emitter.h \
 	build/gen/ir/be/amd64/gen_amd64_emitter.h \
 	build/gen/ir/be/ia32/gen_ia32_emitter.h \
+	build/gen/ir/be/mips/gen_mips_emitter.h \
 	build/gen/ir/be/sparc/gen_sparc_emitter.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.h \
 
@@ -14,6 +15,7 @@ GEN_OPCODES_HEADERS = \
 	build/gen/ir/be/arm/gen_arm_new_nodes.h \
 	build/gen/ir/be/amd64/gen_amd64_new_nodes.h \
 	build/gen/ir/be/ia32/gen_ia32_new_nodes.h \
+	build/gen/ir/be/mips/gen_mips_new_nodes.h \
 	build/gen/ir/be/sparc/gen_sparc_new_nodes.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.h \
 
@@ -21,6 +23,7 @@ GEN_REGALLOC_HEADERS = \
 	build/gen/ir/be/arm/gen_arm_regalloc_if.h \
 	build/gen/ir/be/amd64/gen_amd64_regalloc_if.h \
 	build/gen/ir/be/ia32/gen_ia32_regalloc_if.h \
+	build/gen/ir/be/mips/gen_mips_regalloc_if.h \
 	build/gen/ir/be/sparc/gen_sparc_regalloc_if.h \
 	build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.h \
 
diff --git a/project/tree.mk b/project/tree.mk
index 775ae53..330c875 100644
--- a/project/tree.mk
+++ b/project/tree.mk
@@ -9,11 +9,13 @@ tree.tag:
 		mkdir -p build/gen/ir/be/arm
 		mkdir -p build/gen/ir/be/amd64
 		mkdir -p build/gen/ir/be/ia32
+		mkdir -p build/gen/ir/be/mips
 		mkdir -p build/gen/ir/be/sparc
 		mkdir -p build/gen/ir/be/TEMPLATE
 		mkdir -p ir/be/arm
 		mkdir -p ir/be/amd64
 		mkdir -p ir/be/ia32
+		mkdir -p ir/be/mips
 		mkdir -p ir/be/sparc
 		mkdir -p ir/be/TEMPLATE
 		mkdir -p ir/adt