obtained gcc-4.6.4.tar.bz2 from upstream website;upstream

verified gcc-4.6.4.tar.bz2.sig;
imported gcc-4.6.4 source tree from verified upstream tarball.

downloading a git-generated archive based on the 'upstream' tag
should provide you with a source tree that is binary identical
to the one extracted from the above tarball.

if you have obtained the source via the command 'git clone',
however, do note that line-endings of files in your working
directory might differ from line-endings of the respective
files in the upstream repository.

24 files changed, 9620 insertions, 0 deletions

diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md
new file mode 100644
index 000000000..3d24bc7ae
--- /dev/null
+++ b/gcc/config/m32c/addsub.md
@@ -0,0 +1,260 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; add, sub
+
+(define_insn "addqi3"
+  [(set (match_operand:QI 0 "mra_or_sp_operand"
+		  "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
+	(plus:QI (match_operand:QI 1 "mra_operand"
+		  "%0,0,0,0, 0,0,0,0")
+		 (match_operand:QI 2 "mrai_operand"
+		  "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
+  ""
+  "add.b\t%2,%0"
+  [(set_attr "flags" "oszc")]
+  )
+
+(define_insn "addhi3"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
+	 	  "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
+	(plus:HI (match_operand:HI 1 "m32c_any_operand"
+		  "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
+		 (match_operand:HI 2 "m32c_any_operand"
+		  "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
+  ""
+  "@
+   add.w\t%2,%0
+   add.w\t%2,%0
+   add.w\t%2,%0
+   add.w\t%2,%0
+   sub.w\t%m2,%0
+   sub.w\t%m2,%0
+   mova\t%d2[%1],%0
+   stc\t%1,%0
+   mova\t%D2[%1],%0
+   add.w\t%2,%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
+  )
+
+(define_insn "addpsi3"
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
+	(plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
+		  (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
+  "TARGET_A24"
+  "@
+   add.l:q\t%2,%0
+   addx\t%2,%0
+   add.l\t%2,%0
+   add.l\t%2,%0
+   add.l\t%2,%0
+   mova\t%d2[%1],%0
+   mova\t%D2[%1],%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
+  )
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
+                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24 ||TARGET_A16"
+  ""
+  )
+
+(define_insn "addsi3_1"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
+                 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  "TARGET_A16"
+  "*
+  
+  switch (which_alternative)
+    { 
+    case 0:
+      return \"add.w %X2,%h0\;adcf.w %H0\";
+    case 1:
+      return \"add.w %X2,%h0\;adcf.w %H0\";
+    case 2:
+      if (GET_CODE (operands[2]) == SYMBOL_REF)
+        {
+          output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
+          return \"adc.w #%%hi(%d2),%H0\";
+        }
+      else
+        {
+          output_asm_insn (\"add.w %X2,%h0\",operands);
+          operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+          return \"adc.w %X2,%H0\";
+        }
+    case 3:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 4:
+      output_asm_insn (\"add.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"adc.w %X2,%H0\";
+    case 5:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 6:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    case 7:
+      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
+    default:
+      gcc_unreachable ();
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x,x,x")]
+)
+
+(define_insn "addsi3_2"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
+                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24"
+  "add.l\t%2,%0"
+  [(set_attr "flags" "oszc")]
+)
+
+(define_insn "subqi3"
+  [(set (match_operand:QI 0 "mra_or_sp_operand"
+		   "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
+	(minus:QI (match_operand:QI 1 "mra_operand"
+		   "0,0,0,0, 0,0,0,0, 0")
+		  (match_operand:QI 2 "mrai_operand"
+		   "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
+  ""
+  "sub.b\t%2,%0"
+  [(set_attr "flags" "oszc")]
+  )
+
+(define_insn "subhi3"
+  [(set (match_operand:HI 0 "mra_operand"
+		   "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
+	(minus:HI (match_operand:HI 1 "mras_operand"
+		   "0,0,0,0, 0,0")
+		  (match_operand:HI 2 "mrai_operand"
+		   "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
+  ""
+  "@
+   sub.w\t%2,%0
+   sub.w\t%2,%0
+   sub.w\t%2,%0
+   sub.w\t%2,%0
+   add.w\t%m2,%0
+   add.w\t%m2,%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
+  )
+
+(define_insn "subpsi3"
+  [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
+	(minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
+		   (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
+  "TARGET_A24"
+  "sub.%&\t%2,%0"
+  [(set_attr "flags" "oszc")]
+  )
+
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24 ||TARGET_A16"
+  ""
+)
+
+(define_insn "subsi3_1"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  "TARGET_A16"
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"sub.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"sbb.w %X2,%H0\";
+    case 1:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"sub.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"sbb.w %X2,%H0\";
+    case 3:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 4:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    case 5:
+      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
+    default:
+      gcc_unreachable ();
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
+(define_insn "subsi3_2"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
+                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
+  "TARGET_A24"
+  "sub.l\t%2,%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc")]
+)
+
+(define_insn "negqi2"
+  [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
+	(neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+  ""
+  "neg.b\t%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "neghi2"
+  [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
+	(neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+  ""
+  "neg.w\t%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+; We can negate an SImode by operating on the subparts.  GCC deals
+; with this itself for larger modes, but not SI.
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
+	(neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
+  ""
+  "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "absqi2"
+  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
+	(abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+  ""
+  "abs.b\t%0"
+  [(set_attr "flags" "oszc")]
+  )
+
+(define_insn "abshi2"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+	(abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+  ""
+  "abs.w\t%0"
+  [(set_attr "flags" "oszc")]
+  )
diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md
new file mode 100644
index 000000000..3c8e8427b
--- /dev/null
+++ b/gcc/config/m32c/bitops.md
@@ -0,0 +1,422 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Bit-wise operations (and, ior, xor, shift)
+
+; On the R8C and M16C, "address" for bit instructions is usually (but
+; not always!) the *bit* address, not the *byte* address.  This
+; confuses gcc, so we avoid cases where gcc would produce the wrong
+; code.  We're left with absolute addresses and registers, and the odd
+; case of shifting a bit by a variable.
+
+; On the M32C, "address" for bit instructions is a regular address,
+; and the bit number is stored in a separate field.  Thus, we can let
+; gcc do more interesting things.  However, the M32C cannot set all
+; the bits in a 16-bit register, which the R8C/M16C can do.
+
+; However, it all means that we end up with two sets of patterns, one
+; for each chip.
+
+;;----------------------------------------------------------------------
+
+;; First off, all the ways we can set one bit, other than plain IOR.
+
+(define_insn "bset_qi"
+  [(set (match_operand:QI 0 "memsym_operand" "+Si")
+	(ior:QI (subreg:QI (ashift:HI (const_int 1)
+				      (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
+		(match_operand:QI 2 "memsym_operand" "0")))]
+  "TARGET_A16"
+  "bset\t%0[%1]"
+  [(set_attr "flags" "n")]
+  )  
+
+(define_insn "bset_hi"
+  [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
+			 (const_int 1)
+			 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
+	(const_int 1))]
+  "TARGET_A16"
+  "bset\t%0[%1]"
+  [(set_attr "flags" "n")]
+  )  
+
+;;----------------------------------------------------------------------
+
+;; Now all the ways we can clear one bit, other than plain AND.
+
+; This is odd because the shift patterns use QI counts, but we can't
+; easily put QI in $aN without causing problems elsewhere.
+(define_insn "bclr_qi"
+  [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
+			 (const_int 1)
+			 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
+	(const_int 0))]
+  "TARGET_A16"
+  "bclr\t%0[%1]"
+  [(set_attr "flags" "n")]
+  )  
+
+
+;;----------------------------------------------------------------------
+
+;; Now the generic patterns.
+
+(define_insn "andqi3_16"
+  [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
+	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+  "TARGET_A16"
+  "@
+   bclr\t%B2,%0
+   bclr\t%B2,%h0
+   and.b\t%x2,%0
+   and.b\t%x2,%0
+   and.b\t%x2,%0
+   and.b\t%x2,%0"
+  [(set_attr "flags" "n,n,sz,sz,sz,sz")]
+  )
+
+(define_insn "andhi3_16"
+  [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
+	(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
+		(match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
+  "TARGET_A16"
+  "@
+   
+   bclr\t%B2,%0
+   bclr\t%B2-8,1+%0
+   bclr\t%B2,%0
+   and.w\t%X2,%0
+   and.w\t%X2,%0
+   and.w\t%X2,%0
+   and.w\t%X2,%0"
+  [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
+  )
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"and.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"and.w %X2,%H0\";
+    case 1:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"and.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"and.w %X2,%H0\";
+    case 3:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 4:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 5:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    default:
+      gcc_unreachable ();
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
+
+(define_insn "iorqi3_16"
+  [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
+	(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+		(match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
+  "TARGET_A16"
+  "@
+   bset\t%B2,%0
+   bset\t%B2,%h0
+   or.b\t%x2,%0
+   or.b\t%x2,%0
+   or.b\t%x2,%0
+   or.b\t%x2,%0"
+  [(set_attr "flags" "n,n,sz,sz,sz,sz")]
+  )
+
+(define_insn "iorhi3_16"
+  [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
+	(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
+		(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+  "TARGET_A16"
+  "@
+   bset %B2,%0
+   bset\t%B2-8,1+%0
+   bset\t%B2,%0
+   or.w\t%X2,%0
+   or.w\t%X2,%0
+   or.w\t%X2,%0
+   or.w\t%X2,%0"
+  [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
+  )
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+(define_insn "andqi3_24"
+  [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
+	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+  "TARGET_A24"
+  "@
+   bclr\t%B2,%0
+   bclr\t%B2,%0
+   and.b\t%x2,%0
+   and.b\t%x2,%0
+   and.b\t%x2,%0
+   and.b\t%x2,%0"
+  [(set_attr "flags" "n,n,sz,sz,sz,sz")]
+  )
+
+(define_insn "andhi3_24"
+  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
+	(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
+		(match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
+  "TARGET_A24"
+  "@
+   bclr\t%B2,%0
+   bclr\t%B2-8,1+%0
+   bclr\t%B2,%h0
+   bclr\t%B2-8,%H0
+   and.w\t%X2,%0
+   and.w\t%X2,%0
+   and.w\t%X2,%0
+   and.w\t%X2,%0"
+  [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
+  )
+
+
+
+(define_insn "iorqi3_24"
+  [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
+	(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
+		(match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
+  "TARGET_A24"
+  "@
+   bset\t%B2,%0
+   or.b\t%x2,%0
+   or.b\t%x2,%0
+   or.b\t%x2,%0
+   or.b\t%x2,%0"
+  [(set_attr "flags" "n,sz,sz,sz,sz")]
+  )
+
+(define_insn "iorhi3_24"
+  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
+	(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
+		(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+  "TARGET_A24"
+  "@
+   bset\t%B2,%0
+   bset\t%B2-8,1+%0
+   bset\t%B2,%h0
+   bset\t%B2-8,%H0
+   or.w\t%X2,%0
+   or.w\t%X2,%0
+   or.w\t%X2,%0
+   or.w\t%X2,%0"
+  [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
+  )
+
+
+; ----------------------------------------------------------------------
+
+(define_expand "andqi3"
+  [(set (match_operand:QI 0 "mra_operand" "")
+	(and:QI (match_operand:QI 1 "mra_operand" "")
+		(match_operand:QI 2 "mrai_operand" "")))]
+  ""
+  "if (TARGET_A16)
+     emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
+   else
+     emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
+   DONE;"
+  )
+
+(define_expand "andhi3"
+  [(set (match_operand:HI 0 "mra_operand" "")
+	(and:HI (match_operand:HI 1 "mra_operand" "")
+		(match_operand:HI 2 "mrai_operand" "")))]
+  ""
+  "if (TARGET_A16)
+     emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
+   else
+     emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
+   DONE;"
+  )
+
+(define_expand "iorqi3"
+  [(set (match_operand:QI 0 "mra_operand" "")
+	(ior:QI (match_operand:QI 1 "mra_operand" "")
+		(match_operand:QI 2 "mrai_operand" "")))]
+  ""
+  "if (TARGET_A16)
+     emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
+   else
+     emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
+   DONE;"
+  )
+
+(define_expand "iorhi3"
+  [(set (match_operand:HI 0 "mra_operand" "")
+	(ior:HI (match_operand:HI 1 "mra_operand" "")
+		(match_operand:HI 2 "mrai_operand" "")))]
+  ""
+  "if (TARGET_A16)
+     emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
+   else
+     emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
+   DONE;"
+  )
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"or.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"or.w %X2,%H0\";
+    case 1:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"or.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"or.w %X2,%H0\";
+    case 3:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 4:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 5:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    default:
+      gcc_unreachable ();
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
+(define_insn "xorqi3"
+  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
+	(xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
+		(match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+  ""
+  "xor.b\t%x2,%0"
+  [(set_attr "flags" "sz,sz,sz,sz")]
+  )
+
+(define_insn "xorhi3"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+	(xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+		(match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+  ""
+  "xor.w\t%X2,%0"
+  [(set_attr "flags" "sz,sz,sz,sz")]
+  )
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"xor.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"xor.w %X2,%H0\";
+    case 1:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"xor.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"xor.w %X2,%H0\";
+    case 3:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 4:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 5:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    default:
+      gcc_unreachable ();
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
+(define_insn "one_cmplqi2"
+  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
+	(not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
+  ""
+  "not.b\t%0"
+  [(set_attr "flags" "sz,sz")]
+  )
+
+(define_insn "one_cmplhi2"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+	(not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
+  ""
+  "not.w\t%0"
+  [(set_attr "flags" "sz,sz")]
+  )
+
+; Optimizations using bit opcodes
+
+; We need this because combine only looks at three insns at a time,
+; and the bclr_qi pattern uses four - mov, shift, not, and.  GCC
+; should never expand this pattern, because it only shifts a constant
+; by a constant, so gcc should do that itself.
+(define_insn "shift1_qi"
+  [(set (match_operand:QI 0 "mra_operand" "=Rqi")
+	(ashift:QI (const_int 1)
+		   (match_operand 1 "const_int_operand" "In4")))]
+  ""
+  "mov.b\t#1,%0\n\tshl.b\t%1,%0"
+  )
+(define_insn "shift1_hi"
+  [(set (match_operand:HI 0 "mra_operand" "=Rhi")
+	(ashift:HI (const_int 1)
+		   (match_operand 1 "const_int_operand" "In4")))]
+  ""
+  "mov.w\t#1,%0\n\tshl.w\t%1,%0"
+  )
+
+; Generic insert-bit expander, needed so that we can use the bit
+; opcodes for volatile bitfields.
+
+(define_expand "insv"
+  [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
+			 (match_operand 1 "const_int_operand" "")
+			 (match_operand 2 "const_int_operand" ""))
+	(match_operand:HI 3 "const_int_operand" ""))]
+  ""
+  "if (m32c_expand_insv (operands))
+     FAIL;
+   DONE;"
+  )
diff --git a/gcc/config/m32c/blkmov.md b/gcc/config/m32c/blkmov.md
new file mode 100644
index 000000000..e384d3c52
--- /dev/null
+++ b/gcc/config/m32c/blkmov.md
@@ -0,0 +1,242 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2006, 2007, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; various block move instructions
+
+;; R8C:
+;;  SMOVB - while (r3--) { *a1-- = *r1ha0--; } - memcpy
+;;  SMOVF - while (r3--) { *a1++ = *r1ha0++; } - memcpy
+;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset
+
+;; M32CM:
+;;  SCMPU - while (*a0 && *a0 != *a1) { a0++; a1++; } - strcmp
+;;  SIN   - while (r3--) { *a1++ = *a0; }
+;;  SMOVB - while (r3--) { *a1-- = *a0--; } - memcpy
+;;  SMOVF - while (r3--) { *a1++ = *a0++; } - memcpy
+;;  SMOVU - while (*a1++ = *a0++) ; - strcpy
+;;  SOUT  - while (r3--) { *a1 = *a0++; }
+;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset
+
+
+
+;; 0 = destination (mem:BLK ...)
+;; 1 = source (mem:BLK ...)
+;; 2 = count
+;; 3 = alignment
+(define_expand "movmemhi"
+  [(match_operand 0 "ap_operand" "")
+   (match_operand 1 "ap_operand" "")
+   (match_operand 2 "m32c_r3_operand" "")
+   (match_operand 3 "" "")
+   ]
+  ""
+  "if (m32c_expand_movmemhi(operands)) DONE; FAIL;"
+  )
+
+;; We can't use mode iterators for these because M16C uses r1h to extend
+;; the source address, for copying data from ROM to RAM.  We don't yet
+;; support that, but we need to zero our r1h, so the patterns differ.
+
+;; 0 = dest (out)
+;; 1 = src (out)
+;; 2 = count (out)
+;; 3 = dest (in)
+;; 4 = src (in)
+;; 5 = count (in)
+(define_insn "movmemhi_bhi_op"
+  [(set (mem:QI (match_operand:HI 3 "ap_operand" "0"))
+	(mem:QI (match_operand:HI 4 "ap_operand" "1")))
+   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:HI 0 "ap_operand" "=Ra1")
+	(plus:HI (match_dup 3)
+		  (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
+   (set (match_operand:HI 1 "ap_operand" "=Ra0")
+	(plus:HI (match_dup 4)
+		  (zero_extend:HI (match_dup 5))))
+   (use (reg:HI R1_REGNO))]
+  "TARGET_A16"
+  "mov.b:q\t#0,r1h\n\tsmovf.b\t; %0[0..%2-1]=r1h%1[]"
+  )
+(define_insn "movmemhi_bpsi_op"
+  [(set (mem:QI (match_operand:PSI 3 "ap_operand" "0"))
+	(mem:QI (match_operand:PSI 4 "ap_operand" "1")))
+   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
+	(plus:PSI (match_dup 3)
+		  (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
+   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
+	(plus:PSI (match_dup 4)
+		  (zero_extend:PSI (match_dup 5))))]
+  "TARGET_A24"
+  "smovf.b\t; %0[0..%2-1]=%1[]"
+  )
+(define_insn "movmemhi_whi_op"
+  [(set (mem:HI (match_operand:HI 3 "ap_operand" "0"))
+	(mem:HI (match_operand:HI 4 "ap_operand" "1")))
+   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:HI 0 "ap_operand" "=Ra1")
+	(plus:HI (match_dup 3)
+		  (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
+   (set (match_operand:HI 1 "ap_operand" "=Ra0")
+	(plus:HI (match_dup 4)
+		  (zero_extend:HI (match_dup 5))))
+   (use (reg:HI R1_REGNO))]
+  "TARGET_A16"
+  "mov.b:q\t#0,r1h\n\tsmovf.w\t; %0[0..%2-1]=r1h%1[]"
+  )
+(define_insn "movmemhi_wpsi_op"
+  [(set (mem:HI (match_operand:PSI 3 "ap_operand" "0"))
+	(mem:HI (match_operand:PSI 4 "ap_operand" "1")))
+   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
+	(plus:PSI (match_dup 3)
+		  (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
+   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
+	(plus:PSI (match_dup 4)
+		  (zero_extend:PSI (match_dup 5))))]
+  "TARGET_A24"
+  "smovf.w\t; %0[0..%2-1]=%1[]"
+  )
+
+
+
+;; 0 = destination (mem:BLK ...)
+;; 1 = number of bytes
+;; 2 = value to store
+;; 3 = alignment
+(define_expand "setmemhi"
+  [(match_operand 0 "ap_operand" "")
+   (match_operand 1 "m32c_r3_operand" "")
+   (match_operand 2 "m32c_r0_operand" "")
+   (match_operand 3 "" "")
+   ]
+  "TARGET_A24"
+  "if (m32c_expand_setmemhi(operands)) DONE; FAIL;"
+  )
+
+;; 0 = address (out)
+;; 1 = count (out)
+;; 2 = value (in)
+;; 3 = address (in)
+;; 4 = count (in)
+(define_insn "setmemhi_b<mode>_op"
+  [(set (mem:QI (match_operand:HPSI 3 "ap_operand" "0"))
+	(match_operand:QI 2 "m32c_r0_operand" "R0w"))
+   (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
+	(plus:HPSI (match_dup 3)
+		  (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
+  "TARGET_A24"
+  "sstr.b\t; %0[0..%1-1]=%2"
+  )
+
+(define_insn "setmemhi_w<mode>_op"
+  [(set (mem:HI (match_operand:HPSI 3 "ap_operand" "0"))
+	(match_operand:HI 2 "m32c_r0_operand" "R0w"))
+   (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
+	(const_int 0))
+   (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
+	(plus:HPSI (match_dup 3)
+		  (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
+  "TARGET_A24"
+  "sstr.w\t; %0[0..%1-1]=%2"
+  )
+
+
+;; SCMPU sets the flags according to the result of the string
+;; comparison.  GCC wants the result to be a signed value reflecting
+;; the result, which it then compares to zero.  Hopefully we can
+;; optimize that later (see peephole in cond.md).  Meanwhile, the
+;; strcmp builtin is expanded to a SCMPU followed by a flags-to-int
+;; pattern in cond.md.
+
+;; 0 = result:HI
+;; 1 = destination (mem:BLK ...)
+;; 2 = source (mem:BLK ...)
+;; 3 = alignment
+
+(define_expand "cmpstrsi"
+  [(match_operand:HI 0 "" "")
+   (match_operand 1 "ap_operand" "")
+   (match_operand 2 "ap_operand" "")
+   (match_operand 3 "" "")
+   ]
+  "TARGET_A24"
+  "if (m32c_expand_cmpstr(operands)) DONE; FAIL;"
+  )
+
+;; 0 = string1
+;; 1 = string2
+
+(define_insn "cmpstrhi_op"
+  [(set (reg:CC FLG_REGNO)
+	(compare:CC (mem:BLK (match_operand:PSI 0 "ap_operand" "Ra0"))
+		    (mem:BLK (match_operand:PSI 1 "ap_operand" "Ra1"))))
+   (clobber (match_operand:PSI 2 "ap_operand" "=0"))
+   (clobber (match_operand:PSI 3 "ap_operand" "=1"))]
+  "TARGET_A24"
+  "scmpu.b\t; flags := strcmp(*%0,*%1)"
+  [(set_attr "flags" "oszc")]
+  )
+
+
+
+;; Note that SMOVU leaves the address registers pointing *after*
+;; the NUL at the end of the string.  This is not what gcc expects; it
+;; expects the address registers to point *at* the NUL.  The expander
+;; must emit a suitable add insn.
+
+;; 0 = target: set to &NUL in dest
+;; 1 = destination (mem:BLK ...)
+;; 2 = source (mem:BLK ...)
+
+(define_expand "movstr"
+  [(match_operand 0 "m32c_nonimmediate_operand" "")
+   (match_operand 1 "ap_operand" "")
+   (match_operand 2 "ap_operand" "")
+   ]
+  "TARGET_A24"
+  "if (m32c_expand_movstr(operands)) DONE; FAIL;"
+  )
+
+;; 0 = dest (out)
+;; 1 = src (out) (clobbered)
+;; 2 = dest (in)
+;; 3 = src (in)
+(define_insn "movstr_op"
+  [(set (mem:BLK (match_operand:PSI 2 "ap_operand" "0"))
+	(mem:BLK (match_operand:PSI 3 "ap_operand" "1")))
+   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
+	(plus:PSI (match_dup 2)
+		  (unspec:PSI [(const_int 0)] UNS_SMOVU)))
+   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
+	(plus:PSI (match_dup 3)
+		  (unspec:PSI [(const_int 0)] UNS_SMOVU)))]
+  "TARGET_A24"
+  "smovu.b\t; while (*%2++ := *%3++) != 0"
+  [(set_attr "flags" "*")]
+  )
+  
diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md
new file mode 100644
index 000000000..c751070e7
--- /dev/null
+++ b/gcc/config/m32c/cond.md
@@ -0,0 +1,293 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+; conditionals - cmp, jcc, setcc, etc.
+
+; Special note about conditional instructions: GCC always emits the
+; compare right before the insn, which is good, because m32c's mov
+; insns modify the flags.  However, this means that any conditional
+; insn that may require reloading must be kept with its compare until
+; after reload finishes, else the reload insns might clobber the
+; flags.  Thus, these rules:
+;
+; * the cmp* expanders just save the operands in compare_op0 and
+;   compare_op1 via m32c_pend_compare.
+; * conditional insns that won't need reload can call
+;   m32c_unpend_compare before their expansion.
+; * other insns must expand to include the compare operands within,
+;   then split after reload to a separate compare and conditional.
+
+; Until support for relaxing is supported in gas, we must assume that
+; short labels won't reach, so we must use long labels.
+; Unfortunately, there aren't any conditional jumps with long labels,
+; so instead we invert the conditional and jump around a regular jump.
+
+; Note that we can, at some point in the future, add code to omit the
+; "cmp" portion of the insn if the preceding insn happened to set the
+; right flags already.  For example, a mov followed by a "cmp *,0" is
+; redundant; the move already set the Z flag.
+
+(define_insn_and_split "cbranch<mode>4"
+  [(set (pc) (if_then_else
+	      (match_operator 0 "m32c_cmp_operator"
+			      [(match_operand:QHPSI 1 "mra_operand" "RraSd")
+			       (match_operand:QHPSI 2 "mrai_operand" "iRraSd")])
+              (label_ref (match_operand 3 "" ""))
+	      (pc)))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_dup 1)
+		 (match_dup 2)))
+   (set (pc) (if_then_else (match_op_dup 0 [(reg:CC FLG_REGNO) (const_int 0)])
+			   (label_ref (match_dup 3))
+			   (pc)))]
+  ""
+  )
+
+(define_insn "bcc_op"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+		       [(reg:CC FLG_REGNO) (const_int 0)])
+                      (label_ref (match_operand 1 ""))
+                      (pc)))]
+  ""
+  "j%c0\t%l1"
+  [(set_attr "flags" "n")]
+)
+
+(define_insn "stzx_16"
+  [(set (match_operand:QI 0 "mrai_operand" "=R0w,R0w,R0w")
+	(if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
+			 (match_operand:QI 1 "const_int_operand" "i,i,0")
+			 (match_operand:QI 2 "const_int_operand" "i,0,i")))]
+  "TARGET_A16 && reload_completed"
+  "@
+   stzx\t%1,%2,%0
+   stz\t%1,%0
+   stnz\t%2,%0"
+  [(set_attr "flags" "n,n,n")]
+)
+
+(define_insn "stzx_24_<mode>"
+  [(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd")
+	(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
+			 (match_operand:QHI 1 "const_int_operand" "i,i,0")
+			 (match_operand:QHI 2 "const_int_operand" "i,0,i")))]
+  "TARGET_A24 && reload_completed"
+  "@
+   stzx.<bwl>\t%1,%2,%0
+   stz.<bwl>\t%1,%0
+   stnz.<bwl>\t%2,%0"
+  [(set_attr "flags" "n,n,n")])
+
+(define_insn_and_split "stzx_reversed_<mode>"
+  [(set (match_operand:QHI 0 "m32c_r0_operand" "=R0w")
+	(if_then_else:QHI (ne (reg:CC FLG_REGNO) (const_int 0))
+			 (match_operand:QHI 1 "const_int_operand" "")
+			 (match_operand:QHI 2 "const_int_operand" "")))]
+  "(TARGET_A24 || GET_MODE (operands[0]) == QImode) && reload_completed"
+  "#"
+  ""
+  [(set (match_dup 0)
+	(if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
+		      (match_dup 2)
+		      (match_dup 1)))]
+  ""
+  )
+
+
+(define_insn "cmp<mode>_op"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
+		 (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
+  ""
+  "* return m32c_output_compare(insn, operands); "
+  [(set_attr "flags" "oszc")])
+
+;; m32c_conditional_register_usage changes the setcc_gen_code array to
+;; point to the _24 variants if needed.
+
+;; We need to keep the compare and conditional sets together through
+;; reload, because reload might need to add address reloads to the
+;; set, which would clobber the flags.  By keeping them together, the
+;; reloads get put before the compare, thus preserving the flags.
+
+;; These are the post-split patterns for the conditional sets.
+
+(define_insn "scc_op"
+  [(set (match_operand:QI 0 "register_operand" "=Rqi")
+	(match_operator:QI 1 "ordered_comparison_operator"
+	 [(reg:CC FLG_REGNO) (const_int 0)]))]
+  "TARGET_A16 && reload_completed"
+  "* return m32c_scc_pattern(operands, GET_CODE (operands[1]));")
+
+(define_insn "scc_24_op"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd")
+	(match_operator:HI 1 "ordered_comparison_operator"
+	 [(reg:CC FLG_REGNO) (const_int 0)]))]
+  "TARGET_A24 && reload_completed"
+  "sc%c1\t%0"
+  [(set_attr "flags" "n")]
+)
+
+;; These are the pre-split patterns for the conditional sets.
+
+(define_insn_and_split "cstore<mode>4"
+  [(set (match_operand:QI 0 "register_operand" "=Rqi")
+	(match_operator:QI 1 "ordered_comparison_operator"
+	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
+	  (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
+  "TARGET_A16"
+  "#"
+  "reload_completed"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_dup 2)
+		 (match_dup 3)))
+   (set (match_dup 0)
+	(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
+  ""
+  [(set_attr "flags" "x")]
+)
+
+(define_insn_and_split "cstore<mode>4_24"
+  [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
+	(match_operator:HI 1 "ordered_comparison_operator"
+	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
+	  (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
+  "TARGET_A24"
+  "#"
+  "reload_completed"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_dup 2)
+		 (match_dup 3)))
+   (set (match_dup 0)
+	(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
+  ""
+  [(set_attr "flags" "x")]
+)
+
+(define_insn_and_split "movqicc_<code>_<mode>"
+  [(set (match_operand:QI 0 "register_operand" "=R0w")
+        (if_then_else:QI (eqne_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
+				       (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
+			  (match_operand:QI 3 "const_int_operand" "")
+			  (match_operand:QI 4 "const_int_operand" "")))]
+  ""
+  "#"
+  "reload_completed"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_dup 1)
+		 (match_dup 2)))
+   (set (match_dup 0)
+        (if_then_else:QI (eqne_cond:QI (reg:CC FLG_REGNO) (const_int 0))
+			 (match_dup 3)
+			 (match_dup 4)))]
+  ""
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn_and_split "movhicc_<code>_<mode>"
+  [(set (match_operand:HI 0 "register_operand" "=R0w")
+        (if_then_else:HI (eqne_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
+				       (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
+			  (match_operand:QI 3 "const_int_operand" "")
+			  (match_operand:QI 4 "const_int_operand" "")))]
+  "TARGET_A24"
+  "#"
+  "reload_completed"
+  [(set (reg:CC FLG_REGNO)
+	(compare (match_dup 1)
+		 (match_dup 2)))
+   (set (match_dup 0)
+        (if_then_else:HI (eqne_cond:HI (reg:CC FLG_REGNO) (const_int 0))
+			 (match_dup 3)
+			 (match_dup 4)))]
+  ""
+  [(set_attr "flags" "x")]
+  )
+
+;; And these are the expanders.
+
+(define_expand "movqicc"
+  [(set (match_operand:QI 0 "register_operand" "")
+        (if_then_else:QI (match_operand 1 "m32c_eqne_operator" "")
+                         (match_operand:QI 2 "const_int_operand" "")
+                         (match_operand:QI 3 "const_int_operand" "")))]
+  ""
+  "if (m32c_expand_movcc(operands))
+     FAIL;
+   DONE;"
+)
+
+(define_expand "movhicc"
+  [(set (match_operand:HI 0 "mra_operand" "")
+        (if_then_else:HI (match_operand 1 "m32c_eqne_operator" "")
+                         (match_operand:HI 2 "const_int_operand" "")
+                         (match_operand:HI 3 "const_int_operand" "")))]
+  "TARGET_A24"
+  "if (m32c_expand_movcc(operands))
+     FAIL;
+   DONE;"
+)
+
+
+;; CMP opcodes subtract two values, set the flags, and discard the
+;; value.  This pattern recovers the sign of the discarded value based
+;; on the flags.  Operand 0 is set to -1, 0, or 1.  This is used for
+;; the cmpstr pattern.  For optimal code, this should be removed if
+;; followed by a suitable CMP insn (see the peephole following).  This
+;; pattern is 7 bytes and 5 cycles.  If you don't need specific
+;; values, a 5/4 pattern can be made with SCGT and BMLT to set the
+;; appropriate bits.
+
+(define_insn "cond_to_int"
+  [(set (match_operand:HI 0 "mra_qi_operand" "=Rqi")
+	(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
+			 (const_int -1)
+			 (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
+					  (const_int 0)
+					  (const_int -1))))]
+  "TARGET_A24"
+  "sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0"
+  [(set_attr "flags" "x")]
+  )  
+
+;; A cond_to_int followed by a compare against zero is essentially a
+;; no-op.  However, the result of the cond_to_int may be used by later
+;; insns, so make sure it's dead before deleting its set.
+
+(define_peephole2
+  [(set (match_operand:HI 0 "mra_qi_operand" "")
+	(if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
+			 (const_int -1)
+			 (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
+					  (const_int 0)
+					  (const_int -1))))
+   (set (reg:CC FLG_REGNO)
+	(compare (match_operand:HI 1 "mra_qi_operand" "")
+		 (const_int 0)))
+   ]
+  "rtx_equal_p (operands[0], operands[1])
+     && dead_or_set_p (peep2_next_insn (1), operands[0])"
+  [(const_int 1)]
+  "")
diff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md
new file mode 100644
index 000000000..5f4718dfe
--- /dev/null
+++ b/gcc/config/m32c/jump.md
@@ -0,0 +1,135 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; jump, conditionals, calls, etc
+
+(define_insn "indirect_jump_16"
+  [(set (pc)
+       (match_operand:HI 0 "register_operand" "Rhi"))]
+  "TARGET_A16"
+;  "jmpi.a\t%0"
+  ; no 16-bit jmpi in r8c
+  "push.b #0 | push.w\t%0 | rts"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "indirect_jump_24"
+  [(set (pc)
+       (match_operand:PSI 0 "register_operand" "Rpi"))]
+  "TARGET_A24"
+  "jmpi.a\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_expand "indirect_jump"
+  [(match_operand 0 "register_operand" "")]
+  ""
+  "if (TARGET_A16)
+     emit_jump_insn (gen_indirect_jump_16(operands[0]));
+   else
+     emit_jump_insn (gen_indirect_jump_24(operands[0]));
+   DONE;"
+  )
+
+; We can replace this with jmp.s when gas supports relaxing.  m32c
+; opcodes are too complicated to try to compute their sizes here, it's
+; far easier (and more reliable) to let gas worry about it.
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "jmp.a\t%l0"
+  [(set_attr "flags" "n")]
+)
+
+; No 16-bit indirect calls on r8c/m16c.  */
+(define_insn "call"
+  [(call (match_operand:QI 0 "memory_operand" "Si,SaSb,?Rmm")
+	 (match_operand 1 "" ""))
+   (use (match_operand 2 "immediate_operand" ""))]
+  ""
+  "*
+switch (which_alternative) {
+  case 0:
+    {
+      HOST_WIDE_INT func_vect_num = 
+      current_function_special_page_vector(XEXP (operands[0], 0));
+      if (func_vect_num)
+        {
+          operands[3] = gen_rtx_CONST_INT (VOIDmode, func_vect_num);
+          return \"jsrs\t%3\";
+        }
+      else
+        return \"jsr.a\t%0\";
+    }
+  case 1: return TARGET_A16 ? \"push.w %a0 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a0\";
+  case 2: return \"jsri.a\t%a0\";
+  default: gcc_unreachable ();
+}"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "call_value"
+  [(set (match_operand 0 "m32c_return_operand" "=RdiRmmRpa,RdiRmmRpa,RdiRmmRpa")
+	(call (match_operand:QI 1 "memory_operand" "Si,SaSb,?Rmm")
+	      (match_operand 2 "" "")))
+   (use (match_operand 3 "immediate_operand" ""))]
+  ""
+  "*
+switch (which_alternative) {
+  case 0:
+    {
+      HOST_WIDE_INT func_vect_num = 
+      current_function_special_page_vector(XEXP (operands[1], 0));
+      if (func_vect_num)
+        {
+          operands[4] = gen_rtx_CONST_INT (VOIDmode, func_vect_num);
+          return \"jsrs\t%4\";
+        }
+      else
+        return \"jsr.a\t%1\";
+    }
+  case 1: return TARGET_A16 ? \"push.w %a1 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a1\";
+  case 2: return \"jsri.a\t%a1\";
+  default: gcc_unreachable ();
+}"
+  [(set_attr "flags" "x,x,x")]
+  )
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+                    (const_int 0))
+              (match_operand 1 "" "")
+              (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
+  DONE;
+}")
diff --git a/gcc/config/m32c/m32c-lib1.S b/gcc/config/m32c/m32c-lib1.S
new file mode 100644
index 000000000..9b6577871
--- /dev/null
+++ b/gcc/config/m32c/m32c-lib1.S
@@ -0,0 +1,231 @@
+/* libgcc routines for R8C/M16C/M32C
+   Copyright (C) 2005, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
+#define A16
+#define A(n,w) n
+#define W w
+#else
+#define A24
+#define A(n,w) w
+#define W l
+#endif
+
+
+#ifdef L__m32c_memregs
+
+/* Warning: these memory locations are used as a register bank.  They
+   *must* end up consecutive in any final executable, so you may *not*
+   use the otherwise obvious ".comm" directive to allocate space for
+   them. */
+
+	.bss
+	.global	mem0
+mem0:	.space	1
+	.global	mem1
+mem1:	.space	1
+	.global	mem2
+mem2:	.space	1
+	.global	mem3
+mem3:	.space	1
+	.global	mem4
+mem4:	.space	1
+	.global	mem5
+mem5:	.space	1
+	.global	mem6
+mem6:	.space	1
+	.global	mem7
+mem7:	.space	1
+	.global	mem8
+mem8:	.space	1
+	.global	mem9
+mem9:	.space	1
+	.global	mem10
+mem10:	.space	1
+	.global	mem11
+mem11:	.space	1
+	.global	mem12
+mem12:	.space	1
+	.global	mem13
+mem13:	.space	1
+	.global	mem14
+mem14:	.space	1
+	.global	mem15
+mem15:	.space	1
+
+#endif
+
+#ifdef L__m32c_eh_return
+	.text
+	.global __m32c_eh_return
+__m32c_eh_return:	
+
+	/* At this point, r0 has the stack adjustment, r1r3 has the
+	   address to return to.  The stack looks like this:
+
+	   old_ra
+	   old_fp
+	   <- unwound sp
+	   ...
+	   fb
+	   through
+	   r0
+	   <- sp
+
+	   What we need to do is restore all the registers, update the
+	   stack, and return to the right place.
+	*/
+
+	stc	sp,a0
+	
+	add.W	A(#16,#24),a0
+	/* a0 points to the current stack, just above the register
+	   save areas */
+
+	mov.w	a0,a1
+	exts.w	r0
+	sub.W	A(r0,r2r0),a1
+	sub.W	A(#3,#4),a1
+	/* a1 points to the new stack.  */
+
+	/* This is for the "rts" below.  */
+	mov.w	r1,[a1]
+#ifdef A16
+	mov.w	r2,r1
+	mov.b	r1l,2[a1]
+#else
+	mov.w	r2,2[a1]
+#endif
+
+	/* This is for the "popc sp" below.  */
+	mov.W	a1,[a0]	
+
+	popm    r0,r1,r2,r3,a0,a1,sb,fb
+	popc	sp
+	rts
+#endif
+
+/* SImode arguments for SI foo(SI,SI) functions.  */
+#ifdef A16
+#define SAL  5[fb]
+#define SAH  7[fb]
+#define SBL  9[fb]
+#define SBH 11[fb]
+#else
+#define SAL  8[fb]
+#define SAH 10[fb]
+#define SBL 12[fb]
+#define SBH 14[fb]
+#endif
+
+#ifdef L__m32c_mulsi3
+	.text
+	.global ___mulsi3
+___mulsi3:
+	enter	#0
+	push.w	r2
+	mov.w	SAL,r0
+	mulu.w	SBL,r0		/* writes to r2r0 */
+	mov.w	r0,mem0
+	mov.w	r2,mem2
+	mov.w	SAL,r0
+	mulu.w	SBH,r0		/* writes to r2r0 */
+	add.w	r0,mem2
+	mov.w	SAH,r0
+	mulu.w	SBL,r0		/* writes to r2r0 */
+	add.w	r0,mem2
+	pop.w	r2
+	exitd
+#endif
+
+#ifdef L__m32c_cmpsi2
+	.text
+	.global ___cmpsi2
+___cmpsi2:
+	enter	#0
+	cmp.w	SBH,SAH
+	jgt	cmpsi_gt
+	jlt	cmpsi_lt
+	cmp.w	SBL,SAL
+	jgt	cmpsi_gt
+	jlt	cmpsi_lt
+	mov.w	#1,r0
+	exitd
+cmpsi_gt:
+	mov.w	#2,r0
+	exitd
+cmpsi_lt:
+	mov.w	#0,r0
+	exitd
+#endif
+
+#ifdef L__m32c_ucmpsi2
+	.text
+	.global ___ucmpsi2
+___ucmpsi2:
+	enter	#0
+	cmp.w	SBH,SAH
+	jgtu	cmpsi_gt
+	jltu	cmpsi_lt
+	cmp.w	SBL,SAL
+	jgtu	cmpsi_gt
+	jltu	cmpsi_lt
+	mov.w	#1,r0
+	exitd
+cmpsi_gt:
+	mov.w	#2,r0
+	exitd
+cmpsi_lt:
+	mov.w	#0,r0
+	exitd
+#endif
+
+#ifdef L__m32c_jsri16
+	.text
+#ifdef A16
+	.global	m32c_jsri16
+m32c_jsri16:
+	add.w	#-1, sp
+
+	/* Read the address (16 bits) and return address (24 bits) off
+	the stack.  */
+	mov.w	4[sp], r0
+	mov.w	1[sp], r3
+	mov.b	3[sp], a0 /* This zero-extends, so the high byte has
+			     zero in it.  */
+
+	/* Write the return address, then new address, to the stack.  */
+	mov.w	a0, 1[sp] /* Just to get the zero in 2[sp].  */
+	mov.w	r0, 0[sp]
+	mov.w	r3, 3[sp]
+	mov.b	a0, 5[sp]
+
+	/* This "returns" to the target address, leaving the pending
+	return address on the stack.  */
+	rts
+#endif
+
+#endif
diff --git a/gcc/config/m32c/m32c-lib2-trapv.c b/gcc/config/m32c/m32c-lib2-trapv.c
new file mode 100644
index 000000000..bb61ceaf0
--- /dev/null
+++ b/gcc/config/m32c/m32c-lib2-trapv.c
@@ -0,0 +1,43 @@
+/* 16-bit trapping arithmetic routines for R8C/M16C/M32C
+   Copyright (C) 2009
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* See the comment by the definition of LIBGCC2_UNITS_PER_WORD in
+   m32c.h for why we are creating extra versions of some of the
+   functions defined in libgcc2.c.
+
+   Note - this file is separate from m32c-lib2.c so that the following
+   functions will appear in the their object file.  This is necessary
+   because they call abort() which is defined in the C library whereas
+   the functions in m32c-lib2.c are completely self sufficieent.  */
+
+#define LIBGCC2_UNITS_PER_WORD 2
+
+#define L_mulvsi3
+#define L_negvsi2
+#define L_addvsi3
+#define L_subvsi3
+
+#include "libgcc2.c"
diff --git a/gcc/config/m32c/m32c-lib2.c b/gcc/config/m32c/m32c-lib2.c
new file mode 100644
index 000000000..274affc4a
--- /dev/null
+++ b/gcc/config/m32c/m32c-lib2.c
@@ -0,0 +1,134 @@
+/* libgcc routines for R8C/M16C/M32C
+   Copyright (C) 2005, 2009
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+typedef          int  sint32_type   __attribute__ ((mode (SI)));
+typedef unsigned int  uint32_type   __attribute__ ((mode (SI)));
+typedef int           word_type     __attribute__ ((mode (__word__)));
+
+uint32_type udivmodsi4 (uint32_type, uint32_type, word_type);
+sint32_type __divsi3   (sint32_type, sint32_type);
+sint32_type __modsi3   (sint32_type, sint32_type);
+
+uint32_type
+udivmodsi4 (uint32_type num, uint32_type den, word_type modwanted)
+{
+  uint32_type bit = 1;
+  uint32_type res = 0;
+
+  while (den < num && bit && !(den & (1L << 31)))
+    {
+      den <<= 1;
+      bit <<= 1;
+    }
+  while (bit)
+    {
+      if (num >= den)
+	{
+	  num -= den;
+	  res |= bit;
+	}
+      bit >>= 1;
+      den >>= 1;
+    }
+  if (modwanted)
+    return num;
+  return res;
+}
+
+sint32_type
+__divsi3 (sint32_type a, sint32_type b)
+{
+  word_type neg = 0;
+  sint32_type res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = !neg;
+    }
+
+  if (b < 0)
+    {
+      b = -b;
+      neg = !neg;
+    }
+
+  res = udivmodsi4 (a, b, 0);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+sint32_type
+__modsi3 (sint32_type a, sint32_type b)
+{
+  word_type neg = 0;
+  sint32_type res;
+
+  if (a < 0)
+    {
+      a = -a;
+      neg = 1;
+    }
+
+  if (b < 0)
+    b = -b;
+
+  res = udivmodsi4 (a, b, 1);
+
+  if (neg)
+    res = -res;
+
+  return res;
+}
+
+/* See the comment by the definition of LIBGCC2_UNITS_PER_WORD in
+   m32c.h for why we are creating extra versions of some of the
+   functions defined in libgcc2.c.  */
+
+#define LIBGCC2_UNITS_PER_WORD 2
+
+#define L_clzsi2
+#define L_ctzsi2
+#define L_ffssi2
+#define L_paritysi2
+#define L_popcountsi2
+
+#include "libgcc2.c"
+
+uint32_type
+__udivsi3 (uint32_type a, uint32_type b)
+{
+  return udivmodsi4 (a, b, 0);
+}
+
+uint32_type
+__umoddi3 (uint32_type a, uint32_type b)
+{
+  return udivmodsi4 (a, b, 1);
+}
diff --git a/gcc/config/m32c/m32c-modes.def b/gcc/config/m32c/m32c-modes.def
new file mode 100644
index 000000000..80412104b
--- /dev/null
+++ b/gcc/config/m32c/m32c-modes.def
@@ -0,0 +1,29 @@
+/* Target-Specific Modes for R8C/M16C/M32C
+   Copyright (C) 2005, 2007
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* 24-bit pointers, whole */
+/*INT_MODE (PI, 3);*/
+
+/* 24-bit pointers, in 32-bit units */
+PARTIAL_INT_MODE (SI);
+
+/* 48-bit MULEX result */
+/* INT_MODE (MI, 6); */
diff --git a/gcc/config/m32c/m32c-pragma.c b/gcc/config/m32c/m32c-pragma.c
new file mode 100644
index 000000000..df976574b
--- /dev/null
+++ b/gcc/config/m32c/m32c-pragma.c
@@ -0,0 +1,135 @@
+/* M32C Pragma support
+   Copyright (C) 2004, 2007, 2010 Free Software Foundation, Inc.
+   Contributed by Red Hat, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "c-family/c-pragma.h"
+#include "c-family/c-common.h"
+#include "diagnostic-core.h"
+#include "cpplib.h"
+#include "hard-reg-set.h"
+#include "output.h"
+#include "m32c-protos.h"
+#include "function.h"
+#define MAX_RECOG_OPERANDS 10
+#include "reload.h"
+#include "target.h"
+
+/* Implements the "GCC memregs" pragma.  This pragma takes only an
+   integer, and is semantically identical to the -memregs= command
+   line option.  The only catch is, the programmer should only use
+   this pragma at the beginning of the file (preferably, in some
+   project-wide header) to avoid ABI changes related to changing the
+   list of available "registers".  */
+static void
+m32c_pragma_memregs (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  /* on off */
+  tree val;
+  enum cpp_ttype type;
+  HOST_WIDE_INT i;
+
+  type = pragma_lex (&val);
+  if (type == CPP_NUMBER)
+    {
+      if (host_integerp (val, 1))
+	{
+	  i = tree_low_cst (val, 1);
+
+	  type = pragma_lex (&val);
+	  if (type != CPP_EOF)
+	    warning (0, "junk at end of #pragma GCC memregs [0..16]");
+
+	  if (0 <= i && i <= 16)
+	    {
+	      if (!ok_to_change_target_memregs)
+		{
+		  warning (0,
+			   "#pragma GCC memregs must precede any function decls");
+		  return;
+		}
+	      target_memregs = i;
+	      m32c_conditional_register_usage ();
+	    }
+	  else
+	    {
+	      warning (0, "#pragma GCC memregs takes a number [0..16]");
+	    }
+
+	  return;
+	}
+    }
+
+  error ("#pragma GCC memregs takes a number [0..16]");
+}
+
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+   variable name and an address, and arranges for that variable to be
+   "at" that address.  The variable is also made volatile.  */
+static void
+m32c_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  /* on off */
+  tree var, addr;
+  enum cpp_ttype type;
+
+  type = pragma_lex (&var);
+  if (type == CPP_NAME)
+    {
+      type = pragma_lex (&addr);
+      if (type == CPP_NUMBER)
+	{
+	  if (var != error_mark_node)
+	    {
+	      unsigned uaddr = tree_low_cst (addr, 1);
+	      m32c_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);
+	    }
+
+	  type = pragma_lex (&var);
+	  if (type != CPP_EOF)
+	    {
+	      error ("junk at end of #pragma ADDRESS");
+	    }
+	  return;
+	}
+    }
+  error ("malformed #pragma ADDRESS variable address");
+}
+
+/* Implements REGISTER_TARGET_PRAGMAS.  */
+void
+m32c_register_pragmas (void)
+{
+  c_register_pragma ("GCC", "memregs", m32c_pragma_memregs);
+  c_register_pragma (NULL, "ADDRESS", m32c_pragma_address);
+  c_register_pragma (NULL, "address", m32c_pragma_address);
+
+  /* R8C and M16C have 16-bit pointers in a 20-bit address zpace.
+     M32C has 24-bit pointers in a 24-bit address space, so does not
+     need far pointers, but we accept the qualifier anyway, as a
+     no-op.  */
+  if (TARGET_A16)
+    c_register_addr_space ("__far", ADDR_SPACE_FAR);
+  else
+    c_register_addr_space ("__far", ADDR_SPACE_GENERIC);
+}
diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h
new file mode 100644
index 000000000..f7c32e7e8
--- /dev/null
+++ b/gcc/config/m32c/m32c-protos.h
@@ -0,0 +1,103 @@
+/* Target Prototypes for R8C/M16C/M32C
+   Copyright (C) 2005, 2007, 2008, 2010
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#define MM enum machine_mode
+#define UINT unsigned int
+
+void m32c_conditional_register_usage (void);
+int  m32c_const_ok_for_constraint_p (HOST_WIDE_INT, char, const char *);
+UINT m32c_dwarf_frame_regnum (int);
+int  m32c_eh_return_data_regno (int);
+void m32c_emit_epilogue (void);
+void m32c_emit_prologue (void);
+int  m32c_epilogue_uses (int);
+int  m32c_extra_address_constraint (char, const char *);
+int  m32c_extra_memory_constraint (char, const char *);
+int  m32c_function_arg_regno_p (int);
+void m32c_init_expanders (void);
+int  m32c_initial_elimination_offset (int, int);
+void m32c_output_reg_pop (FILE *, int);
+void m32c_output_reg_push (FILE *, int);
+int  m32c_print_operand_punct_valid_p (int);
+unsigned int  m32c_push_rounding (int);
+int  m32c_reg_class_from_constraint (char, const char *);
+void m32c_register_pragmas (void);
+void m32c_note_pragma_address (const char *, unsigned);
+int  m32c_regno_ok_for_base_p (int);
+int  m32c_trampoline_alignment (void);
+int  m32c_trampoline_size (void);
+
+#ifdef RTX_CODE
+
+int  m32c_cannot_change_mode_class (MM, MM, int);
+int  m32c_class_max_nregs (int, MM);
+rtx  m32c_eh_return_stackadj_rtx (void);
+void m32c_emit_eh_epilogue (rtx);
+int  m32c_expand_cmpstr (rtx *);
+int  m32c_expand_insv (rtx *);
+int  m32c_expand_movcc (rtx *);
+int  m32c_expand_movmemhi (rtx *);
+int  m32c_expand_movstr (rtx *);
+void m32c_expand_neg_mulpsi3 (rtx *);
+int  m32c_expand_setmemhi (rtx *);
+int  m32c_extra_constraint_p (rtx, char, const char *);
+int  m32c_extra_constraint_p2 (rtx, char, const char *);
+int  m32c_hard_regno_nregs (int, MM);
+int  m32c_hard_regno_ok (int, MM);
+bool m32c_illegal_subreg_p (rtx);
+bool m32c_immd_dbl_mov (rtx *, MM);
+rtx  m32c_incoming_return_addr_rtx (void);
+int  m32c_legitimate_constant_p (rtx);
+int  m32c_legitimize_reload_address (rtx *, MM, int, int, int);
+int  m32c_limit_reload_class (MM, int);
+int  m32c_modes_tieable_p (MM, MM);
+bool m32c_mov_ok (rtx *, MM);
+char * m32c_output_compare (rtx, rtx *);
+int  m32c_preferred_output_reload_class (rtx, int);
+int  m32c_preferred_reload_class (rtx, int);
+int  m32c_prepare_move (rtx *, MM);
+int  m32c_prepare_shift (rtx *, int, int);
+void m32c_print_operand (FILE *, rtx, int);
+void m32c_print_operand_address (FILE *, rtx);
+int  m32c_reg_ok_for_base_p (rtx, int);
+enum reg_class m32c_regno_reg_class (int);
+rtx  m32c_return_addr_rtx (int);
+const char *m32c_scc_pattern (rtx *, RTX_CODE);
+int  m32c_secondary_reload_class (int, MM, rtx);
+int  m32c_split_move (rtx *, MM, int);
+int  m32c_split_psi_p (rtx *);
+int current_function_special_page_vector (rtx);
+
+#endif
+
+#ifdef TREE_CODE
+
+tree m32c_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
+void m32c_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+bool m32c_promote_function_return (const_tree);
+int  m32c_special_page_vector_p (tree);
+void m32c_output_aligned_common (FILE *, tree, const char *,
+				 int, int, int);
+
+#endif
+
+#undef MM
+#undef UINT
diff --git a/gcc/config/m32c/m32c.abi b/gcc/config/m32c/m32c.abi
new file mode 100644
index 000000000..ee8324028
--- /dev/null
+++ b/gcc/config/m32c/m32c.abi
@@ -0,0 +1,132 @@
+   Target Definitions for R8C/M16C/M32C
+   Copyright (C) 2005, 2007
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.
+
+
+These are just some random notes I used during development of this
+port.  Please don't consider these to be "official" specifications,
+just additional information to help make the code easier to
+understand.
+
+
+Frame
+=====
+
+	+--------------------
+	| incoming args
+	+--------------------
+	| return Address
+osp ->	+--------------------
+	| saved fp
+fp ->	+--------------------
+	| local data
+	+--------------------
+	| saved regs
+	+--------------------
+	| outgoing args (opt)
+sp ->	+--------------------
+
+Argument Passing
+================
+
+r8c, m16c
+---------
+
+First arg may be passed in r1l or r1 if it (1) fits (QImode or
+HImode), (2) is named, and (3) is an integer or pointer type (no
+structs, floats, etc).  Otherwise, it's passed on the stack.
+
+Second arg may be passed in r2, same restrictions (but not QImode),
+even if the first arg is passed on the stack.
+
+Third and further args are passed on the stack.  No padding is used,
+stack "alignment" is 8 bits.
+
+m32cm, m32c
+-----------
+First arg may be passed in r0l or r0, same restrictions as above.
+
+Second and further args are passed on the stack.  Padding is used
+after QImode parameters (i.e. lower-addressed byte is the value,
+higher-addressed byte is the padding), stack "alignment" is 16 bits.
+
+
+Return Value
+============
+
+r8c, m16c
+---------
+
+QImode in r0l
+HImode in r0
+near pointer in r0
+(desired)
+SImode in r2r0
+far pointer in r2r0
+(actual)
+Anything bigger than 16 bits is returned in memory, at mem0 (mem0
+through mem15 are provided by libgcc.a)
+
+Aggregate values (regardless of size) are returned by pushing a
+pointer to a temporary area on the stack after the args are pushed.
+The function fills in this area with the value.  Note that this
+pointer on the stack does not affect how register arguments, if any,
+are configured.
+
+m32cm, m32c
+-----------
+Same.
+
+
+Registers Preserved Across Calls
+================================
+
+r8c, m16c
+---------
+sb, fb, sp (i.e. nearly all registers are call clobbered)
+
+m32cm, m32c
+-----------
+r1, r2, r3, a0, a1, sb, fb, sp
+(except when used for return values)
+
+
+Interrupt Handlers
+==================
+
+The stack frame is slightly different for interrupt handlers, because
+(1) we don't have a usable parent frame, and (2) we have to use
+special instructions to return and thus must save/restore everything
+differently.
+
+	+--------------------
+	| program state
+osp ->	+--------------------
+	| return address
+	+--------------------
+	| saved r0..fp (pushm)
+fp ->	+--------------------
+	| local data
+	+--------------------
+	| saved regs mem0..mem15
+	+--------------------
+	| outgoing args (opt)
+sp ->	+--------------------
+
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
new file mode 100644
index 000000000..9b4a5a95c
--- /dev/null
+++ b/gcc/config/m32c/m32c.c
@@ -0,0 +1,4860 @@
+/* Target Code for R8C/M16C/M32C
+   Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "reload.h"
+#include "diagnostic-core.h"
+#include "obstack.h"
+#include "tree.h"
+#include "expr.h"
+#include "optabs.h"
+#include "except.h"
+#include "function.h"
+#include "ggc.h"
+#include "target.h"
+#include "target-def.h"
+#include "tm_p.h"
+#include "langhooks.h"
+#include "gimple.h"
+#include "df.h"
+
+/* Prototypes */
+
+/* Used by m32c_pushm_popm.  */
+typedef enum
+{
+  PP_pushm,
+  PP_popm,
+  PP_justcount
+} Push_Pop_Type;
+
+static bool m32c_function_needs_enter (void);
+static tree interrupt_handler (tree *, tree, tree, int, bool *);
+static tree function_vector_handler (tree *, tree, tree, int, bool *);
+static int interrupt_p (tree node);
+static int bank_switch_p (tree node);
+static int fast_interrupt_p (tree node);
+static int interrupt_p (tree node);
+static bool m32c_asm_integer (rtx, unsigned int, int);
+static int m32c_comp_type_attributes (const_tree, const_tree);
+static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
+static struct machine_function *m32c_init_machine_status (void);
+static void m32c_insert_attributes (tree, tree *);
+static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
+static bool m32c_addr_space_legitimate_address_p (enum machine_mode, rtx, bool, addr_space_t);
+static rtx m32c_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
+			      const_tree, bool);
+static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
+				    const_tree, bool);
+static void m32c_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
+				       const_tree, bool);
+static unsigned int m32c_function_arg_boundary (enum machine_mode, const_tree);
+static int m32c_pushm_popm (Push_Pop_Type);
+static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
+static rtx m32c_struct_value_rtx (tree, int);
+static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
+static int need_to_save (int);
+static rtx m32c_function_value (const_tree, const_tree, bool);
+static rtx m32c_libcall_value (enum machine_mode, const_rtx);
+
+/* Returns true if an address is specified, else false.  */
+static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
+
+#define SYMBOL_FLAG_FUNCVEC_FUNCTION    (SYMBOL_FLAG_MACH_DEP << 0)
+
+#define streq(a,b) (strcmp ((a), (b)) == 0)
+
+/* Internal support routines */
+
+/* Debugging statements are tagged with DEBUG0 only so that they can
+   be easily enabled individually, by replacing the '0' with '1' as
+   needed.  */
+#define DEBUG0 0
+#define DEBUG1 1
+
+#if DEBUG0
+/* This is needed by some of the commented-out debug statements
+   below.  */
+static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
+#endif
+static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
+
+/* These are all to support encode_pattern().  */
+static char pattern[30], *patternp;
+static GTY(()) rtx patternr[30];
+#define RTX_IS(x) (streq (pattern, x))
+
+/* Some macros to simplify the logic throughout this file.  */
+#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
+#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
+
+#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
+#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
+
+static int
+far_addr_space_p (rtx x)
+{
+  if (GET_CODE (x) != MEM)
+    return 0;
+#if DEBUG0
+  fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
+  fprintf(stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
+#endif
+  return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;
+}
+
+/* We do most RTX matching by converting the RTX into a string, and
+   using string compares.  This vastly simplifies the logic in many of
+   the functions in this file.
+
+   On exit, pattern[] has the encoded string (use RTX_IS("...") to
+   compare it) and patternr[] has pointers to the nodes in the RTX
+   corresponding to each character in the encoded string.  The latter
+   is mostly used by print_operand().
+
+   Unrecognized patterns have '?' in them; this shows up when the
+   assembler complains about syntax errors.
+*/
+
+static void
+encode_pattern_1 (rtx x)
+{
+  int i;
+
+  if (patternp == pattern + sizeof (pattern) - 2)
+    {
+      patternp[-1] = '?';
+      return;
+    }
+
+  patternr[patternp - pattern] = x;
+
+  switch (GET_CODE (x))
+    {
+    case REG:
+      *patternp++ = 'r';
+      break;
+    case SUBREG:
+      if (GET_MODE_SIZE (GET_MODE (x)) !=
+	  GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
+	*patternp++ = 'S';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case MEM:
+      *patternp++ = 'm';
+    case CONST:
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case SIGN_EXTEND:
+      *patternp++ = '^';
+      *patternp++ = 'S';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case ZERO_EXTEND:
+      *patternp++ = '^';
+      *patternp++ = 'Z';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case PLUS:
+      *patternp++ = '+';
+      encode_pattern_1 (XEXP (x, 0));
+      encode_pattern_1 (XEXP (x, 1));
+      break;
+    case PRE_DEC:
+      *patternp++ = '>';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case POST_INC:
+      *patternp++ = '<';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case LO_SUM:
+      *patternp++ = 'L';
+      encode_pattern_1 (XEXP (x, 0));
+      encode_pattern_1 (XEXP (x, 1));
+      break;
+    case HIGH:
+      *patternp++ = 'H';
+      encode_pattern_1 (XEXP (x, 0));
+      break;
+    case SYMBOL_REF:
+      *patternp++ = 's';
+      break;
+    case LABEL_REF:
+      *patternp++ = 'l';
+      break;
+    case CODE_LABEL:
+      *patternp++ = 'c';
+      break;
+    case CONST_INT:
+    case CONST_DOUBLE:
+      *patternp++ = 'i';
+      break;
+    case UNSPEC:
+      *patternp++ = 'u';
+      *patternp++ = '0' + XCINT (x, 1, UNSPEC);
+      for (i = 0; i < XVECLEN (x, 0); i++)
+	encode_pattern_1 (XVECEXP (x, 0, i));
+      break;
+    case USE:
+      *patternp++ = 'U';
+      break;
+    case PARALLEL:
+      *patternp++ = '|';
+      for (i = 0; i < XVECLEN (x, 0); i++)
+	encode_pattern_1 (XVECEXP (x, 0, i));
+      break;
+    case EXPR_LIST:
+      *patternp++ = 'E';
+      encode_pattern_1 (XEXP (x, 0));
+      if (XEXP (x, 1))
+	encode_pattern_1 (XEXP (x, 1));
+      break;
+    default:
+      *patternp++ = '?';
+#if DEBUG0
+      fprintf (stderr, "can't encode pattern %s\n",
+	       GET_RTX_NAME (GET_CODE (x)));
+      debug_rtx (x);
+      gcc_unreachable ();
+#endif
+      break;
+    }
+}
+
+static void
+encode_pattern (rtx x)
+{
+  patternp = pattern;
+  encode_pattern_1 (x);
+  *patternp = 0;
+}
+
+/* Since register names indicate the mode they're used in, we need a
+   way to determine which name to refer to the register with.  Called
+   by print_operand().  */
+
+static const char *
+reg_name_with_mode (int regno, enum machine_mode mode)
+{
+  int mlen = GET_MODE_SIZE (mode);
+  if (regno == R0_REGNO && mlen == 1)
+    return "r0l";
+  if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
+    return "r2r0";
+  if (regno == R0_REGNO && mlen == 6)
+    return "r2r1r0";
+  if (regno == R0_REGNO && mlen == 8)
+    return "r3r1r2r0";
+  if (regno == R1_REGNO && mlen == 1)
+    return "r1l";
+  if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
+    return "r3r1";
+  if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
+    return "a1a0";
+  return reg_names[regno];
+}
+
+/* How many bytes a register uses on stack when it's pushed.  We need
+   to know this because the push opcode needs to explicitly indicate
+   the size of the register, even though the name of the register
+   already tells it that.  Used by m32c_output_reg_{push,pop}, which
+   is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}.  */
+
+static int
+reg_push_size (int regno)
+{
+  switch (regno)
+    {
+    case R0_REGNO:
+    case R1_REGNO:
+      return 2;
+    case R2_REGNO:
+    case R3_REGNO:
+    case FLG_REGNO:
+      return 2;
+    case A0_REGNO:
+    case A1_REGNO:
+    case SB_REGNO:
+    case FB_REGNO:
+    case SP_REGNO:
+      if (TARGET_A16)
+	return 2;
+      else
+	return 3;
+    default:
+      gcc_unreachable ();
+    }
+}
+
+static int *class_sizes = 0;
+
+/* Given two register classes, find the largest intersection between
+   them.  If there is no intersection, return RETURNED_IF_EMPTY
+   instead.  */
+static int
+reduce_class (int original_class, int limiting_class, int returned_if_empty)
+{
+  int cc = class_contents[original_class][0];
+  int i, best = NO_REGS;
+  int best_size = 0;
+
+  if (original_class == limiting_class)
+    return original_class;
+
+  if (!class_sizes)
+    {
+      int r;
+      class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
+      for (i = 0; i < LIM_REG_CLASSES; i++)
+	{
+	  class_sizes[i] = 0;
+	  for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+	    if (class_contents[i][0] & (1 << r))
+	      class_sizes[i]++;
+	}
+    }
+
+  cc &= class_contents[limiting_class][0];
+  for (i = 0; i < LIM_REG_CLASSES; i++)
+    {
+      int ic = class_contents[i][0];
+
+      if ((~cc & ic) == 0)
+	if (best_size < class_sizes[i])
+	  {
+	    best = i;
+	    best_size = class_sizes[i];
+	  }
+
+    }
+  if (best == NO_REGS)
+    return returned_if_empty;
+  return best;
+}
+
+/* Used by m32c_register_move_cost to determine if a move is
+   impossibly expensive.  */
+static bool
+class_can_hold_mode (reg_class_t rclass, enum machine_mode mode)
+{
+  /* Cache the results:  0=untested  1=no  2=yes */
+  static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
+
+  if (results[(int) rclass][mode] == 0)
+    {
+      int r;
+      results[rclass][mode] = 1;
+      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
+	if (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)
+	    && HARD_REGNO_MODE_OK (r, mode))
+	  {
+	    results[rclass][mode] = 2;
+	    break;
+	  }
+    }
+
+#if DEBUG0
+  fprintf (stderr, "class %s can hold %s? %s\n",
+	   class_names[(int) rclass], mode_name[mode],
+	   (results[rclass][mode] == 2) ? "yes" : "no");
+#endif
+  return results[(int) rclass][mode] == 2;
+}
+
+/* Run-time Target Specification.  */
+
+/* Memregs are memory locations that gcc treats like general
+   registers, as there are a limited number of true registers and the
+   m32c families can use memory in most places that registers can be
+   used.
+
+   However, since memory accesses are more expensive than registers,
+   we allow the user to limit the number of memregs available, in
+   order to try to persuade gcc to try harder to use real registers.
+
+   Memregs are provided by m32c-lib1.S.
+*/
+
+int target_memregs = 16;
+static bool target_memregs_set = FALSE;
+int ok_to_change_target_memregs = TRUE;
+
+#undef  TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION m32c_handle_option
+static bool
+m32c_handle_option (size_t code,
+		    const char *arg ATTRIBUTE_UNUSED,
+		    int value ATTRIBUTE_UNUSED)
+{
+  if (code == OPT_memregs_)
+    {
+      target_memregs_set = TRUE;
+      target_memregs = atoi (arg);
+    }
+  return TRUE;
+}
+
+/* Implements TARGET_OPTION_OVERRIDE.  */
+
+#undef TARGET_OPTION_OVERRIDE
+#define TARGET_OPTION_OVERRIDE m32c_option_override
+
+static void
+m32c_option_override (void)
+{
+  /* We limit memregs to 0..16, and provide a default.  */
+  if (target_memregs_set)
+    {
+      if (target_memregs < 0 || target_memregs > 16)
+	error ("invalid target memregs value '%d'", target_memregs);
+    }
+  else
+    target_memregs = 16;
+
+  if (TARGET_A24)
+    flag_ivopts = 0;
+
+  /* This target defaults to strict volatile bitfields.  */
+  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
+    flag_strict_volatile_bitfields = 1;
+
+  /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
+     This is always worse than an absolute call.  */
+  if (TARGET_A16)
+    flag_no_function_cse = 1;
+
+  /* This wants to put insns between compares and their jumps.  */
+  /* FIXME: The right solution is to properly trace the flags register
+     values, but that is too much work for stage 4.  */
+  flag_combine_stack_adjustments = 0;
+}
+
+#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
+#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
+
+static void
+m32c_override_options_after_change (void)
+{
+  if (TARGET_A16)
+    flag_no_function_cse = 1;
+}
+
+/* Defining data structures for per-function information */
+
+/* The usual; we set up our machine_function data.  */
+static struct machine_function *
+m32c_init_machine_status (void)
+{
+  return ggc_alloc_cleared_machine_function ();
+}
+
+/* Implements INIT_EXPANDERS.  We just set up to call the above
+   function.  */
+void
+m32c_init_expanders (void)
+{
+  init_machine_status = m32c_init_machine_status;
+}
+
+/* Storage Layout */
+
+/* Register Basics */
+
+/* Basic Characteristics of Registers */
+
+/* Whether a mode fits in a register is complex enough to warrant a
+   table.  */
+static struct
+{
+  char qi_regs;
+  char hi_regs;
+  char pi_regs;
+  char si_regs;
+  char di_regs;
+} nregs_table[FIRST_PSEUDO_REGISTER] =
+{
+  { 1, 1, 2, 2, 4 },		/* r0 */
+  { 0, 1, 0, 0, 0 },		/* r2 */
+  { 1, 1, 2, 2, 0 },		/* r1 */
+  { 0, 1, 0, 0, 0 },		/* r3 */
+  { 0, 1, 1, 0, 0 },		/* a0 */
+  { 0, 1, 1, 0, 0 },		/* a1 */
+  { 0, 1, 1, 0, 0 },		/* sb */
+  { 0, 1, 1, 0, 0 },		/* fb */
+  { 0, 1, 1, 0, 0 },		/* sp */
+  { 1, 1, 1, 0, 0 },		/* pc */
+  { 0, 0, 0, 0, 0 },		/* fl */
+  { 1, 1, 1, 0, 0 },		/* ap */
+  { 1, 1, 2, 2, 4 },		/* mem0 */
+  { 1, 1, 2, 2, 4 },		/* mem1 */
+  { 1, 1, 2, 2, 4 },		/* mem2 */
+  { 1, 1, 2, 2, 4 },		/* mem3 */
+  { 1, 1, 2, 2, 4 },		/* mem4 */
+  { 1, 1, 2, 2, 0 },		/* mem5 */
+  { 1, 1, 2, 2, 0 },		/* mem6 */
+  { 1, 1, 0, 0, 0 },		/* mem7 */
+};
+
+/* Implements TARGET_CONDITIONAL_REGISTER_USAGE.  We adjust the number
+   of available memregs, and select which registers need to be preserved
+   across calls based on the chip family.  */
+
+#undef TARGET_CONDITIONAL_REGISTER_USAGE
+#define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
+void
+m32c_conditional_register_usage (void)
+{
+  int i;
+
+  if (0 <= target_memregs && target_memregs <= 16)
+    {
+      /* The command line option is bytes, but our "registers" are
+	 16-bit words.  */
+      for (i = (target_memregs+1)/2; i < 8; i++)
+	{
+	  fixed_regs[MEM0_REGNO + i] = 1;
+	  CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
+	}
+    }
+
+  /* M32CM and M32C preserve more registers across function calls.  */
+  if (TARGET_A24)
+    {
+      call_used_regs[R1_REGNO] = 0;
+      call_used_regs[R2_REGNO] = 0;
+      call_used_regs[R3_REGNO] = 0;
+      call_used_regs[A0_REGNO] = 0;
+      call_used_regs[A1_REGNO] = 0;
+    }
+}
+
+/* How Values Fit in Registers */
+
+/* Implements HARD_REGNO_NREGS.  This is complicated by the fact that
+   different registers are different sizes from each other, *and* may
+   be different sizes in different chip families.  */
+static int
+m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
+{
+  if (regno == FLG_REGNO && mode == CCmode)
+    return 1;
+  if (regno >= FIRST_PSEUDO_REGISTER)
+    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
+
+  if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
+    return (GET_MODE_SIZE (mode) + 1) / 2;
+
+  if (GET_MODE_SIZE (mode) <= 1)
+    return nregs_table[regno].qi_regs;
+  if (GET_MODE_SIZE (mode) <= 2)
+    return nregs_table[regno].hi_regs;
+  if (regno == A0_REGNO && mode == SImode && TARGET_A16)
+    return 2;
+  if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
+    return nregs_table[regno].pi_regs;
+  if (GET_MODE_SIZE (mode) <= 4)
+    return nregs_table[regno].si_regs;
+  if (GET_MODE_SIZE (mode) <= 8)
+    return nregs_table[regno].di_regs;
+  return 0;
+}
+
+int
+m32c_hard_regno_nregs (int regno, enum machine_mode mode)
+{
+  int rv = m32c_hard_regno_nregs_1 (regno, mode);
+  return rv ? rv : 1;
+}
+
+/* Implements HARD_REGNO_MODE_OK.  The above function does the work
+   already; just test its return value.  */
+int
+m32c_hard_regno_ok (int regno, enum machine_mode mode)
+{
+  return m32c_hard_regno_nregs_1 (regno, mode) != 0;
+}
+
+/* Implements MODES_TIEABLE_P.  In general, modes aren't tieable since
+   registers are all different sizes.  However, since most modes are
+   bigger than our registers anyway, it's easier to implement this
+   function that way, leaving QImode as the only unique case.  */
+int
+m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
+{
+  if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
+    return 1;
+
+#if 0
+  if (m1 == QImode || m2 == QImode)
+    return 0;
+#endif
+
+  return 1;
+}
+
+/* Register Classes */
+
+/* Implements REGNO_REG_CLASS.  */
+enum reg_class
+m32c_regno_reg_class (int regno)
+{
+  switch (regno)
+    {
+    case R0_REGNO:
+      return R0_REGS;
+    case R1_REGNO:
+      return R1_REGS;
+    case R2_REGNO:
+      return R2_REGS;
+    case R3_REGNO:
+      return R3_REGS;
+    case A0_REGNO:
+      return A0_REGS;
+    case A1_REGNO:
+      return A1_REGS;
+    case SB_REGNO:
+      return SB_REGS;
+    case FB_REGNO:
+      return FB_REGS;
+    case SP_REGNO:
+      return SP_REGS;
+    case FLG_REGNO:
+      return FLG_REGS;
+    default:
+      if (IS_MEM_REGNO (regno))
+	return MEM_REGS;
+      return ALL_REGS;
+    }
+}
+
+/* Implements REG_CLASS_FROM_CONSTRAINT.  Note that some constraints only match
+   for certain chip families.  */
+int
+m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
+{
+  if (memcmp (s, "Rsp", 3) == 0)
+    return SP_REGS;
+  if (memcmp (s, "Rfb", 3) == 0)
+    return FB_REGS;
+  if (memcmp (s, "Rsb", 3) == 0)
+    return SB_REGS;
+  if (memcmp (s, "Rcr", 3) == 0)
+    return TARGET_A16 ? CR_REGS : NO_REGS;
+  if (memcmp (s, "Rcl", 3) == 0)
+    return TARGET_A24 ? CR_REGS : NO_REGS;
+  if (memcmp (s, "R0w", 3) == 0)
+    return R0_REGS;
+  if (memcmp (s, "R1w", 3) == 0)
+    return R1_REGS;
+  if (memcmp (s, "R2w", 3) == 0)
+    return R2_REGS;
+  if (memcmp (s, "R3w", 3) == 0)
+    return R3_REGS;
+  if (memcmp (s, "R02", 3) == 0)
+    return R02_REGS;
+  if (memcmp (s, "R13", 3) == 0)
+    return R13_REGS;
+  if (memcmp (s, "R03", 3) == 0)
+    return R03_REGS;
+  if (memcmp (s, "Rdi", 3) == 0)
+    return DI_REGS;
+  if (memcmp (s, "Rhl", 3) == 0)
+    return HL_REGS;
+  if (memcmp (s, "R23", 3) == 0)
+    return R23_REGS;
+  if (memcmp (s, "Ra0", 3) == 0)
+    return A0_REGS;
+  if (memcmp (s, "Ra1", 3) == 0)
+    return A1_REGS;
+  if (memcmp (s, "Raa", 3) == 0)
+    return A_REGS;
+  if (memcmp (s, "Raw", 3) == 0)
+    return TARGET_A16 ? A_REGS : NO_REGS;
+  if (memcmp (s, "Ral", 3) == 0)
+    return TARGET_A24 ? A_REGS : NO_REGS;
+  if (memcmp (s, "Rqi", 3) == 0)
+    return QI_REGS;
+  if (memcmp (s, "Rad", 3) == 0)
+    return AD_REGS;
+  if (memcmp (s, "Rsi", 3) == 0)
+    return SI_REGS;
+  if (memcmp (s, "Rhi", 3) == 0)
+    return HI_REGS;
+  if (memcmp (s, "Rhc", 3) == 0)
+    return HC_REGS;
+  if (memcmp (s, "Rra", 3) == 0)
+    return RA_REGS;
+  if (memcmp (s, "Rfl", 3) == 0)
+    return FLG_REGS;
+  if (memcmp (s, "Rmm", 3) == 0)
+    {
+      if (fixed_regs[MEM0_REGNO])
+	return NO_REGS;
+      return MEM_REGS;
+    }
+
+  /* PSImode registers - i.e. whatever can hold a pointer.  */
+  if (memcmp (s, "Rpi", 3) == 0)
+    {
+      if (TARGET_A16)
+	return HI_REGS;
+      else
+	return RA_REGS; /* r2r0 and r3r1 can hold pointers.  */
+    }
+
+  /* We handle this one as an EXTRA_CONSTRAINT.  */
+  if (memcmp (s, "Rpa", 3) == 0)
+    return NO_REGS;
+
+  if (*s == 'R')
+    {
+      fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
+      gcc_unreachable();
+    }
+
+  return NO_REGS;
+}
+
+/* Implements REGNO_OK_FOR_BASE_P.  */
+int
+m32c_regno_ok_for_base_p (int regno)
+{
+  if (regno == A0_REGNO
+      || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
+    return 1;
+  return 0;
+}
+
+#define DEBUG_RELOAD 0
+
+/* Implements PREFERRED_RELOAD_CLASS.  In general, prefer general
+   registers of the appropriate size.  */
+int
+m32c_preferred_reload_class (rtx x, int rclass)
+{
+  int newclass = rclass;
+
+#if DEBUG_RELOAD
+  fprintf (stderr, "\npreferred_reload_class for %s is ",
+	   class_names[rclass]);
+#endif
+  if (rclass == NO_REGS)
+    rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
+
+  if (reg_classes_intersect_p (rclass, CR_REGS))
+    {
+      switch (GET_MODE (x))
+	{
+	case QImode:
+	  newclass = HL_REGS;
+	  break;
+	default:
+	  /*      newclass = HI_REGS; */
+	  break;
+	}
+    }
+
+  else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
+    newclass = SI_REGS;
+  else if (GET_MODE_SIZE (GET_MODE (x)) > 4
+	   && ~class_contents[rclass][0] & 0x000f)
+    newclass = DI_REGS;
+
+  rclass = reduce_class (rclass, newclass, rclass);
+
+  if (GET_MODE (x) == QImode)
+    rclass = reduce_class (rclass, HL_REGS, rclass);
+
+#if DEBUG_RELOAD
+  fprintf (stderr, "%s\n", class_names[rclass]);
+  debug_rtx (x);
+
+  if (GET_CODE (x) == MEM
+      && GET_CODE (XEXP (x, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
+    fprintf (stderr, "Glorm!\n");
+#endif
+  return rclass;
+}
+
+/* Implements PREFERRED_OUTPUT_RELOAD_CLASS.  */
+int
+m32c_preferred_output_reload_class (rtx x, int rclass)
+{
+  return m32c_preferred_reload_class (x, rclass);
+}
+
+/* Implements LIMIT_RELOAD_CLASS.  We basically want to avoid using
+   address registers for reloads since they're needed for address
+   reloads.  */
+int
+m32c_limit_reload_class (enum machine_mode mode, int rclass)
+{
+#if DEBUG_RELOAD
+  fprintf (stderr, "limit_reload_class for %s: %s ->",
+	   mode_name[mode], class_names[rclass]);
+#endif
+
+  if (mode == QImode)
+    rclass = reduce_class (rclass, HL_REGS, rclass);
+  else if (mode == HImode)
+    rclass = reduce_class (rclass, HI_REGS, rclass);
+  else if (mode == SImode)
+    rclass = reduce_class (rclass, SI_REGS, rclass);
+
+  if (rclass != A_REGS)
+    rclass = reduce_class (rclass, DI_REGS, rclass);
+
+#if DEBUG_RELOAD
+  fprintf (stderr, " %s\n", class_names[rclass]);
+#endif
+  return rclass;
+}
+
+/* Implements SECONDARY_RELOAD_CLASS.  QImode have to be reloaded in
+   r0 or r1, as those are the only real QImode registers.  CR regs get
+   reloaded through appropriately sized general or address
+   registers.  */
+int
+m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
+{
+  int cc = class_contents[rclass][0];
+#if DEBUG0
+  fprintf (stderr, "\nsecondary reload class %s %s\n",
+	   class_names[rclass], mode_name[mode]);
+  debug_rtx (x);
+#endif
+  if (mode == QImode
+      && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
+    return QI_REGS;
+  if (reg_classes_intersect_p (rclass, CR_REGS)
+      && GET_CODE (x) == REG
+      && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
+    return TARGET_A16 ? HI_REGS : A_REGS;
+  return NO_REGS;
+}
+
+/* Implements TARGET_CLASS_LIKELY_SPILLED_P.  A_REGS is needed for address
+   reloads.  */
+
+#undef TARGET_CLASS_LIKELY_SPILLED_P
+#define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
+
+static bool
+m32c_class_likely_spilled_p (reg_class_t regclass)
+{
+  if (regclass == A_REGS)
+    return true;
+
+  return (reg_class_size[(int) regclass] == 1);
+}
+
+/* Implements CLASS_MAX_NREGS.  We calculate this according to its
+   documented meaning, to avoid potential inconsistencies with actual
+   class definitions.  */
+int
+m32c_class_max_nregs (int regclass, enum machine_mode mode)
+{
+  int rn, max = 0;
+
+  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
+    if (class_contents[regclass][0] & (1 << rn))
+      {
+	int n = m32c_hard_regno_nregs (rn, mode);
+	if (max < n)
+	  max = n;
+      }
+  return max;
+}
+
+/* Implements CANNOT_CHANGE_MODE_CLASS.  Only r0 and r1 can change to
+   QI (r0l, r1l) because the chip doesn't support QI ops on other
+   registers (well, it does on a0/a1 but if we let gcc do that, reload
+   suffers).  Otherwise, we allow changes to larger modes.  */
+int
+m32c_cannot_change_mode_class (enum machine_mode from,
+			       enum machine_mode to, int rclass)
+{
+  int rn;
+#if DEBUG0
+  fprintf (stderr, "cannot change from %s to %s in %s\n",
+	   mode_name[from], mode_name[to], class_names[rclass]);
+#endif
+
+  /* If the larger mode isn't allowed in any of these registers, we
+     can't allow the change.  */
+  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
+    if (class_contents[rclass][0] & (1 << rn))
+      if (! m32c_hard_regno_ok (rn, to))
+	return 1;
+
+  if (to == QImode)
+    return (class_contents[rclass][0] & 0x1ffa);
+
+  if (class_contents[rclass][0] & 0x0005	/* r0, r1 */
+      && GET_MODE_SIZE (from) > 1)
+    return 0;
+  if (GET_MODE_SIZE (from) > 2)	/* all other regs */
+    return 0;
+
+  return 1;
+}
+
+/* Helpers for the rest of the file.  */
+/* TRUE if the rtx is a REG rtx for the given register.  */
+#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
+			   && REGNO (rtx) == regno)
+/* TRUE if the rtx is a pseudo - specifically, one we can use as a
+   base register in address calculations (hence the "strict"
+   argument).  */
+#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
+			       && (REGNO (rtx) == AP_REGNO \
+				   || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
+
+/* Implements CONST_OK_FOR_CONSTRAINT_P.  Currently, all constant
+   constraints start with 'I', with the next two characters indicating
+   the type and size of the range allowed.  */
+int
+m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
+				char c ATTRIBUTE_UNUSED, const char *str)
+{
+  /* s=signed u=unsigned n=nonzero m=minus l=log2able,
+     [sun] bits [SUN] bytes, p=pointer size
+     I[-0-9][0-9] matches that number */
+  if (memcmp (str, "Is3", 3) == 0)
+    {
+      return (-8 <= value && value <= 7);
+    }
+  if (memcmp (str, "IS1", 3) == 0)
+    {
+      return (-128 <= value && value <= 127);
+    }
+  if (memcmp (str, "IS2", 3) == 0)
+    {
+      return (-32768 <= value && value <= 32767);
+    }
+  if (memcmp (str, "IU2", 3) == 0)
+    {
+      return (0 <= value && value <= 65535);
+    }
+  if (memcmp (str, "IU3", 3) == 0)
+    {
+      return (0 <= value && value <= 0x00ffffff);
+    }
+  if (memcmp (str, "In4", 3) == 0)
+    {
+      return (-8 <= value && value && value <= 8);
+    }
+  if (memcmp (str, "In5", 3) == 0)
+    {
+      return (-16 <= value && value && value <= 16);
+    }
+  if (memcmp (str, "In6", 3) == 0)
+    {
+      return (-32 <= value && value && value <= 32);
+    }
+  if (memcmp (str, "IM2", 3) == 0)
+    {
+      return (-65536 <= value && value && value <= -1);
+    }
+  if (memcmp (str, "Ilb", 3) == 0)
+    {
+      int b = exact_log2 (value);
+      return (b >= 0 && b <= 7);
+    }
+  if (memcmp (str, "Imb", 3) == 0)
+    {
+      int b = exact_log2 ((value ^ 0xff) & 0xff);
+      return (b >= 0 && b <= 7);
+    }
+  if (memcmp (str, "ImB", 3) == 0)
+    {
+      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
+      return (b >= 0 && b <= 7);
+    }
+  if (memcmp (str, "Ilw", 3) == 0)
+    {
+      int b = exact_log2 (value);
+      return (b >= 0 && b <= 15);
+    }
+  if (memcmp (str, "Imw", 3) == 0)
+    {
+      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
+      return (b >= 0 && b <= 15);
+    }
+  if (memcmp (str, "I00", 3) == 0)
+    {
+      return (value == 0);
+    }
+  return 0;
+}
+
+#define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
+
+/* Implements EXTRA_CONSTRAINT_STR (see next function too).  'S' is
+   for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
+   call return values.  */
+int
+m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
+{
+  encode_pattern (value);
+
+  if (far_addr_space_p (value))
+    {
+      if (memcmp (str, "SF", 2) == 0)
+	{
+	  return (   (RTX_IS ("mr")
+		      && A0_OR_PSEUDO (patternr[1])
+		      && GET_MODE (patternr[1]) == SImode)
+		     || (RTX_IS ("m+^Sri")
+			 && A0_OR_PSEUDO (patternr[4])
+			 && GET_MODE (patternr[4]) == HImode)
+		     || (RTX_IS ("m+^Srs")
+			 && A0_OR_PSEUDO (patternr[4])
+			 && GET_MODE (patternr[4]) == HImode)
+		     || (RTX_IS ("m+^S+ris")
+			 && A0_OR_PSEUDO (patternr[5])
+			 && GET_MODE (patternr[5]) == HImode)
+		     || RTX_IS ("ms")
+		     );
+	}
+      return 0;
+    }
+
+  if (memcmp (str, "Sd", 2) == 0)
+    {
+      /* This is the common "src/dest" address */
+      rtx r;
+      if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
+	return 1;
+      if (RTX_IS ("ms") || RTX_IS ("m+si"))
+	return 1;
+      if (RTX_IS ("m++rii"))
+	{
+	  if (REGNO (patternr[3]) == FB_REGNO
+	      && INTVAL (patternr[4]) == 0)
+	    return 1;
+	}
+      if (RTX_IS ("mr"))
+	r = patternr[1];
+      else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
+	r = patternr[2];
+      else
+	return 0;
+      if (REGNO (r) == SP_REGNO)
+	return 0;
+      return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
+    }
+  else if (memcmp (str, "Sa", 2) == 0)
+    {
+      rtx r;
+      if (RTX_IS ("mr"))
+	r = patternr[1];
+      else if (RTX_IS ("m+ri"))
+	r = patternr[2];
+      else
+	return 0;
+      return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
+    }
+  else if (memcmp (str, "Si", 2) == 0)
+    {
+      return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
+    }
+  else if (memcmp (str, "Ss", 2) == 0)
+    {
+      return ((RTX_IS ("mr")
+	       && (IS_REG (patternr[1], SP_REGNO)))
+	      || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
+    }
+  else if (memcmp (str, "Sf", 2) == 0)
+    {
+      return ((RTX_IS ("mr")
+	       && (IS_REG (patternr[1], FB_REGNO)))
+	      || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
+    }
+  else if (memcmp (str, "Sb", 2) == 0)
+    {
+      return ((RTX_IS ("mr")
+	       && (IS_REG (patternr[1], SB_REGNO)))
+	      || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
+    }
+  else if (memcmp (str, "Sp", 2) == 0)
+    {
+      /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
+      return (RTX_IS ("mi")
+	      && !(INTVAL (patternr[1]) & ~0x1fff));
+    }
+  else if (memcmp (str, "S1", 2) == 0)
+    {
+      return r1h_operand (value, QImode);
+    }
+  else if (memcmp (str, "SF", 2) == 0)
+    {
+      return 0;
+    }
+
+  gcc_assert (str[0] != 'S');
+
+  if (memcmp (str, "Rpa", 2) == 0)
+    return GET_CODE (value) == PARALLEL;
+
+  return 0;
+}
+
+/* This is for when we're debugging the above.  */
+int
+m32c_extra_constraint_p (rtx value, char c, const char *str)
+{
+  int rv = m32c_extra_constraint_p2 (value, c, str);
+#if DEBUG0
+  fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
+	   rv);
+  debug_rtx (value);
+#endif
+  return rv;
+}
+
+/* Implements EXTRA_MEMORY_CONSTRAINT.  Currently, we only use strings
+   starting with 'S'.  */
+int
+m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
+{
+  return c == 'S';
+}
+
+/* Implements EXTRA_ADDRESS_CONSTRAINT.  We reserve 'A' strings for these,
+   but don't currently define any.  */
+int
+m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
+{
+  return c == 'A';
+}
+
+/* STACK AND CALLING */
+
+/* Frame Layout */
+
+/* Implements RETURN_ADDR_RTX.  Note that R8C and M16C push 24 bits
+   (yes, THREE bytes) onto the stack for the return address, but we
+   don't support pointers bigger than 16 bits on those chips.  This
+   will likely wreak havoc with exception unwinding.  FIXME.  */
+rtx
+m32c_return_addr_rtx (int count)
+{
+  enum machine_mode mode;
+  int offset;
+  rtx ra_mem;
+
+  if (count)
+    return NULL_RTX;
+  /* we want 2[$fb] */
+
+  if (TARGET_A24)
+    {
+      /* It's four bytes */
+      mode = PSImode;
+      offset = 4;
+    }
+  else
+    {
+      /* FIXME: it's really 3 bytes */
+      mode = HImode;
+      offset = 2;
+    }
+
+  ra_mem =
+    gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
+  return copy_to_mode_reg (mode, ra_mem);
+}
+
+/* Implements INCOMING_RETURN_ADDR_RTX.  See comment above.  */
+rtx
+m32c_incoming_return_addr_rtx (void)
+{
+  /* we want [sp] */
+  return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
+}
+
+/* Exception Handling Support */
+
+/* Implements EH_RETURN_DATA_REGNO.  Choose registers able to hold
+   pointers.  */
+int
+m32c_eh_return_data_regno (int n)
+{
+  switch (n)
+    {
+    case 0:
+      return A0_REGNO;
+    case 1:
+      if (TARGET_A16)
+	return R3_REGNO;
+      else
+	return R1_REGNO;
+    default:
+      return INVALID_REGNUM;
+    }
+}
+
+/* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in
+   m32c_emit_eh_epilogue.  */
+rtx
+m32c_eh_return_stackadj_rtx (void)
+{
+  if (!cfun->machine->eh_stack_adjust)
+    {
+      rtx sa;
+
+      sa = gen_rtx_REG (Pmode, R0_REGNO);
+      cfun->machine->eh_stack_adjust = sa;
+    }
+  return cfun->machine->eh_stack_adjust;
+}
+
+/* Registers That Address the Stack Frame */
+
+/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER.  Note that
+   the original spec called for dwarf numbers to vary with register
+   width as well, for example, r0l, r0, and r2r0 would each have
+   different dwarf numbers.  GCC doesn't support this, and we don't do
+   it, and gdb seems to like it this way anyway.  */
+unsigned int
+m32c_dwarf_frame_regnum (int n)
+{
+  switch (n)
+    {
+    case R0_REGNO:
+      return 5;
+    case R1_REGNO:
+      return 6;
+    case R2_REGNO:
+      return 7;
+    case R3_REGNO:
+      return 8;
+    case A0_REGNO:
+      return 9;
+    case A1_REGNO:
+      return 10;
+    case FB_REGNO:
+      return 11;
+    case SB_REGNO:
+      return 19;
+
+    case SP_REGNO:
+      return 12;
+    case PC_REGNO:
+      return 13;
+    default:
+      return DWARF_FRAME_REGISTERS + 1;
+    }
+}
+
+/* The frame looks like this:
+
+   ap -> +------------------------------
+         | Return address (3 or 4 bytes)
+	 | Saved FB (2 or 4 bytes)
+   fb -> +------------------------------
+	 | local vars
+         | register saves fb
+	 |        through r0 as needed
+   sp -> +------------------------------
+*/
+
+/* We use this to wrap all emitted insns in the prologue.  */
+static rtx
+F (rtx x)
+{
+  RTX_FRAME_RELATED_P (x) = 1;
+  return x;
+}
+
+/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
+   how much the stack pointer moves for each, for each cpu family.  */
+static struct
+{
+  int reg1;
+  int bit;
+  int a16_bytes;
+  int a24_bytes;
+} pushm_info[] =
+{
+  /* These are in reverse push (nearest-to-sp) order.  */
+  { R0_REGNO, 0x80, 2, 2 },
+  { R1_REGNO, 0x40, 2, 2 },
+  { R2_REGNO, 0x20, 2, 2 },
+  { R3_REGNO, 0x10, 2, 2 },
+  { A0_REGNO, 0x08, 2, 4 },
+  { A1_REGNO, 0x04, 2, 4 },
+  { SB_REGNO, 0x02, 2, 4 },
+  { FB_REGNO, 0x01, 2, 4 }
+};
+
+#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
+
+/* Returns TRUE if we need to save/restore the given register.  We
+   save everything for exception handlers, so that any register can be
+   unwound.  For interrupt handlers, we save everything if the handler
+   calls something else (because we don't know what *that* function
+   might do), but try to be a bit smarter if the handler is a leaf
+   function.  We always save $a0, though, because we use that in the
+   epilogue to copy $fb to $sp.  */
+static int
+need_to_save (int regno)
+{
+  if (fixed_regs[regno])
+    return 0;
+  if (crtl->calls_eh_return)
+    return 1;
+  if (regno == FP_REGNO)
+    return 0;
+  if (cfun->machine->is_interrupt
+      && (!cfun->machine->is_leaf
+	  || (regno == A0_REGNO
+	      && m32c_function_needs_enter ())
+	  ))
+    return 1;
+  if (df_regs_ever_live_p (regno)
+      && (!call_used_regs[regno] || cfun->machine->is_interrupt))
+    return 1;
+  return 0;
+}
+
+/* This function contains all the intelligence about saving and
+   restoring registers.  It always figures out the register save set.
+   When called with PP_justcount, it merely returns the size of the
+   save set (for eliminating the frame pointer, for example).  When
+   called with PP_pushm or PP_popm, it emits the appropriate
+   instructions for saving (pushm) or restoring (popm) the
+   registers.  */
+static int
+m32c_pushm_popm (Push_Pop_Type ppt)
+{
+  int reg_mask = 0;
+  int byte_count = 0, bytes;
+  int i;
+  rtx dwarf_set[PUSHM_N];
+  int n_dwarfs = 0;
+  int nosave_mask = 0;
+
+  if (crtl->return_rtx
+      && GET_CODE (crtl->return_rtx) == PARALLEL
+      && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
+    {
+      rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
+      rtx rv = XEXP (exp, 0);
+      int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
+
+      if (rv_bytes > 2)
+	nosave_mask |= 0x20;	/* PSI, SI */
+      else
+	nosave_mask |= 0xf0;	/* DF */
+      if (rv_bytes > 4)
+	nosave_mask |= 0x50;	/* DI */
+    }
+
+  for (i = 0; i < (int) PUSHM_N; i++)
+    {
+      /* Skip if neither register needs saving.  */
+      if (!need_to_save (pushm_info[i].reg1))
+	continue;
+
+      if (pushm_info[i].bit & nosave_mask)
+	continue;
+
+      reg_mask |= pushm_info[i].bit;
+      bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
+
+      if (ppt == PP_pushm)
+	{
+	  enum machine_mode mode = (bytes == 2) ? HImode : SImode;
+	  rtx addr;
+
+	  /* Always use stack_pointer_rtx instead of calling
+	     rtx_gen_REG ourselves.  Code elsewhere in GCC assumes
+	     that there is a single rtx representing the stack pointer,
+	     namely stack_pointer_rtx, and uses == to recognize it.  */
+	  addr = stack_pointer_rtx;
+
+	  if (byte_count != 0)
+	    addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
+
+	  dwarf_set[n_dwarfs++] =
+	    gen_rtx_SET (VOIDmode,
+			 gen_rtx_MEM (mode, addr),
+			 gen_rtx_REG (mode, pushm_info[i].reg1));
+	  F (dwarf_set[n_dwarfs - 1]);
+
+	}
+      byte_count += bytes;
+    }
+
+  if (cfun->machine->is_interrupt)
+    {
+      cfun->machine->intr_pushm = reg_mask & 0xfe;
+      reg_mask = 0;
+      byte_count = 0;
+    }
+
+  if (cfun->machine->is_interrupt)
+    for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
+      if (need_to_save (i))
+	{
+	  byte_count += 2;
+	  cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
+	}
+
+  if (ppt == PP_pushm && byte_count)
+    {
+      rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
+      rtx pushm;
+
+      if (reg_mask)
+	{
+	  XVECEXP (note, 0, 0)
+	    = gen_rtx_SET (VOIDmode,
+			   stack_pointer_rtx,
+			   gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
+					 stack_pointer_rtx,
+					 GEN_INT (-byte_count)));
+	  F (XVECEXP (note, 0, 0));
+
+	  for (i = 0; i < n_dwarfs; i++)
+	    XVECEXP (note, 0, i + 1) = dwarf_set[i];
+
+	  pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
+
+	  add_reg_note (pushm, REG_FRAME_RELATED_EXPR, note);
+	}
+
+      if (cfun->machine->is_interrupt)
+	for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
+	  if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
+	    {
+	      if (TARGET_A16)
+		pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
+	      else
+		pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
+	      F (pushm);
+	    }
+    }
+  if (ppt == PP_popm && byte_count)
+    {
+      if (cfun->machine->is_interrupt)
+	for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
+	  if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
+	    {
+	      if (TARGET_A16)
+		emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
+	      else
+		emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
+	    }
+      if (reg_mask)
+	emit_insn (gen_popm (GEN_INT (reg_mask)));
+    }
+
+  return byte_count;
+}
+
+/* Implements INITIAL_ELIMINATION_OFFSET.  See the comment above that
+   diagrams our call frame.  */
+int
+m32c_initial_elimination_offset (int from, int to)
+{
+  int ofs = 0;
+
+  if (from == AP_REGNO)
+    {
+      if (TARGET_A16)
+	ofs += 5;
+      else
+	ofs += 8;
+    }
+
+  if (to == SP_REGNO)
+    {
+      ofs += m32c_pushm_popm (PP_justcount);
+      ofs += get_frame_size ();
+    }
+
+  /* Account for push rounding.  */
+  if (TARGET_A24)
+    ofs = (ofs + 1) & ~1;
+#if DEBUG0
+  fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
+	   to, ofs);
+#endif
+  return ofs;
+}
+
+/* Passing Function Arguments on the Stack */
+
+/* Implements PUSH_ROUNDING.  The R8C and M16C have byte stacks, the
+   M32C has word stacks.  */
+unsigned int
+m32c_push_rounding (int n)
+{
+  if (TARGET_R8C || TARGET_M16C)
+    return n;
+  return (n + 1) & ~1;
+}
+
+/* Passing Arguments in Registers */
+
+/* Implements TARGET_FUNCTION_ARG.  Arguments are passed partly in
+   registers, partly on stack.  If our function returns a struct, a
+   pointer to a buffer for it is at the top of the stack (last thing
+   pushed).  The first few real arguments may be in registers as
+   follows:
+
+   R8C/M16C:	arg1 in r1 if it's QI or HI (else it's pushed on stack)
+		arg2 in r2 if it's HI (else pushed on stack)
+		rest on stack
+   M32C:        arg1 in r0 if it's QI or HI (else it's pushed on stack)
+		rest on stack
+
+   Structs are not passed in registers, even if they fit.  Only
+   integer and pointer types are passed in registers.
+
+   Note that when arg1 doesn't fit in r1, arg2 may still be passed in
+   r2 if it fits.  */
+#undef TARGET_FUNCTION_ARG
+#define TARGET_FUNCTION_ARG m32c_function_arg
+static rtx
+m32c_function_arg (CUMULATIVE_ARGS * ca,
+		   enum machine_mode mode, const_tree type, bool named)
+{
+  /* Can return a reg, parallel, or 0 for stack */
+  rtx rv = NULL_RTX;
+#if DEBUG0
+  fprintf (stderr, "func_arg %d (%s, %d)\n",
+	   ca->parm_num, mode_name[mode], named);
+  debug_tree (type);
+#endif
+
+  if (mode == VOIDmode)
+    return GEN_INT (0);
+
+  if (ca->force_mem || !named)
+    {
+#if DEBUG0
+      fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
+	       named);
+#endif
+      return NULL_RTX;
+    }
+
+  if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
+    return NULL_RTX;
+
+  if (type && AGGREGATE_TYPE_P (type))
+    return NULL_RTX;
+
+  switch (ca->parm_num)
+    {
+    case 1:
+      if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
+	rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
+      break;
+
+    case 2:
+      if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
+	rv = gen_rtx_REG (mode, R2_REGNO);
+      break;
+    }
+
+#if DEBUG0
+  debug_rtx (rv);
+#endif
+  return rv;
+}
+
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
+static bool
+m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
+			enum machine_mode mode ATTRIBUTE_UNUSED,
+			const_tree type ATTRIBUTE_UNUSED,
+			bool named ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Implements INIT_CUMULATIVE_ARGS.  */
+void
+m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
+			   tree fntype,
+			   rtx libname ATTRIBUTE_UNUSED,
+			   tree fndecl,
+			   int n_named_args ATTRIBUTE_UNUSED)
+{
+  if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
+    ca->force_mem = 1;
+  else
+    ca->force_mem = 0;
+  ca->parm_num = 1;
+}
+
+/* Implements TARGET_FUNCTION_ARG_ADVANCE.  force_mem is set for
+   functions returning structures, so we always reset that.  Otherwise,
+   we only need to know the sequence number of the argument to know what
+   to do with it.  */
+#undef TARGET_FUNCTION_ARG_ADVANCE
+#define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
+static void
+m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
+			   enum machine_mode mode ATTRIBUTE_UNUSED,
+			   const_tree type ATTRIBUTE_UNUSED,
+			   bool named ATTRIBUTE_UNUSED)
+{
+  if (ca->force_mem)
+    ca->force_mem = 0;
+  else
+    ca->parm_num++;
+}
+
+/* Implements TARGET_FUNCTION_ARG_BOUNDARY.  */
+#undef TARGET_FUNCTION_ARG_BOUNDARY
+#define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
+static unsigned int
+m32c_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
+			    const_tree type ATTRIBUTE_UNUSED)
+{
+  return (TARGET_A16 ? 8 : 16);
+}
+
+/* Implements FUNCTION_ARG_REGNO_P.  */
+int
+m32c_function_arg_regno_p (int r)
+{
+  if (TARGET_A24)
+    return (r == R0_REGNO);
+  return (r == R1_REGNO || r == R2_REGNO);
+}
+
+/* HImode and PSImode are the two "native" modes as far as GCC is
+   concerned, but the chips also support a 32-bit mode which is used
+   for some opcodes in R8C/M16C and for reset vectors and such.  */
+#undef TARGET_VALID_POINTER_MODE
+#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
+static bool
+m32c_valid_pointer_mode (enum machine_mode mode)
+{
+  if (mode == HImode
+      || mode == PSImode
+      || mode == SImode
+      )
+    return 1;
+  return 0;
+}
+
+/* How Scalar Function Values Are Returned */
+
+/* Implements TARGET_LIBCALL_VALUE.  Most values are returned in $r0, or some
+   combination of registers starting there (r2r0 for longs, r3r1r2r0
+   for long long, r3r2r1r0 for doubles), except that that ABI
+   currently doesn't work because it ends up using all available
+   general registers and gcc often can't compile it.  So, instead, we
+   return anything bigger than 16 bits in "mem0" (effectively, a
+   memory location).  */
+
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE m32c_libcall_value
+
+static rtx
+m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
+{
+  /* return reg or parallel */
+#if 0
+  /* FIXME: GCC has difficulty returning large values in registers,
+     because that ties up most of the general registers and gives the
+     register allocator little to work with.  Until we can resolve
+     this, large values are returned in memory.  */
+  if (mode == DFmode)
+    {
+      rtx rv;
+
+      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
+      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
+					      gen_rtx_REG (HImode,
+							   R0_REGNO),
+					      GEN_INT (0));
+      XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
+					      gen_rtx_REG (HImode,
+							   R1_REGNO),
+					      GEN_INT (2));
+      XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
+					      gen_rtx_REG (HImode,
+							   R2_REGNO),
+					      GEN_INT (4));
+      XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
+					      gen_rtx_REG (HImode,
+							   R3_REGNO),
+					      GEN_INT (6));
+      return rv;
+    }
+
+  if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
+    {
+      rtx rv;
+
+      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
+      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
+					      gen_rtx_REG (mode,
+							   R0_REGNO),
+					      GEN_INT (0));
+      return rv;
+    }
+#endif
+
+  if (GET_MODE_SIZE (mode) > 2)
+    return gen_rtx_REG (mode, MEM0_REGNO);
+  return gen_rtx_REG (mode, R0_REGNO);
+}
+
+/* Implements TARGET_FUNCTION_VALUE.  Functions and libcalls have the same
+   conventions.  */
+
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE m32c_function_value
+
+static rtx
+m32c_function_value (const_tree valtype,
+		     const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
+		     bool outgoing ATTRIBUTE_UNUSED)
+{
+  /* return reg or parallel */
+  const enum machine_mode mode = TYPE_MODE (valtype);
+  return m32c_libcall_value (mode, NULL_RTX);
+}
+
+/* Implements TARGET_FUNCTION_VALUE_REGNO_P.  */
+
+#undef TARGET_FUNCTION_VALUE_REGNO_P
+#define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
+
+static bool
+m32c_function_value_regno_p (const unsigned int regno)
+{
+  return (regno == R0_REGNO || regno == MEM0_REGNO);
+}
+
+/* How Large Values Are Returned */
+
+/* We return structures by pushing the address on the stack, even if
+   we use registers for the first few "real" arguments.  */
+#undef TARGET_STRUCT_VALUE_RTX
+#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
+static rtx
+m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
+		       int incoming ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Function Entry and Exit */
+
+/* Implements EPILOGUE_USES.  Interrupts restore all registers.  */
+int
+m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
+{
+  if (cfun->machine->is_interrupt)
+    return 1;
+  return 0;
+}
+
+/* Implementing the Varargs Macros */
+
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
+static bool
+m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
+{
+  return 1;
+}
+
+/* Trampolines for Nested Functions */
+
+/*
+   m16c:
+   1 0000 75C43412              mov.w   #0x1234,a0
+   2 0004 FC000000              jmp.a   label
+
+   m32c:
+   1 0000 BC563412              mov.l:s #0x123456,a0
+   2 0004 CC000000              jmp.a   label
+*/
+
+/* Implements TRAMPOLINE_SIZE.  */
+int
+m32c_trampoline_size (void)
+{
+  /* Allocate extra space so we can avoid the messy shifts when we
+     initialize the trampoline; we just write past the end of the
+     opcode.  */
+  return TARGET_A16 ? 8 : 10;
+}
+
+/* Implements TRAMPOLINE_ALIGNMENT.  */
+int
+m32c_trampoline_alignment (void)
+{
+  return 2;
+}
+
+/* Implements TARGET_TRAMPOLINE_INIT.  */
+
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
+static void
+m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
+{
+  rtx function = XEXP (DECL_RTL (fndecl), 0);
+
+#define A0(m,i) adjust_address (m_tramp, m, i)
+  if (TARGET_A16)
+    {
+      /* Note: we subtract a "word" because the moves want signed
+	 constants, not unsigned constants.  */
+      emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
+      emit_move_insn (A0 (HImode, 2), chainval);
+      emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
+      /* We use 16-bit addresses here, but store the zero to turn it
+	 into a 24-bit offset.  */
+      emit_move_insn (A0 (HImode, 5), function);
+      emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
+    }
+  else
+    {
+      /* Note that the PSI moves actually write 4 bytes.  Make sure we
+	 write stuff out in the right order, and leave room for the
+	 extra byte at the end.  */
+      emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
+      emit_move_insn (A0 (PSImode, 1), chainval);
+      emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
+      emit_move_insn (A0 (PSImode, 5), function);
+    }
+#undef A0
+}
+
+/* Implicit Calls to Library Routines */
+
+#undef TARGET_INIT_LIBFUNCS
+#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
+static void
+m32c_init_libfuncs (void)
+{
+  /* We do this because the M32C has an HImode operand, but the
+     M16C has an 8-bit operand.  Since gcc looks at the match data
+     and not the expanded rtl, we have to reset the optab so that
+     the right modes are found. */
+  if (TARGET_A24)
+    {
+      set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
+      set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
+      set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstorepsi4_24);
+    }
+}
+
+/* Addressing Modes */
+
+/* The r8c/m32c family supports a wide range of non-orthogonal
+   addressing modes, including the ability to double-indirect on *some*
+   of them.  Not all insns support all modes, either, but we rely on
+   predicates and constraints to deal with that.  */
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
+bool
+m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
+{
+  int mode_adjust;
+  if (CONSTANT_P (x))
+    return 1;
+
+  if (TARGET_A16 && GET_MODE (x) != HImode && GET_MODE (x) != SImode)
+    return 0;
+  if (TARGET_A24 && GET_MODE (x) != PSImode)
+    return 0;
+
+  /* Wide references to memory will be split after reload, so we must
+     ensure that all parts of such splits remain legitimate
+     addresses.  */
+  mode_adjust = GET_MODE_SIZE (mode) - 1;
+
+  /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
+  if (GET_CODE (x) == PRE_DEC
+      || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
+    {
+      return (GET_CODE (XEXP (x, 0)) == REG
+	      && REGNO (XEXP (x, 0)) == SP_REGNO);
+    }
+
+#if 0
+  /* This is the double indirection detection, but it currently
+     doesn't work as cleanly as this code implies, so until we've had
+     a chance to debug it, leave it disabled.  */
+  if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
+    {
+#if DEBUG_DOUBLE
+      fprintf (stderr, "double indirect\n");
+#endif
+      x = XEXP (x, 0);
+    }
+#endif
+
+  encode_pattern (x);
+  if (RTX_IS ("r"))
+    {
+      /* Most indexable registers can be used without displacements,
+	 although some of them will be emitted with an explicit zero
+	 to please the assembler.  */
+      switch (REGNO (patternr[0]))
+	{
+	case A1_REGNO:
+	case SB_REGNO:
+	case FB_REGNO:
+	case SP_REGNO:
+	  if (TARGET_A16 && GET_MODE (x) == SImode)
+	    return 0;
+	case A0_REGNO:
+	  return 1;
+
+	default:
+	  if (IS_PSEUDO (patternr[0], strict))
+	    return 1;
+	  return 0;
+	}
+    }
+
+  if (TARGET_A16 && GET_MODE (x) == SImode)
+    return 0;
+
+  if (RTX_IS ("+ri"))
+    {
+      /* This is more interesting, because different base registers
+	 allow for different displacements - both range and signedness
+	 - and it differs from chip series to chip series too.  */
+      int rn = REGNO (patternr[1]);
+      HOST_WIDE_INT offs = INTVAL (patternr[2]);
+      switch (rn)
+	{
+	case A0_REGNO:
+	case A1_REGNO:
+	case SB_REGNO:
+	  /* The syntax only allows positive offsets, but when the
+	     offsets span the entire memory range, we can simulate
+	     negative offsets by wrapping.  */
+	  if (TARGET_A16)
+	    return (offs >= -65536 && offs <= 65535 - mode_adjust);
+	  if (rn == SB_REGNO)
+	    return (offs >= 0 && offs <= 65535 - mode_adjust);
+	  /* A0 or A1 */
+	  return (offs >= -16777216 && offs <= 16777215);
+
+	case FB_REGNO:
+	  if (TARGET_A16)
+	    return (offs >= -128 && offs <= 127 - mode_adjust);
+	  return (offs >= -65536 && offs <= 65535 - mode_adjust);
+
+	case SP_REGNO:
+	  return (offs >= -128 && offs <= 127 - mode_adjust);
+
+	default:
+	  if (IS_PSEUDO (patternr[1], strict))
+	    return 1;
+	  return 0;
+	}
+    }
+  if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
+    {
+      rtx reg = patternr[1];
+
+      /* We don't know where the symbol is, so only allow base
+	 registers which support displacements spanning the whole
+	 address range.  */
+      switch (REGNO (reg))
+	{
+	case A0_REGNO:
+	case A1_REGNO:
+	  /* $sb needs a secondary reload, but since it's involved in
+	     memory address reloads too, we don't deal with it very
+	     well.  */
+	  /*    case SB_REGNO: */
+	  return 1;
+	default:
+	  if (IS_PSEUDO (reg, strict))
+	    return 1;
+	  return 0;
+	}
+    }
+  return 0;
+}
+
+/* Implements REG_OK_FOR_BASE_P.  */
+int
+m32c_reg_ok_for_base_p (rtx x, int strict)
+{
+  if (GET_CODE (x) != REG)
+    return 0;
+  switch (REGNO (x))
+    {
+    case A0_REGNO:
+    case A1_REGNO:
+    case SB_REGNO:
+    case FB_REGNO:
+    case SP_REGNO:
+      return 1;
+    default:
+      if (IS_PSEUDO (x, strict))
+	return 1;
+      return 0;
+    }
+}
+
+/* We have three choices for choosing fb->aN offsets.  If we choose -128,
+   we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
+   like this:
+       EB 4B FF    mova    -128[$fb],$a0
+       D8 0C FF FF mov.w:Q #0,-1[$a0]
+
+   Alternately, we subtract the frame size, and hopefully use 8-bit aN
+   displacements:
+       7B F4       stc $fb,$a0
+       77 54 00 01 sub #256,$a0
+       D8 08 01    mov.w:Q #0,1[$a0]
+
+   If we don't offset (i.e. offset by zero), we end up with:
+       7B F4       stc $fb,$a0
+       D8 0C 00 FF mov.w:Q #0,-256[$a0]
+
+   We have to subtract *something* so that we have a PLUS rtx to mark
+   that we've done this reload.  The -128 offset will never result in
+   an 8-bit aN offset, and the payoff for the second case is five
+   loads *if* those loads are within 256 bytes of the other end of the
+   frame, so the third case seems best.  Note that we subtract the
+   zero, but detect that in the addhi3 pattern.  */
+
+#define BIG_FB_ADJ 0
+
+/* Implements LEGITIMIZE_ADDRESS.  The only address we really have to
+   worry about is frame base offsets, as $fb has a limited
+   displacement range.  We deal with this by attempting to reload $fb
+   itself into an address register; that seems to result in the best
+   code.  */
+#undef TARGET_LEGITIMIZE_ADDRESS
+#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
+static rtx
+m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
+			 enum machine_mode mode)
+{
+#if DEBUG0
+  fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
+  debug_rtx (x);
+  fprintf (stderr, "\n");
+#endif
+
+  if (GET_CODE (x) == PLUS
+      && GET_CODE (XEXP (x, 0)) == REG
+      && REGNO (XEXP (x, 0)) == FB_REGNO
+      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && (INTVAL (XEXP (x, 1)) < -128
+	  || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
+    {
+      /* reload FB to A_REGS */
+      rtx temp = gen_reg_rtx (Pmode);
+      x = copy_rtx (x);
+      emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
+      XEXP (x, 0) = temp;
+    }
+
+  return x;
+}
+
+/* Implements LEGITIMIZE_RELOAD_ADDRESS.  See comment above.  */
+int
+m32c_legitimize_reload_address (rtx * x,
+				enum machine_mode mode,
+				int opnum,
+				int type, int ind_levels ATTRIBUTE_UNUSED)
+{
+#if DEBUG0
+  fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
+	   mode_name[mode]);
+  debug_rtx (*x);
+#endif
+
+  /* At one point, this function tried to get $fb copied to an address
+     register, which in theory would maximize sharing, but gcc was
+     *also* still trying to reload the whole address, and we'd run out
+     of address registers.  So we let gcc do the naive (but safe)
+     reload instead, when the above function doesn't handle it for
+     us.
+
+     The code below is a second attempt at the above.  */
+
+  if (GET_CODE (*x) == PLUS
+      && GET_CODE (XEXP (*x, 0)) == REG
+      && REGNO (XEXP (*x, 0)) == FB_REGNO
+      && GET_CODE (XEXP (*x, 1)) == CONST_INT
+      && (INTVAL (XEXP (*x, 1)) < -128
+	  || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
+    {
+      rtx sum;
+      int offset = INTVAL (XEXP (*x, 1));
+      int adjustment = -BIG_FB_ADJ;
+
+      sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
+			  GEN_INT (adjustment));
+      *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
+      if (type == RELOAD_OTHER)
+	type = RELOAD_FOR_OTHER_ADDRESS;
+      push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
+		   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
+		   (enum reload_type) type);
+      return 1;
+    }
+
+  if (GET_CODE (*x) == PLUS
+      && GET_CODE (XEXP (*x, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
+      && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
+      && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
+      && GET_CODE (XEXP (*x, 1)) == CONST_INT
+      )
+    {
+      if (type == RELOAD_OTHER)
+	type = RELOAD_FOR_OTHER_ADDRESS;
+      push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
+		   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
+		   (enum reload_type) type);
+      return 1;
+    }
+
+  return 0;
+}
+
+/* Implements LEGITIMATE_CONSTANT_P.  We split large constants anyway,
+   so we can allow anything.  */
+int
+m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
+{
+  return 1;
+}
+
+
+/* Return the appropriate mode for a named address pointer.  */
+#undef TARGET_ADDR_SPACE_POINTER_MODE
+#define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
+static enum machine_mode
+m32c_addr_space_pointer_mode (addr_space_t addrspace)
+{
+  switch (addrspace)
+    {
+    case ADDR_SPACE_GENERIC:
+      return TARGET_A24 ? PSImode : HImode;
+    case ADDR_SPACE_FAR:
+      return SImode;
+    default:
+      gcc_unreachable ();
+    }
+}
+
+/* Return the appropriate mode for a named address address.  */
+#undef TARGET_ADDR_SPACE_ADDRESS_MODE
+#define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
+static enum machine_mode
+m32c_addr_space_address_mode (addr_space_t addrspace)
+{
+  switch (addrspace)
+    {
+    case ADDR_SPACE_GENERIC:
+      return TARGET_A24 ? PSImode : HImode;
+    case ADDR_SPACE_FAR:
+      return SImode;
+    default:
+      gcc_unreachable ();
+    }
+}
+
+/* Like m32c_legitimate_address_p, except with named addresses.  */
+#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
+#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
+  m32c_addr_space_legitimate_address_p
+static bool
+m32c_addr_space_legitimate_address_p (enum machine_mode mode, rtx x,
+				      bool strict, addr_space_t as)
+{
+  if (as == ADDR_SPACE_FAR)
+    {
+      if (TARGET_A24)
+	return 0;
+      encode_pattern (x);
+      if (RTX_IS ("r"))
+	{
+	  if (GET_MODE (x) != SImode)
+	    return 0;
+	  switch (REGNO (patternr[0]))
+	    {
+	    case A0_REGNO:
+	      return 1;
+
+	    default:
+	      if (IS_PSEUDO (patternr[0], strict))
+		return 1;
+	      return 0;
+	    }
+	}
+      if (RTX_IS ("+^Sri"))
+	{
+	  int rn = REGNO (patternr[3]);
+	  HOST_WIDE_INT offs = INTVAL (patternr[4]);
+	  if (GET_MODE (patternr[3]) != HImode)
+	    return 0;
+	  switch (rn)
+	    {
+	    case A0_REGNO:
+	      return (offs >= 0 && offs <= 0xfffff);
+
+	    default:
+	      if (IS_PSEUDO (patternr[3], strict))
+		return 1;
+	      return 0;
+	    }
+	}
+      if (RTX_IS ("+^Srs"))
+	{
+	  int rn = REGNO (patternr[3]);
+	  if (GET_MODE (patternr[3]) != HImode)
+	    return 0;
+	  switch (rn)
+	    {
+	    case A0_REGNO:
+	      return 1;
+
+	    default:
+	      if (IS_PSEUDO (patternr[3], strict))
+		return 1;
+	      return 0;
+	    }
+	}
+      if (RTX_IS ("+^S+ris"))
+	{
+	  int rn = REGNO (patternr[4]);
+	  if (GET_MODE (patternr[4]) != HImode)
+	    return 0;
+	  switch (rn)
+	    {
+	    case A0_REGNO:
+	      return 1;
+
+	    default:
+	      if (IS_PSEUDO (patternr[4], strict))
+		return 1;
+	      return 0;
+	    }
+	}
+      if (RTX_IS ("s"))
+	{
+	  return 1;
+	}
+      return 0;
+    }
+
+  else if (as != ADDR_SPACE_GENERIC)
+    gcc_unreachable ();
+
+  return m32c_legitimate_address_p (mode, x, strict);
+}
+
+/* Like m32c_legitimate_address, except with named address support.  */
+#undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
+#define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
+static rtx
+m32c_addr_space_legitimize_address (rtx x, rtx oldx, enum machine_mode mode,
+				    addr_space_t as)
+{
+  if (as != ADDR_SPACE_GENERIC)
+    {
+#if DEBUG0
+      fprintf (stderr, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name[mode]);
+      debug_rtx (x);
+      fprintf (stderr, "\n");
+#endif
+
+      if (GET_CODE (x) != REG)
+	{
+	  x = force_reg (SImode, x);
+	}
+      return x;
+    }
+
+  return m32c_legitimize_address (x, oldx, mode);
+}
+
+/* Determine if one named address space is a subset of another.  */
+#undef TARGET_ADDR_SPACE_SUBSET_P
+#define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
+static bool
+m32c_addr_space_subset_p (addr_space_t subset, addr_space_t superset)
+{
+  gcc_assert (subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_FAR);
+  gcc_assert (superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_FAR);
+
+  if (subset == superset)
+    return true;
+
+  else
+    return (subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_FAR);
+}
+
+#undef TARGET_ADDR_SPACE_CONVERT
+#define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
+/* Convert from one address space to another.  */
+static rtx
+m32c_addr_space_convert (rtx op, tree from_type, tree to_type)
+{
+  addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));
+  addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));
+  rtx result;
+
+  gcc_assert (from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR);
+  gcc_assert (to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR);
+
+  if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR)
+    {
+      /* This is unpredictable, as we're truncating off usable address
+	 bits.  */
+
+      result = gen_reg_rtx (HImode);
+      emit_move_insn (result, simplify_subreg (HImode, op, SImode, 0));
+      return result;
+    }
+  else if (to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC)
+    {
+      /* This always works.  */
+      result = gen_reg_rtx (SImode);
+      emit_insn (gen_zero_extendhisi2 (result, op));
+      return result;
+    }
+  else
+    gcc_unreachable ();
+}
+
+/* Condition Code Status */
+
+#undef TARGET_FIXED_CONDITION_CODE_REGS
+#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
+static bool
+m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
+{
+  *p1 = FLG_REGNO;
+  *p2 = INVALID_REGNUM;
+  return true;
+}
+
+/* Describing Relative Costs of Operations */
+
+/* Implements TARGET_REGISTER_MOVE_COST.  We make impossible moves
+   prohibitively expensive, like trying to put QIs in r2/r3 (there are
+   no opcodes to do that).  We also discourage use of mem* registers
+   since they're really memory.  */
+
+#undef TARGET_REGISTER_MOVE_COST
+#define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
+
+static int
+m32c_register_move_cost (enum machine_mode mode, reg_class_t from,
+			 reg_class_t to)
+{
+  int cost = COSTS_N_INSNS (3);
+  HARD_REG_SET cc;
+
+/* FIXME: pick real values, but not 2 for now.  */
+  COPY_HARD_REG_SET (cc, reg_class_contents[(int) from]);
+  IOR_HARD_REG_SET (cc, reg_class_contents[(int) to]);
+
+  if (mode == QImode
+      && hard_reg_set_intersect_p (cc, reg_class_contents[R23_REGS]))
+    {
+      if (hard_reg_set_subset_p (cc, reg_class_contents[R23_REGS]))
+	cost = COSTS_N_INSNS (1000);
+      else
+	cost = COSTS_N_INSNS (80);
+    }
+
+  if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
+    cost = COSTS_N_INSNS (1000);
+
+  if (reg_classes_intersect_p (from, CR_REGS))
+    cost += COSTS_N_INSNS (5);
+
+  if (reg_classes_intersect_p (to, CR_REGS))
+    cost += COSTS_N_INSNS (5);
+
+  if (from == MEM_REGS || to == MEM_REGS)
+    cost += COSTS_N_INSNS (50);
+  else if (reg_classes_intersect_p (from, MEM_REGS)
+	   || reg_classes_intersect_p (to, MEM_REGS))
+    cost += COSTS_N_INSNS (10);
+
+#if DEBUG0
+  fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
+	   mode_name[mode], class_names[(int) from], class_names[(int) to],
+	   cost);
+#endif
+  return cost;
+}
+
+/*  Implements TARGET_MEMORY_MOVE_COST.  */
+
+#undef TARGET_MEMORY_MOVE_COST
+#define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
+
+static int
+m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+		       reg_class_t rclass ATTRIBUTE_UNUSED,
+		       bool in ATTRIBUTE_UNUSED)
+{
+  /* FIXME: pick real values.  */
+  return COSTS_N_INSNS (10);
+}
+
+/* Here we try to describe when we use multiple opcodes for one RTX so
+   that gcc knows when to use them.  */
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS m32c_rtx_costs
+static bool
+m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
+		bool speed ATTRIBUTE_UNUSED)
+{
+  switch (code)
+    {
+    case REG:
+      if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
+	*total += COSTS_N_INSNS (500);
+      else
+	*total += COSTS_N_INSNS (1);
+      return true;
+
+    case ASHIFT:
+    case LSHIFTRT:
+    case ASHIFTRT:
+      if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+	{
+	  /* mov.b r1l, r1h */
+	  *total +=  COSTS_N_INSNS (1);
+	  return true;
+	}
+      if (INTVAL (XEXP (x, 1)) > 8
+	  || INTVAL (XEXP (x, 1)) < -8)
+	{
+	  /* mov.b #N, r1l */
+	  /* mov.b r1l, r1h */
+	  *total +=  COSTS_N_INSNS (2);
+	  return true;
+	}
+      return true;
+
+    case LE:
+    case LEU:
+    case LT:
+    case LTU:
+    case GT:
+    case GTU:
+    case GE:
+    case GEU:
+    case NE:
+    case EQ:
+      if (outer_code == SET)
+	{
+	  *total += COSTS_N_INSNS (2);
+	  return true;
+	}
+      break;
+
+    case ZERO_EXTRACT:
+      {
+	rtx dest = XEXP (x, 0);
+	rtx addr = XEXP (dest, 0);
+	switch (GET_CODE (addr))
+	  {
+	  case CONST_INT:
+	    *total += COSTS_N_INSNS (1);
+	    break;
+	  case SYMBOL_REF:
+	    *total += COSTS_N_INSNS (3);
+	    break;
+	  default:
+	    *total += COSTS_N_INSNS (2);
+	    break;
+	  }
+	return true;
+      }
+      break;
+
+    default:
+      /* Reasonable default.  */
+      if (TARGET_A16 && GET_MODE(x) == SImode)
+	*total += COSTS_N_INSNS (2);
+      break;
+    }
+  return false;
+}
+
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST m32c_address_cost
+static int
+m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
+{
+  int i;
+  /*  fprintf(stderr, "\naddress_cost\n");
+      debug_rtx(addr);*/
+  switch (GET_CODE (addr))
+    {
+    case CONST_INT:
+      i = INTVAL (addr);
+      if (i == 0)
+	return COSTS_N_INSNS(1);
+      if (0 < i && i <= 255)
+	return COSTS_N_INSNS(2);
+      if (0 < i && i <= 65535)
+	return COSTS_N_INSNS(3);
+      return COSTS_N_INSNS(4);
+    case SYMBOL_REF:
+      return COSTS_N_INSNS(4);
+    case REG:
+      return COSTS_N_INSNS(1);
+    case PLUS:
+      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+	{
+	  i = INTVAL (XEXP (addr, 1));
+	  if (i == 0)
+	    return COSTS_N_INSNS(1);
+	  if (0 < i && i <= 255)
+	    return COSTS_N_INSNS(2);
+	  if (0 < i && i <= 65535)
+	    return COSTS_N_INSNS(3);
+	}
+      return COSTS_N_INSNS(4);
+    default:
+      return 0;
+    }
+}
+
+/* Defining the Output Assembler Language */
+
+/* The Overall Framework of an Assembler File */
+
+#undef TARGET_HAVE_NAMED_SECTIONS
+#define TARGET_HAVE_NAMED_SECTIONS true
+
+/* Output of Data */
+
+/* We may have 24 bit sizes, which is the native address size.
+   Currently unused, but provided for completeness.  */
+#undef TARGET_ASM_INTEGER
+#define TARGET_ASM_INTEGER m32c_asm_integer
+static bool
+m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
+{
+  switch (size)
+    {
+    case 3:
+      fprintf (asm_out_file, "\t.3byte\t");
+      output_addr_const (asm_out_file, x);
+      fputc ('\n', asm_out_file);
+      return true;
+    case 4:
+      if (GET_CODE (x) == SYMBOL_REF)
+	{
+	  fprintf (asm_out_file, "\t.long\t");
+	  output_addr_const (asm_out_file, x);
+	  fputc ('\n', asm_out_file);
+	  return true;
+	}
+      break;
+    }
+  return default_assemble_integer (x, size, aligned_p);
+}
+
+/* Output of Assembler Instructions */
+
+/* We use a lookup table because the addressing modes are non-orthogonal.  */
+
+static struct
+{
+  char code;
+  char const *pattern;
+  char const *format;
+}
+const conversions[] = {
+  { 0, "r", "0" },
+
+  { 0, "mr", "z[1]" },
+  { 0, "m+ri", "3[2]" },
+  { 0, "m+rs", "3[2]" },
+  { 0, "m+^Zrs", "5[4]" },
+  { 0, "m+^Zri", "5[4]" },
+  { 0, "m+^Z+ris", "7+6[5]" },
+  { 0, "m+^Srs", "5[4]" },
+  { 0, "m+^Sri", "5[4]" },
+  { 0, "m+^S+ris", "7+6[5]" },
+  { 0, "m+r+si", "4+5[2]" },
+  { 0, "ms", "1" },
+  { 0, "mi", "1" },
+  { 0, "m+si", "2+3" },
+
+  { 0, "mmr", "[z[2]]" },
+  { 0, "mm+ri", "[4[3]]" },
+  { 0, "mm+rs", "[4[3]]" },
+  { 0, "mm+r+si", "[5+6[3]]" },
+  { 0, "mms", "[[2]]" },
+  { 0, "mmi", "[[2]]" },
+  { 0, "mm+si", "[4[3]]" },
+
+  { 0, "i", "#0" },
+  { 0, "s", "#0" },
+  { 0, "+si", "#1+2" },
+  { 0, "l", "#0" },
+
+  { 'l', "l", "0" },
+  { 'd', "i", "0" },
+  { 'd', "s", "0" },
+  { 'd', "+si", "1+2" },
+  { 'D', "i", "0" },
+  { 'D', "s", "0" },
+  { 'D', "+si", "1+2" },
+  { 'x', "i", "#0" },
+  { 'X', "i", "#0" },
+  { 'm', "i", "#0" },
+  { 'b', "i", "#0" },
+  { 'B', "i", "0" },
+  { 'p', "i", "0" },
+
+  { 0, 0, 0 }
+};
+
+/* This is in order according to the bitfield that pushm/popm use.  */
+static char const *pushm_regs[] = {
+  "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
+};
+
+/* Implements PRINT_OPERAND.  */
+void
+m32c_print_operand (FILE * file, rtx x, int code)
+{
+  int i, j, b;
+  const char *comma;
+  HOST_WIDE_INT ival;
+  int unsigned_const = 0;
+  int force_sign;
+
+  /* Multiplies; constants are converted to sign-extended format but
+   we need unsigned, so 'u' and 'U' tell us what size unsigned we
+   need.  */
+  if (code == 'u')
+    {
+      unsigned_const = 2;
+      code = 0;
+    }
+  if (code == 'U')
+    {
+      unsigned_const = 1;
+      code = 0;
+    }
+  /* This one is only for debugging; you can put it in a pattern to
+     force this error.  */
+  if (code == '!')
+    {
+      fprintf (stderr, "dj: unreviewed pattern:");
+      if (current_output_insn)
+	debug_rtx (current_output_insn);
+      gcc_unreachable ();
+    }
+  /* PSImode operations are either .w or .l depending on the target.  */
+  if (code == '&')
+    {
+      if (TARGET_A16)
+	fprintf (file, "w");
+      else
+	fprintf (file, "l");
+      return;
+    }
+  /* Inverted conditionals.  */
+  if (code == 'C')
+    {
+      switch (GET_CODE (x))
+	{
+	case LE:
+	  fputs ("gt", file);
+	  break;
+	case LEU:
+	  fputs ("gtu", file);
+	  break;
+	case LT:
+	  fputs ("ge", file);
+	  break;
+	case LTU:
+	  fputs ("geu", file);
+	  break;
+	case GT:
+	  fputs ("le", file);
+	  break;
+	case GTU:
+	  fputs ("leu", file);
+	  break;
+	case GE:
+	  fputs ("lt", file);
+	  break;
+	case GEU:
+	  fputs ("ltu", file);
+	  break;
+	case NE:
+	  fputs ("eq", file);
+	  break;
+	case EQ:
+	  fputs ("ne", file);
+	  break;
+	default:
+	  gcc_unreachable ();
+	}
+      return;
+    }
+  /* Regular conditionals.  */
+  if (code == 'c')
+    {
+      switch (GET_CODE (x))
+	{
+	case LE:
+	  fputs ("le", file);
+	  break;
+	case LEU:
+	  fputs ("leu", file);
+	  break;
+	case LT:
+	  fputs ("lt", file);
+	  break;
+	case LTU:
+	  fputs ("ltu", file);
+	  break;
+	case GT:
+	  fputs ("gt", file);
+	  break;
+	case GTU:
+	  fputs ("gtu", file);
+	  break;
+	case GE:
+	  fputs ("ge", file);
+	  break;
+	case GEU:
+	  fputs ("geu", file);
+	  break;
+	case NE:
+	  fputs ("ne", file);
+	  break;
+	case EQ:
+	  fputs ("eq", file);
+	  break;
+	default:
+	  gcc_unreachable ();
+	}
+      return;
+    }
+  /* Used in negsi2 to do HImode ops on the two parts of an SImode
+     operand.  */
+  if (code == 'h' && GET_MODE (x) == SImode)
+    {
+      x = m32c_subreg (HImode, x, SImode, 0);
+      code = 0;
+    }
+  if (code == 'H' && GET_MODE (x) == SImode)
+    {
+      x = m32c_subreg (HImode, x, SImode, 2);
+      code = 0;
+    }
+  if (code == 'h' && GET_MODE (x) == HImode)
+    {
+      x = m32c_subreg (QImode, x, HImode, 0);
+      code = 0;
+    }
+  if (code == 'H' && GET_MODE (x) == HImode)
+    {
+      /* We can't actually represent this as an rtx.  Do it here.  */
+      if (GET_CODE (x) == REG)
+	{
+	  switch (REGNO (x))
+	    {
+	    case R0_REGNO:
+	      fputs ("r0h", file);
+	      return;
+	    case R1_REGNO:
+	      fputs ("r1h", file);
+	      return;
+	    default:
+	      gcc_unreachable();
+	    }
+	}
+      /* This should be a MEM.  */
+      x = m32c_subreg (QImode, x, HImode, 1);
+      code = 0;
+    }
+  /* This is for BMcond, which always wants word register names.  */
+  if (code == 'h' && GET_MODE (x) == QImode)
+    {
+      if (GET_CODE (x) == REG)
+	x = gen_rtx_REG (HImode, REGNO (x));
+      code = 0;
+    }
+  /* 'x' and 'X' need to be ignored for non-immediates.  */
+  if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
+    code = 0;
+
+  encode_pattern (x);
+  force_sign = 0;
+  for (i = 0; conversions[i].pattern; i++)
+    if (conversions[i].code == code
+	&& streq (conversions[i].pattern, pattern))
+      {
+	for (j = 0; conversions[i].format[j]; j++)
+	  /* backslash quotes the next character in the output pattern.  */
+	  if (conversions[i].format[j] == '\\')
+	    {
+	      fputc (conversions[i].format[j + 1], file);
+	      j++;
+	    }
+	  /* Digits in the output pattern indicate that the
+	     corresponding RTX is to be output at that point.  */
+	  else if (ISDIGIT (conversions[i].format[j]))
+	    {
+	      rtx r = patternr[conversions[i].format[j] - '0'];
+	      switch (GET_CODE (r))
+		{
+		case REG:
+		  fprintf (file, "%s",
+			   reg_name_with_mode (REGNO (r), GET_MODE (r)));
+		  break;
+		case CONST_INT:
+		  switch (code)
+		    {
+		    case 'b':
+		    case 'B':
+		      {
+			int v = INTVAL (r);
+			int i = (int) exact_log2 (v);
+			if (i == -1)
+			  i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
+			if (i == -1)
+			  i = (int) exact_log2 ((v ^ 0xff) & 0xff);
+			/* Bit position.  */
+			fprintf (file, "%d", i);
+		      }
+		      break;
+		    case 'x':
+		      /* Unsigned byte.  */
+		      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+			       INTVAL (r) & 0xff);
+		      break;
+		    case 'X':
+		      /* Unsigned word.  */
+		      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+			       INTVAL (r) & 0xffff);
+		      break;
+		    case 'p':
+		      /* pushm and popm encode a register set into a single byte.  */
+		      comma = "";
+		      for (b = 7; b >= 0; b--)
+			if (INTVAL (r) & (1 << b))
+			  {
+			    fprintf (file, "%s%s", comma, pushm_regs[b]);
+			    comma = ",";
+			  }
+		      break;
+		    case 'm':
+		      /* "Minus".  Output -X  */
+		      ival = (-INTVAL (r) & 0xffff);
+		      if (ival & 0x8000)
+			ival = ival - 0x10000;
+		      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
+		      break;
+		    default:
+		      ival = INTVAL (r);
+		      if (conversions[i].format[j + 1] == '[' && ival < 0)
+			{
+			  /* We can simulate negative displacements by
+			     taking advantage of address space
+			     wrapping when the offset can span the
+			     entire address range.  */
+			  rtx base =
+			    patternr[conversions[i].format[j + 2] - '0'];
+			  if (GET_CODE (base) == REG)
+			    switch (REGNO (base))
+			      {
+			      case A0_REGNO:
+			      case A1_REGNO:
+				if (TARGET_A24)
+				  ival = 0x1000000 + ival;
+				else
+				  ival = 0x10000 + ival;
+				break;
+			      case SB_REGNO:
+				if (TARGET_A16)
+				  ival = 0x10000 + ival;
+				break;
+			      }
+			}
+		      else if (code == 'd' && ival < 0 && j == 0)
+			/* The "mova" opcode is used to do addition by
+			   computing displacements, but again, we need
+			   displacements to be unsigned *if* they're
+			   the only component of the displacement
+			   (i.e. no "symbol-4" type displacement).  */
+			ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
+
+		      if (conversions[i].format[j] == '0')
+			{
+			  /* More conversions to unsigned.  */
+			  if (unsigned_const == 2)
+			    ival &= 0xffff;
+			  if (unsigned_const == 1)
+			    ival &= 0xff;
+			}
+		      if (streq (conversions[i].pattern, "mi")
+			  || streq (conversions[i].pattern, "mmi"))
+			{
+			  /* Integers used as addresses are unsigned.  */
+			  ival &= (TARGET_A24 ? 0xffffff : 0xffff);
+			}
+		      if (force_sign && ival >= 0)
+			fputc ('+', file);
+		      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
+		      break;
+		    }
+		  break;
+		case CONST_DOUBLE:
+		  /* We don't have const_double constants.  If it
+		     happens, make it obvious.  */
+		  fprintf (file, "[const_double 0x%lx]",
+			   (unsigned long) CONST_DOUBLE_HIGH (r));
+		  break;
+		case SYMBOL_REF:
+		  assemble_name (file, XSTR (r, 0));
+		  break;
+		case LABEL_REF:
+		  output_asm_label (r);
+		  break;
+		default:
+		  fprintf (stderr, "don't know how to print this operand:");
+		  debug_rtx (r);
+		  gcc_unreachable ();
+		}
+	    }
+	  else
+	    {
+	      if (conversions[i].format[j] == 'z')
+		{
+		  /* Some addressing modes *must* have a displacement,
+		     so insert a zero here if needed.  */
+		  int k;
+		  for (k = j + 1; conversions[i].format[k]; k++)
+		    if (ISDIGIT (conversions[i].format[k]))
+		      {
+			rtx reg = patternr[conversions[i].format[k] - '0'];
+			if (GET_CODE (reg) == REG
+			    && (REGNO (reg) == SB_REGNO
+				|| REGNO (reg) == FB_REGNO
+				|| REGNO (reg) == SP_REGNO))
+			  fputc ('0', file);
+		      }
+		  continue;
+		}
+	      /* Signed displacements off symbols need to have signs
+		 blended cleanly.  */
+	      if (conversions[i].format[j] == '+'
+		  && (!code || code == 'D' || code == 'd')
+		  && ISDIGIT (conversions[i].format[j + 1])
+		  && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
+		      == CONST_INT))
+		{
+		  force_sign = 1;
+		  continue;
+		}
+	      fputc (conversions[i].format[j], file);
+	    }
+	break;
+      }
+  if (!conversions[i].pattern)
+    {
+      fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
+	       pattern);
+      debug_rtx (x);
+      fprintf (file, "[%c.%s]", code ? code : '-', pattern);
+    }
+
+  return;
+}
+
+/* Implements PRINT_OPERAND_PUNCT_VALID_P.  See m32c_print_operand
+   above for descriptions of what these do.  */
+int
+m32c_print_operand_punct_valid_p (int c)
+{
+  if (c == '&' || c == '!')
+    return 1;
+  return 0;
+}
+
+/* Implements PRINT_OPERAND_ADDRESS.  Nothing unusual here.  */
+void
+m32c_print_operand_address (FILE * stream, rtx address)
+{
+  if (GET_CODE (address) == MEM)
+    address = XEXP (address, 0);
+  else
+    /* cf: gcc.dg/asm-4.c.  */
+    gcc_assert (GET_CODE (address) == REG);
+
+  m32c_print_operand (stream, address, 0);
+}
+
+/* Implements ASM_OUTPUT_REG_PUSH.  Control registers are pushed
+   differently than general registers.  */
+void
+m32c_output_reg_push (FILE * s, int regno)
+{
+  if (regno == FLG_REGNO)
+    fprintf (s, "\tpushc\tflg\n");
+  else
+    fprintf (s, "\tpush.%c\t%s\n",
+	     " bwll"[reg_push_size (regno)], reg_names[regno]);
+}
+
+/* Likewise for ASM_OUTPUT_REG_POP.  */
+void
+m32c_output_reg_pop (FILE * s, int regno)
+{
+  if (regno == FLG_REGNO)
+    fprintf (s, "\tpopc\tflg\n");
+  else
+    fprintf (s, "\tpop.%c\t%s\n",
+	     " bwll"[reg_push_size (regno)], reg_names[regno]);
+}
+
+/* Defining target-specific uses of `__attribute__' */
+
+/* Used to simplify the logic below.  Find the attributes wherever
+   they may be.  */
+#define M32C_ATTRIBUTES(decl) \
+  (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
+                : DECL_ATTRIBUTES (decl) \
+                  ? (DECL_ATTRIBUTES (decl)) \
+		  : TYPE_ATTRIBUTES (TREE_TYPE (decl))
+
+/* Returns TRUE if the given tree has the "interrupt" attribute.  */
+static int
+interrupt_p (tree node ATTRIBUTE_UNUSED)
+{
+  tree list = M32C_ATTRIBUTES (node);
+  while (list)
+    {
+      if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
+	return 1;
+      list = TREE_CHAIN (list);
+    }
+  return fast_interrupt_p (node);
+}
+
+/* Returns TRUE if the given tree has the "bank_switch" attribute.  */
+static int
+bank_switch_p (tree node ATTRIBUTE_UNUSED)
+{
+  tree list = M32C_ATTRIBUTES (node);
+  while (list)
+    {
+      if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
+	return 1;
+      list = TREE_CHAIN (list);
+    }
+  return 0;
+}
+
+/* Returns TRUE if the given tree has the "fast_interrupt" attribute.  */
+static int
+fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
+{
+  tree list = M32C_ATTRIBUTES (node);
+  while (list)
+    {
+      if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
+	return 1;
+      list = TREE_CHAIN (list);
+    }
+  return 0;
+}
+
+static tree
+interrupt_handler (tree * node ATTRIBUTE_UNUSED,
+		   tree name ATTRIBUTE_UNUSED,
+		   tree args ATTRIBUTE_UNUSED,
+		   int flags ATTRIBUTE_UNUSED,
+		   bool * no_add_attrs ATTRIBUTE_UNUSED)
+{
+  return NULL_TREE;
+}
+
+/* Returns TRUE if given tree has the "function_vector" attribute. */
+int
+m32c_special_page_vector_p (tree func)
+{
+  tree list;
+
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    return 0;
+
+  list = M32C_ATTRIBUTES (func);
+  while (list)
+    {
+      if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
+        return 1;
+      list = TREE_CHAIN (list);
+    }
+  return 0;
+}
+
+static tree
+function_vector_handler (tree * node ATTRIBUTE_UNUSED,
+                         tree name ATTRIBUTE_UNUSED,
+                         tree args ATTRIBUTE_UNUSED,
+                         int flags ATTRIBUTE_UNUSED,
+                         bool * no_add_attrs ATTRIBUTE_UNUSED)
+{
+  if (TARGET_R8C)
+    {
+      /* The attribute is not supported for R8C target.  */
+      warning (OPT_Wattributes,
+                "%qE attribute is not supported for R8C target",
+                name);
+      *no_add_attrs = true;
+    }
+  else if (TREE_CODE (*node) != FUNCTION_DECL)
+    {
+      /* The attribute must be applied to functions only.  */
+      warning (OPT_Wattributes,
+                "%qE attribute applies only to functions",
+                name);
+      *no_add_attrs = true;
+    }
+  else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
+    {
+      /* The argument must be a constant integer.  */
+      warning (OPT_Wattributes,
+                "%qE attribute argument not an integer constant",
+                name);
+      *no_add_attrs = true;
+    }
+  else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
+           || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
+    {
+      /* The argument value must be between 18 to 255.  */
+      warning (OPT_Wattributes,
+                "%qE attribute argument should be between 18 to 255",
+                name);
+      *no_add_attrs = true;
+    }
+  return NULL_TREE;
+}
+
+/* If the function is assigned the attribute 'function_vector', it
+   returns the function vector number, otherwise returns zero.  */
+int
+current_function_special_page_vector (rtx x)
+{
+  int num;
+
+  if ((GET_CODE(x) == SYMBOL_REF)
+      && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
+    {
+      tree list;
+      tree t = SYMBOL_REF_DECL (x);
+
+      if (TREE_CODE (t) != FUNCTION_DECL)
+        return 0;
+
+      list = M32C_ATTRIBUTES (t);
+      while (list)
+        {
+          if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
+            {
+              num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
+              return num;
+            }
+
+          list = TREE_CHAIN (list);
+        }
+
+      return 0;
+    }
+  else
+    return 0;
+}
+
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
+static const struct attribute_spec m32c_attribute_table[] = {
+  {"interrupt", 0, 0, false, false, false, interrupt_handler},
+  {"bank_switch", 0, 0, false, false, false, interrupt_handler},
+  {"fast_interrupt", 0, 0, false, false, false, interrupt_handler},
+  {"function_vector", 1, 1, true,  false, false, function_vector_handler},
+  {0, 0, 0, 0, 0, 0, 0}
+};
+
+#undef TARGET_COMP_TYPE_ATTRIBUTES
+#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
+static int
+m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
+			   const_tree type2 ATTRIBUTE_UNUSED)
+{
+  /* 0=incompatible 1=compatible 2=warning */
+  return 1;
+}
+
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
+static void
+m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
+			tree * attr_ptr ATTRIBUTE_UNUSED)
+{
+  unsigned addr;
+  /* See if we need to make #pragma address variables volatile.  */
+
+  if (TREE_CODE (node) == VAR_DECL)
+    {
+      const char *name = IDENTIFIER_POINTER (DECL_NAME (node));
+      if (m32c_get_pragma_address  (name, &addr))
+	{
+	  TREE_THIS_VOLATILE (node) = true;
+	}
+    }	
+}
+
+
+struct GTY(()) pragma_entry {
+  const char *varname;
+  unsigned address;
+};
+typedef struct pragma_entry pragma_entry;
+
+/* Hash table of pragma info.  */
+static GTY((param_is (pragma_entry))) htab_t pragma_htab;
+
+static int
+pragma_entry_eq (const void *p1, const void *p2)
+{
+  const pragma_entry *old = (const pragma_entry *) p1;
+  const char *new_name = (const char *) p2;
+
+  return strcmp (old->varname, new_name) == 0;
+}
+
+static hashval_t
+pragma_entry_hash (const void *p)
+{
+  const pragma_entry *old = (const pragma_entry *) p;
+  return htab_hash_string (old->varname);
+}
+
+void
+m32c_note_pragma_address (const char *varname, unsigned address)
+{
+  pragma_entry **slot;
+
+  if (!pragma_htab)
+    pragma_htab = htab_create_ggc (31, pragma_entry_hash,
+				    pragma_entry_eq, NULL);
+
+  slot = (pragma_entry **)
+    htab_find_slot_with_hash (pragma_htab, varname,
+			      htab_hash_string (varname), INSERT);
+
+  if (!*slot)
+    {
+      *slot = ggc_alloc_pragma_entry ();
+      (*slot)->varname = ggc_strdup (varname);
+    }
+  (*slot)->address = address;
+}
+
+static bool
+m32c_get_pragma_address (const char *varname, unsigned *address)
+{
+  pragma_entry **slot;
+
+  if (!pragma_htab)
+    return false;
+
+  slot = (pragma_entry **)
+    htab_find_slot_with_hash (pragma_htab, varname,
+			      htab_hash_string (varname), NO_INSERT);
+  if (slot && *slot)
+    {
+      *address = (*slot)->address;
+      return true;
+    }
+  return false;
+}
+
+void
+m32c_output_aligned_common (FILE *stream, tree decl ATTRIBUTE_UNUSED,
+			    const char *name,
+			    int size, int align, int global)
+{
+  unsigned address;
+
+  if (m32c_get_pragma_address (name, &address))
+    {
+      /* We never output these as global.  */
+      assemble_name (stream, name);
+      fprintf (stream, " = 0x%04x\n", address);
+      return;
+    }
+  if (!global)
+    {
+      fprintf (stream, "\t.local\t");
+      assemble_name (stream, name);
+      fprintf (stream, "\n");
+    }
+  fprintf (stream, "\t.comm\t");
+  assemble_name (stream, name);
+  fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT);
+}
+
+/* Predicates */
+
+/* This is a list of legal subregs of hard regs.  */
+static const struct {
+  unsigned char outer_mode_size;
+  unsigned char inner_mode_size;
+  unsigned char byte_mask;
+  unsigned char legal_when;
+  unsigned int regno;
+} legal_subregs[] = {
+  {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
+  {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
+  {1, 2, 0x01, 1, A0_REGNO},
+  {1, 2, 0x01, 1, A1_REGNO},
+
+  {1, 4, 0x01, 1, A0_REGNO},
+  {1, 4, 0x01, 1, A1_REGNO},
+
+  {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
+  {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
+  {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
+  {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
+  {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
+
+  {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
+};
+
+/* Returns TRUE if OP is a subreg of a hard reg which we don't
+   support.  We also bail on MEMs with illegal addresses.  */
+bool
+m32c_illegal_subreg_p (rtx op)
+{
+  int offset;
+  unsigned int i;
+  int src_mode, dest_mode;
+
+  if (GET_CODE (op) == MEM
+      && ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))
+    {
+      return true;
+    }
+
+  if (GET_CODE (op) != SUBREG)
+    return false;
+
+  dest_mode = GET_MODE (op);
+  offset = SUBREG_BYTE (op);
+  op = SUBREG_REG (op);
+  src_mode = GET_MODE (op);
+
+  if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
+    return false;
+  if (GET_CODE (op) != REG)
+    return false;
+  if (REGNO (op) >= MEM0_REGNO)
+    return false;
+
+  offset = (1 << offset);
+
+  for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
+    if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
+	&& legal_subregs[i].regno == REGNO (op)
+	&& legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
+	&& legal_subregs[i].byte_mask & offset)
+      {
+	switch (legal_subregs[i].legal_when)
+	  {
+	  case 1:
+	    return false;
+	  case 16:
+	    if (TARGET_A16)
+	      return false;
+	    break;
+	  case 24:
+	    if (TARGET_A24)
+	      return false;
+	    break;
+	  }
+      }
+  return true;
+}
+
+/* Returns TRUE if we support a move between the first two operands.
+   At the moment, we just want to discourage mem to mem moves until
+   after reload, because reload has a hard time with our limited
+   number of address registers, and we can get into a situation where
+   we need three of them when we only have two.  */
+bool
+m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+
+  if (TARGET_A24)
+    return true;
+
+#define DEBUG_MOV_OK 0
+#if DEBUG_MOV_OK
+  fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
+  debug_rtx (op0);
+  debug_rtx (op1);
+#endif
+
+  if (GET_CODE (op0) == SUBREG)
+    op0 = XEXP (op0, 0);
+  if (GET_CODE (op1) == SUBREG)
+    op1 = XEXP (op1, 0);
+
+  if (GET_CODE (op0) == MEM
+      && GET_CODE (op1) == MEM
+      && ! reload_completed)
+    {
+#if DEBUG_MOV_OK
+      fprintf (stderr, " - no, mem to mem\n");
+#endif
+      return false;
+    }
+
+#if DEBUG_MOV_OK
+  fprintf (stderr, " - ok\n");
+#endif
+  return true;
+}
+
+/* Returns TRUE if two consecutive HImode mov instructions, generated
+   for moving an immediate double data to a double data type variable
+   location, can be combined into single SImode mov instruction.  */
+bool
+m32c_immd_dbl_mov (rtx * operands, 
+		   enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
+  const char *str1;
+  const char *str2;
+
+  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+      && MEM_SCALAR_P (operands[0])
+      && !MEM_IN_STRUCT_P (operands[0])
+      && GET_CODE (XEXP (operands[2], 0)) == CONST
+      && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
+      && MEM_SCALAR_P (operands[2])
+      && !MEM_IN_STRUCT_P (operands[2]))
+    flag = 1; 
+
+  else if (GET_CODE (XEXP (operands[0], 0)) == CONST
+           && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
+           && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
+           && MEM_SCALAR_P (operands[0])
+           && !MEM_IN_STRUCT_P (operands[0])
+           && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
+           && GET_CODE (XEXP (operands[2], 0)) == CONST
+           && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
+           && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
+           && MEM_SCALAR_P (operands[2])
+           && !MEM_IN_STRUCT_P (operands[2]))
+    flag = 2; 
+
+  else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
+           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
+           &&  REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO 
+           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
+           &&  MEM_SCALAR_P (operands[0])
+           &&  !MEM_IN_STRUCT_P (operands[0])
+           &&  !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
+           &&  REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO 
+           &&  GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
+           &&  MEM_SCALAR_P (operands[2])
+           &&  !MEM_IN_STRUCT_P (operands[2]))
+    flag = 3; 
+
+  else
+    return false;
+
+  switch (flag)
+    {
+    case 1:
+      str1 = XSTR (XEXP (operands[0], 0), 0);
+      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
+      if (strcmp (str1, str2) == 0)
+	okflag = 1; 
+      else
+	okflag = 0; 
+      break;
+    case 2:
+      str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
+      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
+      if (strcmp(str1,str2) == 0)
+	okflag = 1; 
+      else
+	okflag = 0; 
+      break; 
+    case 3:
+      offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
+      offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
+      offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
+      if (((offset2-offset1) == 2) && offsetsign != 0)
+	okflag = 1;
+      else 
+	okflag = 0; 
+      break; 
+    default:
+      okflag = 0; 
+    } 
+      
+  if (okflag == 1)
+    {
+      HOST_WIDE_INT val;
+      operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
+
+      val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
+      operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
+     
+      return true;
+    }
+
+  return false;
+}  
+
+/* Expanders */
+
+/* Subregs are non-orthogonal for us, because our registers are all
+   different sizes.  */
+static rtx
+m32c_subreg (enum machine_mode outer,
+	     rtx x, enum machine_mode inner, int byte)
+{
+  int r, nr = -1;
+
+  /* Converting MEMs to different types that are the same size, we
+     just rewrite them.  */
+  if (GET_CODE (x) == SUBREG
+      && SUBREG_BYTE (x) == 0
+      && GET_CODE (SUBREG_REG (x)) == MEM
+      && (GET_MODE_SIZE (GET_MODE (x))
+	  == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
+    {
+      rtx oldx = x;
+      x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
+      MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
+    }
+
+  /* Push/pop get done as smaller push/pops.  */
+  if (GET_CODE (x) == MEM
+      && (GET_CODE (XEXP (x, 0)) == PRE_DEC
+	  || GET_CODE (XEXP (x, 0)) == POST_INC))
+    return gen_rtx_MEM (outer, XEXP (x, 0));
+  if (GET_CODE (x) == SUBREG
+      && GET_CODE (XEXP (x, 0)) == MEM
+      && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
+	  || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
+    return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
+
+  if (GET_CODE (x) != REG)
+    {
+      rtx r = simplify_gen_subreg (outer, x, inner, byte);
+      if (GET_CODE (r) == SUBREG
+	  && GET_CODE (x) == MEM
+	  && MEM_VOLATILE_P (x))
+	{
+	  /* Volatile MEMs don't get simplified, but we need them to
+	     be.  We are little endian, so the subreg byte is the
+	     offset.  */
+	  r = adjust_address_nv (x, outer, byte);
+	}
+      return r;
+    }
+
+  r = REGNO (x);
+  if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
+    return simplify_gen_subreg (outer, x, inner, byte);
+
+  if (IS_MEM_REGNO (r))
+    return simplify_gen_subreg (outer, x, inner, byte);
+
+  /* This is where the complexities of our register layout are
+     described.  */
+  if (byte == 0)
+    nr = r;
+  else if (outer == HImode)
+    {
+      if (r == R0_REGNO && byte == 2)
+	nr = R2_REGNO;
+      else if (r == R0_REGNO && byte == 4)
+	nr = R1_REGNO;
+      else if (r == R0_REGNO && byte == 6)
+	nr = R3_REGNO;
+      else if (r == R1_REGNO && byte == 2)
+	nr = R3_REGNO;
+      else if (r == A0_REGNO && byte == 2)
+	nr = A1_REGNO;
+    }
+  else if (outer == SImode)
+    {
+      if (r == R0_REGNO && byte == 0)
+	nr = R0_REGNO;
+      else if (r == R0_REGNO && byte == 4)
+	nr = R1_REGNO;
+    }
+  if (nr == -1)
+    {
+      fprintf (stderr, "m32c_subreg %s %s %d\n",
+	       mode_name[outer], mode_name[inner], byte);
+      debug_rtx (x);
+      gcc_unreachable ();
+    }
+  return gen_rtx_REG (outer, nr);
+}
+
+/* Used to emit move instructions.  We split some moves,
+   and avoid mem-mem moves.  */
+int
+m32c_prepare_move (rtx * operands, enum machine_mode mode)
+{
+  if (far_addr_space_p (operands[0])
+      && CONSTANT_P (operands[1]))
+    {
+      operands[1] = force_reg (GET_MODE (operands[0]), operands[1]);
+    }
+  if (TARGET_A16 && mode == PSImode)
+    return m32c_split_move (operands, mode, 1);
+  if ((GET_CODE (operands[0]) == MEM)
+      && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
+    {
+      rtx pmv = XEXP (operands[0], 0);
+      rtx dest_reg = XEXP (pmv, 0);
+      rtx dest_mod = XEXP (pmv, 1);
+
+      emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
+      operands[0] = gen_rtx_MEM (mode, dest_reg);
+    }
+  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
+    operands[1] = copy_to_mode_reg (mode, operands[1]);
+  return 0;
+}
+
+#define DEBUG_SPLIT 0
+
+/* Returns TRUE if the given PSImode move should be split.  We split
+   for all r8c/m16c moves, since it doesn't support them, and for
+   POP.L as we can only *push* SImode.  */
+int
+m32c_split_psi_p (rtx * operands)
+{
+#if DEBUG_SPLIT
+  fprintf (stderr, "\nm32c_split_psi_p\n");
+  debug_rtx (operands[0]);
+  debug_rtx (operands[1]);
+#endif
+  if (TARGET_A16)
+    {
+#if DEBUG_SPLIT
+      fprintf (stderr, "yes, A16\n");
+#endif
+      return 1;
+    }
+  if (GET_CODE (operands[1]) == MEM
+      && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
+    {
+#if DEBUG_SPLIT
+      fprintf (stderr, "yes, pop.l\n");
+#endif
+      return 1;
+    }
+#if DEBUG_SPLIT
+  fprintf (stderr, "no, default\n");
+#endif
+  return 0;
+}
+
+/* Split the given move.  SPLIT_ALL is 0 if splitting is optional
+   (define_expand), 1 if it is not optional (define_insn_and_split),
+   and 3 for define_split (alternate api). */
+int
+m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
+{
+  rtx s[4], d[4];
+  int parts, si, di, rev = 0;
+  int rv = 0, opi = 2;
+  enum machine_mode submode = HImode;
+  rtx *ops, local_ops[10];
+
+  /* define_split modifies the existing operands, but the other two
+     emit new insns.  OPS is where we store the operand pairs, which
+     we emit later.  */
+  if (split_all == 3)
+    ops = operands;
+  else
+    ops = local_ops;
+
+  /* Else HImode.  */
+  if (mode == DImode)
+    submode = SImode;
+
+  /* Before splitting mem-mem moves, force one operand into a
+     register.  */
+  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
+    {
+#if DEBUG0
+      fprintf (stderr, "force_reg...\n");
+      debug_rtx (operands[1]);
+#endif
+      operands[1] = force_reg (mode, operands[1]);
+#if DEBUG0
+      debug_rtx (operands[1]);
+#endif
+    }
+
+  parts = 2;
+
+#if DEBUG_SPLIT
+  fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
+	   split_all);
+  debug_rtx (operands[0]);
+  debug_rtx (operands[1]);
+#endif
+
+  /* Note that split_all is not used to select the api after this
+     point, so it's safe to set it to 3 even with define_insn.  */
+  /* None of the chips can move SI operands to sp-relative addresses,
+     so we always split those.  */
+  if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
+    split_all = 3;
+
+  if (TARGET_A16
+      && (far_addr_space_p (operands[0])
+	  || far_addr_space_p (operands[1])))
+    split_all |= 1;
+
+  /* We don't need to split these.  */
+  if (TARGET_A24
+      && split_all != 3
+      && (mode == SImode || mode == PSImode)
+      && !(GET_CODE (operands[1]) == MEM
+	   && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
+    return 0;
+
+  /* First, enumerate the subregs we'll be dealing with.  */
+  for (si = 0; si < parts; si++)
+    {
+      d[si] =
+	m32c_subreg (submode, operands[0], mode,
+		     si * GET_MODE_SIZE (submode));
+      s[si] =
+	m32c_subreg (submode, operands[1], mode,
+		     si * GET_MODE_SIZE (submode));
+    }
+
+  /* Split pushes by emitting a sequence of smaller pushes.  */
+  if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
+    {
+      for (si = parts - 1; si >= 0; si--)
+	{
+	  ops[opi++] = gen_rtx_MEM (submode,
+				    gen_rtx_PRE_DEC (Pmode,
+						     gen_rtx_REG (Pmode,
+								  SP_REGNO)));
+	  ops[opi++] = s[si];
+	}
+
+      rv = 1;
+    }
+  /* Likewise for pops.  */
+  else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
+    {
+      for (di = 0; di < parts; di++)
+	{
+	  ops[opi++] = d[di];
+	  ops[opi++] = gen_rtx_MEM (submode,
+				    gen_rtx_POST_INC (Pmode,
+						      gen_rtx_REG (Pmode,
+								   SP_REGNO)));
+	}
+      rv = 1;
+    }
+  else if (split_all)
+    {
+      /* if d[di] == s[si] for any di < si, we'll early clobber. */
+      for (di = 0; di < parts - 1; di++)
+	for (si = di + 1; si < parts; si++)
+	  if (reg_mentioned_p (d[di], s[si]))
+	    rev = 1;
+
+      if (rev)
+	for (si = 0; si < parts; si++)
+	  {
+	    ops[opi++] = d[si];
+	    ops[opi++] = s[si];
+	  }
+      else
+	for (si = parts - 1; si >= 0; si--)
+	  {
+	    ops[opi++] = d[si];
+	    ops[opi++] = s[si];
+	  }
+      rv = 1;
+    }
+  /* Now emit any moves we may have accumulated.  */
+  if (rv && split_all != 3)
+    {
+      int i;
+      for (i = 2; i < opi; i += 2)
+	emit_move_insn (ops[i], ops[i + 1]);
+    }
+  return rv;
+}
+
+/* The m32c has a number of opcodes that act like memcpy, strcmp, and
+   the like.  For the R8C they expect one of the addresses to be in
+   R1L:An so we need to arrange for that.  Otherwise, it's just a
+   matter of picking out the operands we want and emitting the right
+   pattern for them.  All these expanders, which correspond to
+   patterns in blkmov.md, must return nonzero if they expand the insn,
+   or zero if they should FAIL.  */
+
+/* This is a memset() opcode.  All operands are implied, so we need to
+   arrange for them to be in the right registers.  The opcode wants
+   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
+   the count (HI), and $2 the value (QI).  */
+int
+m32c_expand_setmemhi(rtx *operands)
+{
+  rtx desta, count, val;
+  rtx desto, counto;
+
+  desta = XEXP (operands[0], 0);
+  count = operands[1];
+  val = operands[2];
+
+  desto = gen_reg_rtx (Pmode);
+  counto = gen_reg_rtx (HImode);
+
+  if (GET_CODE (desta) != REG
+      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
+    desta = copy_to_mode_reg (Pmode, desta);
+
+  /* This looks like an arbitrary restriction, but this is by far the
+     most common case.  For counts 8..14 this actually results in
+     smaller code with no speed penalty because the half-sized
+     constant can be loaded with a shorter opcode.  */
+  if (GET_CODE (count) == CONST_INT
+      && GET_CODE (val) == CONST_INT
+      && ! (INTVAL (count) & 1)
+      && (INTVAL (count) > 1)
+      && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
+    {
+      unsigned v = INTVAL (val) & 0xff;
+      v = v | (v << 8);
+      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
+      val = copy_to_mode_reg (HImode, GEN_INT (v));
+      if (TARGET_A16)
+	emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
+      else
+	emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
+      return 1;
+    }
+
+  /* This is the generalized memset() case.  */
+  if (GET_CODE (val) != REG
+      || REGNO (val) < FIRST_PSEUDO_REGISTER)
+    val = copy_to_mode_reg (QImode, val);
+
+  if (GET_CODE (count) != REG
+      || REGNO (count) < FIRST_PSEUDO_REGISTER)
+    count = copy_to_mode_reg (HImode, count);
+
+  if (TARGET_A16)
+    emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
+  else
+    emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
+
+  return 1;
+}
+
+/* This is a memcpy() opcode.  All operands are implied, so we need to
+   arrange for them to be in the right registers.  The opcode wants
+   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
+   is the source (MEM:BLK), and $2 the count (HI).  */
+int
+m32c_expand_movmemhi(rtx *operands)
+{
+  rtx desta, srca, count;
+  rtx desto, srco, counto;
+
+  desta = XEXP (operands[0], 0);
+  srca = XEXP (operands[1], 0);
+  count = operands[2];
+
+  desto = gen_reg_rtx (Pmode);
+  srco = gen_reg_rtx (Pmode);
+  counto = gen_reg_rtx (HImode);
+
+  if (GET_CODE (desta) != REG
+      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
+    desta = copy_to_mode_reg (Pmode, desta);
+
+  if (GET_CODE (srca) != REG
+      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
+    srca = copy_to_mode_reg (Pmode, srca);
+
+  /* Similar to setmem, but we don't need to check the value.  */
+  if (GET_CODE (count) == CONST_INT
+      && ! (INTVAL (count) & 1)
+      && (INTVAL (count) > 1))
+    {
+      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
+      if (TARGET_A16)
+	emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
+      else
+	emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
+      return 1;
+    }
+
+  /* This is the generalized memset() case.  */
+  if (GET_CODE (count) != REG
+      || REGNO (count) < FIRST_PSEUDO_REGISTER)
+    count = copy_to_mode_reg (HImode, count);
+
+  if (TARGET_A16)
+    emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
+  else
+    emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
+
+  return 1;
+}
+
+/* This is a stpcpy() opcode.  $0 is the destination (MEM:BLK) after
+   the copy, which should point to the NUL at the end of the string,
+   $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
+   Since our opcode leaves the destination pointing *after* the NUL,
+   we must emit an adjustment.  */
+int
+m32c_expand_movstr(rtx *operands)
+{
+  rtx desta, srca;
+  rtx desto, srco;
+
+  desta = XEXP (operands[1], 0);
+  srca = XEXP (operands[2], 0);
+
+  desto = gen_reg_rtx (Pmode);
+  srco = gen_reg_rtx (Pmode);
+
+  if (GET_CODE (desta) != REG
+      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
+    desta = copy_to_mode_reg (Pmode, desta);
+
+  if (GET_CODE (srca) != REG
+      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
+    srca = copy_to_mode_reg (Pmode, srca);
+
+  emit_insn (gen_movstr_op (desto, srco, desta, srca));
+  /* desto ends up being a1, which allows this type of add through MOVA.  */
+  emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
+
+  return 1;
+}
+
+/* This is a strcmp() opcode.  $0 is the destination (HI) which holds
+   <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
+   $2 is the other (MEM:BLK).  We must do the comparison, and then
+   convert the flags to a signed integer result.  */
+int
+m32c_expand_cmpstr(rtx *operands)
+{
+  rtx src1a, src2a;
+
+  src1a = XEXP (operands[1], 0);
+  src2a = XEXP (operands[2], 0);
+
+  if (GET_CODE (src1a) != REG
+      || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
+    src1a = copy_to_mode_reg (Pmode, src1a);
+
+  if (GET_CODE (src2a) != REG
+      || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
+    src2a = copy_to_mode_reg (Pmode, src2a);
+
+  emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
+  emit_insn (gen_cond_to_int (operands[0]));
+
+  return 1;
+}
+
+
+typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
+
+static shift_gen_func
+shift_gen_func_for (int mode, int code)
+{
+#define GFF(m,c,f) if (mode == m && code == c) return f
+  GFF(QImode,  ASHIFT,   gen_ashlqi3_i);
+  GFF(QImode,  ASHIFTRT, gen_ashrqi3_i);
+  GFF(QImode,  LSHIFTRT, gen_lshrqi3_i);
+  GFF(HImode,  ASHIFT,   gen_ashlhi3_i);
+  GFF(HImode,  ASHIFTRT, gen_ashrhi3_i);
+  GFF(HImode,  LSHIFTRT, gen_lshrhi3_i);
+  GFF(PSImode, ASHIFT,   gen_ashlpsi3_i);
+  GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
+  GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
+  GFF(SImode,  ASHIFT,   TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
+  GFF(SImode,  ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
+  GFF(SImode,  LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
+#undef GFF
+  gcc_unreachable ();
+}
+
+/* The m32c only has one shift, but it takes a signed count.  GCC
+   doesn't want this, so we fake it by negating any shift count when
+   we're pretending to shift the other way.  Also, the shift count is
+   limited to -8..8.  It's slightly better to use two shifts for 9..15
+   than to load the count into r1h, so we do that too.  */
+int
+m32c_prepare_shift (rtx * operands, int scale, int shift_code)
+{
+  enum machine_mode mode = GET_MODE (operands[0]);
+  shift_gen_func func = shift_gen_func_for (mode, shift_code);
+  rtx temp;
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
+      int count = INTVAL (operands[2]) * scale;
+
+      while (count > maxc)
+	{
+	  temp = gen_reg_rtx (mode);
+	  emit_insn (func (temp, operands[1], GEN_INT (maxc)));
+	  operands[1] = temp;
+	  count -= maxc;
+	}
+      while (count < -maxc)
+	{
+	  temp = gen_reg_rtx (mode);
+	  emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
+	  operands[1] = temp;
+	  count += maxc;
+	}
+      emit_insn (func (operands[0], operands[1], GEN_INT (count)));
+      return 1;
+    }
+
+  temp = gen_reg_rtx (QImode);
+  if (scale < 0)
+    /* The pattern has a NEG that corresponds to this. */
+    emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
+  else if (TARGET_A16 && mode == SImode)
+    /* We do this because the code below may modify this, we don't
+       want to modify the origin of this value.  */
+    emit_move_insn (temp, operands[2]);
+  else
+    /* We'll only use it for the shift, no point emitting a move.  */
+    temp = operands[2];
+
+  if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
+    {
+      /* The m16c has a limit of -16..16 for SI shifts, even when the
+	 shift count is in a register.  Since there are so many targets
+	 of these shifts, it's better to expand the RTL here than to
+	 call a helper function.
+
+	 The resulting code looks something like this:
+
+		cmp.b	r1h,-16
+		jge.b	1f
+		shl.l	-16,dest
+		add.b	r1h,16
+	1f:	cmp.b	r1h,16
+		jle.b	1f
+		shl.l	16,dest
+		sub.b	r1h,16
+	1f:	shl.l	r1h,dest
+
+	 We take advantage of the fact that "negative" shifts are
+	 undefined to skip one of the comparisons.  */
+
+      rtx count;
+      rtx label, insn, tempvar;
+
+      emit_move_insn (operands[0], operands[1]);
+
+      count = temp;
+      label = gen_label_rtx ();
+      LABEL_NUSES (label) ++;
+
+      tempvar = gen_reg_rtx (mode);
+
+      if (shift_code == ASHIFT)
+	{
+	  /* This is a left shift.  We only need check positive counts.  */
+	  emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
+					  count, GEN_INT (16), label));
+	  emit_insn (func (tempvar, operands[0], GEN_INT (8)));
+	  emit_insn (func (operands[0], tempvar, GEN_INT (8)));
+	  insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
+	  emit_label_after (label, insn);
+	}
+      else
+	{
+	  /* This is a right shift.  We only need check negative counts.  */
+	  emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
+					  count, GEN_INT (-16), label));
+	  emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
+	  emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
+	  insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
+	  emit_label_after (label, insn);
+	}
+      operands[1] = operands[0];
+      emit_insn (func (operands[0], operands[0], count));
+      return 1;
+    }
+
+  operands[2] = temp;
+  return 0;
+}
+
+/* The m32c has a limited range of operations that work on PSImode
+   values; we have to expand to SI, do the math, and truncate back to
+   PSI.  Yes, this is expensive, but hopefully gcc will learn to avoid
+   those cases.  */
+void
+m32c_expand_neg_mulpsi3 (rtx * operands)
+{
+  /* operands: a = b * i */
+  rtx temp1; /* b as SI */
+  rtx scale /* i as SI */;
+  rtx temp2; /* a*b as SI */
+
+  temp1 = gen_reg_rtx (SImode);
+  temp2 = gen_reg_rtx (SImode);
+  if (GET_CODE (operands[2]) != CONST_INT)
+    {
+      scale = gen_reg_rtx (SImode);
+      emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
+    }
+  else
+    scale = copy_to_mode_reg (SImode, operands[2]);
+
+  emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
+  temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
+  emit_insn (gen_truncsipsi2 (operands[0], temp2));
+}
+
+/* Pattern Output Functions */
+
+int
+m32c_expand_movcc (rtx *operands)
+{
+  rtx rel = operands[1];
+
+  if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
+    return 1;
+  if (GET_CODE (operands[2]) != CONST_INT
+      || GET_CODE (operands[3]) != CONST_INT)
+    return 1;
+  if (GET_CODE (rel) == NE)
+    {
+      rtx tmp = operands[2];
+      operands[2] = operands[3];
+      operands[3] = tmp;
+      rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
+    }
+
+  emit_move_insn (operands[0],
+		  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
+					rel,
+					operands[2],
+					operands[3]));
+  return 0;
+}
+
+/* Used for the "insv" pattern.  Return nonzero to fail, else done.  */
+int
+m32c_expand_insv (rtx *operands)
+{
+  rtx op0, src0, p;
+  int mask;
+
+  if (INTVAL (operands[1]) != 1)
+    return 1;
+
+  /* Our insv opcode (bset, bclr) can only insert a one-bit constant.  */
+  if (GET_CODE (operands[3]) != CONST_INT)
+    return 1;
+  if (INTVAL (operands[3]) != 0
+      && INTVAL (operands[3]) != 1
+      && INTVAL (operands[3]) != -1)
+    return 1;
+
+  mask = 1 << INTVAL (operands[2]);
+
+  op0 = operands[0];
+  if (GET_CODE (op0) == SUBREG
+      && SUBREG_BYTE (op0) == 0)
+    {
+      rtx sub = SUBREG_REG (op0);
+      if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
+	op0 = sub;
+    }
+
+  if (!can_create_pseudo_p ()
+      || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
+    src0 = op0;
+  else
+    {
+      src0 = gen_reg_rtx (GET_MODE (op0));
+      emit_move_insn (src0, op0);
+    }
+
+  if (GET_MODE (op0) == HImode
+      && INTVAL (operands[2]) >= 8
+      && GET_CODE (op0) == MEM)
+    {
+      /* We are little endian.  */
+      rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
+      MEM_COPY_ATTRIBUTES (new_mem, op0);
+      mask >>= 8;
+    }
+
+  /* First, we generate a mask with the correct polarity.  If we are
+     storing a zero, we want an AND mask, so invert it.  */
+  if (INTVAL (operands[3]) == 0)
+    {
+      /* Storing a zero, use an AND mask */
+      if (GET_MODE (op0) == HImode)
+	mask ^= 0xffff;
+      else
+	mask ^= 0xff;
+    }
+  /* Now we need to properly sign-extend the mask in case we need to
+     fall back to an AND or OR opcode.  */
+  if (GET_MODE (op0) == HImode)
+    {
+      if (mask & 0x8000)
+	mask -= 0x10000;
+    }
+  else
+    {
+      if (mask & 0x80)
+	mask -= 0x100;
+    }
+
+  switch (  (INTVAL (operands[3]) ? 4 : 0)
+	  + ((GET_MODE (op0) == HImode) ? 2 : 0)
+	  + (TARGET_A24 ? 1 : 0))
+    {
+    case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
+    case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
+    case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
+    case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
+    case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
+    case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
+    case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
+    case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
+    default: p = NULL_RTX; break; /* Not reached, but silences a warning.  */
+    }
+
+  emit_insn (p);
+  return 0;
+}
+
+const char *
+m32c_scc_pattern(rtx *operands, RTX_CODE code)
+{
+  static char buf[30];
+  if (GET_CODE (operands[0]) == REG
+      && REGNO (operands[0]) == R0_REGNO)
+    {
+      if (code == EQ)
+	return "stzx\t#1,#0,r0l";
+      if (code == NE)
+	return "stzx\t#0,#1,r0l";
+    }
+  sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
+  return buf;
+}
+
+/* Encode symbol attributes of a SYMBOL_REF into its
+   SYMBOL_REF_FLAGS. */
+static void
+m32c_encode_section_info (tree decl, rtx rtl, int first)
+{
+  int extra_flags = 0;
+
+  default_encode_section_info (decl, rtl, first);
+  if (TREE_CODE (decl) == FUNCTION_DECL
+      && m32c_special_page_vector_p (decl))
+
+    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
+
+  if (extra_flags)
+    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
+}
+
+/* Returns TRUE if the current function is a leaf, and thus we can
+   determine which registers an interrupt function really needs to
+   save.  The logic below is mostly about finding the insn sequence
+   that's the function, versus any sequence that might be open for the
+   current insn.  */
+static int
+m32c_leaf_function_p (void)
+{
+  rtx saved_first, saved_last;
+  struct sequence_stack *seq;
+  int rv;
+
+  saved_first = crtl->emit.x_first_insn;
+  saved_last = crtl->emit.x_last_insn;
+  for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
+    ;
+  if (seq)
+    {
+      crtl->emit.x_first_insn = seq->first;
+      crtl->emit.x_last_insn = seq->last;
+    }
+
+  rv = leaf_function_p ();
+
+  crtl->emit.x_first_insn = saved_first;
+  crtl->emit.x_last_insn = saved_last;
+  return rv;
+}
+
+/* Returns TRUE if the current function needs to use the ENTER/EXIT
+   opcodes.  If the function doesn't need the frame base or stack
+   pointer, it can use the simpler RTS opcode.  */
+static bool
+m32c_function_needs_enter (void)
+{
+  rtx insn;
+  struct sequence_stack *seq;
+  rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
+  rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
+
+  insn = get_insns ();
+  for (seq = crtl->emit.sequence_stack;
+       seq;
+       insn = seq->first, seq = seq->next);
+
+  while (insn)
+    {
+      if (reg_mentioned_p (sp, insn))
+	return true;
+      if (reg_mentioned_p (fb, insn))
+	return true;
+      insn = NEXT_INSN (insn);
+    }
+  return false;
+}
+
+/* Mark all the subexpressions of the PARALLEL rtx PAR as
+   frame-related.  Return PAR.
+
+   dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
+   PARALLEL rtx other than the first if they do not have the
+   FRAME_RELATED flag set on them.  So this function is handy for
+   marking up 'enter' instructions.  */
+static rtx
+m32c_all_frame_related (rtx par)
+{
+  int len = XVECLEN (par, 0);
+  int i;
+
+  for (i = 0; i < len; i++)
+    F (XVECEXP (par, 0, i));
+
+  return par;
+}
+
+/* Emits the prologue.  See the frame layout comment earlier in this
+   file.  We can reserve up to 256 bytes with the ENTER opcode, beyond
+   that we manually update sp.  */
+void
+m32c_emit_prologue (void)
+{
+  int frame_size, extra_frame_size = 0, reg_save_size;
+  int complex_prologue = 0;
+
+  cfun->machine->is_leaf = m32c_leaf_function_p ();
+  if (interrupt_p (cfun->decl))
+    {
+      cfun->machine->is_interrupt = 1;
+      complex_prologue = 1;
+    }
+  else if (bank_switch_p (cfun->decl))
+    warning (OPT_Wattributes,
+	     "%<bank_switch%> has no effect on non-interrupt functions");
+
+  reg_save_size = m32c_pushm_popm (PP_justcount);
+
+  if (interrupt_p (cfun->decl))
+    {
+      if (bank_switch_p (cfun->decl))
+	emit_insn (gen_fset_b ());
+      else if (cfun->machine->intr_pushm)
+	emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
+    }
+
+  frame_size =
+    m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
+  if (frame_size == 0
+      && !m32c_function_needs_enter ())
+    cfun->machine->use_rts = 1;
+
+  if (frame_size > 254)
+    {
+      extra_frame_size = frame_size - 254;
+      frame_size = 254;
+    }
+  if (cfun->machine->use_rts == 0)
+    F (emit_insn (m32c_all_frame_related
+		  (TARGET_A16
+		   ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
+		   : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
+
+  if (extra_frame_size)
+    {
+      complex_prologue = 1;
+      if (TARGET_A16)
+	F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
+				  gen_rtx_REG (HImode, SP_REGNO),
+				  GEN_INT (-extra_frame_size))));
+      else
+	F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
+				   gen_rtx_REG (PSImode, SP_REGNO),
+				   GEN_INT (-extra_frame_size))));
+    }
+
+  complex_prologue += m32c_pushm_popm (PP_pushm);
+
+  /* This just emits a comment into the .s file for debugging.  */
+  if (complex_prologue)
+    emit_insn (gen_prologue_end ());
+}
+
+/* Likewise, for the epilogue.  The only exception is that, for
+   interrupts, we must manually unwind the frame as the REIT opcode
+   doesn't do that.  */
+void
+m32c_emit_epilogue (void)
+{
+  /* This just emits a comment into the .s file for debugging.  */
+  if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
+    emit_insn (gen_epilogue_start ());
+
+  m32c_pushm_popm (PP_popm);
+
+  if (cfun->machine->is_interrupt)
+    {
+      enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
+
+      /* REIT clears B flag and restores $fp for us, but we still
+	 have to fix up the stack.  USE_RTS just means we didn't
+	 emit ENTER.  */
+      if (!cfun->machine->use_rts)
+	{
+	  emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
+			  gen_rtx_REG (spmode, FP_REGNO));
+	  emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
+			  gen_rtx_REG (spmode, A0_REGNO));
+	  /* We can't just add this to the POPM because it would be in
+	     the wrong order, and wouldn't fix the stack if we're bank
+	     switching.  */
+	  if (TARGET_A16)
+	    emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
+	  else
+	    emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
+	}
+      if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
+	emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
+
+      /* The FREIT (Fast REturn from InTerrupt) instruction should be
+         generated only for M32C/M32CM targets (generate the REIT
+         instruction otherwise).  */
+      if (fast_interrupt_p (cfun->decl))
+        {
+          /* Check if fast_attribute is set for M32C or M32CM.  */
+          if (TARGET_A24)
+            {
+              emit_jump_insn (gen_epilogue_freit ());
+            }
+          /* If fast_interrupt attribute is set for an R8C or M16C
+             target ignore this attribute and generated REIT
+             instruction.  */
+          else
+	    {
+	      warning (OPT_Wattributes,
+		       "%<fast_interrupt%> attribute directive ignored");
+	      emit_jump_insn (gen_epilogue_reit_16 ());
+	    }
+        }
+      else if (TARGET_A16)
+	emit_jump_insn (gen_epilogue_reit_16 ());
+      else
+	emit_jump_insn (gen_epilogue_reit_24 ());
+    }
+  else if (cfun->machine->use_rts)
+    emit_jump_insn (gen_epilogue_rts ());
+  else if (TARGET_A16)
+    emit_jump_insn (gen_epilogue_exitd_16 ());
+  else
+    emit_jump_insn (gen_epilogue_exitd_24 ());
+  emit_barrier ();
+}
+
+void
+m32c_emit_eh_epilogue (rtx ret_addr)
+{
+  /* R0[R2] has the stack adjustment.  R1[R3] has the address to
+     return to.  We have to fudge the stack, pop everything, pop SP
+     (fudged), and return (fudged).  This is actually easier to do in
+     assembler, so punt to libgcc.  */
+  emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
+  /*  emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
+  emit_barrier ();
+}
+
+/* Indicate which flags must be properly set for a given conditional.  */
+static int
+flags_needed_for_conditional (rtx cond)
+{
+  switch (GET_CODE (cond))
+    {
+    case LE:
+    case GT:
+      return FLAGS_OSZ;
+    case LEU:
+    case GTU:
+      return FLAGS_ZC;
+    case LT:
+    case GE:
+      return FLAGS_OS;
+    case LTU:
+    case GEU:
+      return FLAGS_C;
+    case EQ:
+    case NE:
+      return FLAGS_Z;
+    default:
+      return FLAGS_N;
+    }
+}
+
+#define DEBUG_CMP 0
+
+/* Returns true if a compare insn is redundant because it would only
+   set flags that are already set correctly.  */
+static bool
+m32c_compare_redundant (rtx cmp, rtx *operands)
+{
+  int flags_needed;
+  int pflags;
+  rtx prev, pp, next;
+  rtx op0, op1;
+#if DEBUG_CMP
+  int prev_icode, i;
+#endif
+
+  op0 = operands[0];
+  op1 = operands[1];
+
+#if DEBUG_CMP
+  fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
+  debug_rtx(cmp);
+  for (i=0; i<2; i++)
+    {
+      fprintf(stderr, "operands[%d] = ", i);
+      debug_rtx(operands[i]);
+    }
+#endif
+
+  next = next_nonnote_insn (cmp);
+  if (!next || !INSN_P (next))
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "compare not followed by insn\n");
+      debug_rtx(next);
+#endif
+      return false;
+    }
+  if (GET_CODE (PATTERN (next)) == SET
+      && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
+    {
+      next = XEXP (XEXP (PATTERN (next), 1), 0);
+    }
+  else if (GET_CODE (PATTERN (next)) == SET)
+    {
+      /* If this is a conditional, flags_needed will be something
+	 other than FLAGS_N, which we test below.  */
+      next = XEXP (PATTERN (next), 1);
+    }
+  else
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "compare not followed by conditional\n");
+      debug_rtx(next);
+#endif
+      return false;
+    }
+#if DEBUG_CMP
+  fprintf(stderr, "conditional is: ");
+  debug_rtx(next);
+#endif
+
+  flags_needed = flags_needed_for_conditional (next);
+  if (flags_needed == FLAGS_N)
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "compare not followed by conditional\n");
+      debug_rtx(next);
+#endif
+      return false;
+    }
+
+  /* Compare doesn't set overflow and carry the same way that
+     arithmetic instructions do, so we can't replace those.  */
+  if (flags_needed & FLAGS_OC)
+    return false;
+
+  prev = cmp;
+  do {
+    prev = prev_nonnote_insn (prev);
+    if (!prev)
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "No previous insn.\n");
+#endif
+	return false;
+      }
+    if (!INSN_P (prev))
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "Previous insn is a non-insn.\n");
+#endif
+	return false;
+      }
+    pp = PATTERN (prev);
+    if (GET_CODE (pp) != SET)
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "Previous insn is not a SET.\n");
+#endif
+	return false;
+      }
+    pflags = get_attr_flags (prev);
+
+    /* Looking up attributes of previous insns corrupted the recog
+       tables.  */
+    INSN_UID (cmp) = -1;
+    recog (PATTERN (cmp), cmp, 0);
+
+    if (pflags == FLAGS_N
+	&& reg_mentioned_p (op0, pp))
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "intermediate non-flags insn uses op:\n");
+	debug_rtx(prev);
+#endif
+	return false;
+      }
+
+    /* Check for comparisons against memory - between volatiles and
+       aliases, we just can't risk this one.  */
+    if (GET_CODE (operands[0]) == MEM
+	|| GET_CODE (operands[0]) == MEM)
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "comparisons with memory:\n");
+	debug_rtx(prev);
+#endif
+	return false;
+      }
+
+    /* Check for PREV changing a register that's used to compute a
+       value in CMP, even if it doesn't otherwise change flags.  */
+    if (GET_CODE (operands[0]) == REG
+	&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "sub-value affected, op0:\n");
+	debug_rtx(prev);
+#endif
+	return false;
+      }
+    if (GET_CODE (operands[1]) == REG
+	&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
+      {
+#if DEBUG_CMP
+	fprintf(stderr, "sub-value affected, op1:\n");
+	debug_rtx(prev);
+#endif
+	return false;
+      }
+
+  } while (pflags == FLAGS_N);
+#if DEBUG_CMP
+  fprintf(stderr, "previous flag-setting insn:\n");
+  debug_rtx(prev);
+  debug_rtx(pp);
+#endif
+
+  if (GET_CODE (pp) == SET
+      && GET_CODE (XEXP (pp, 0)) == REG
+      && REGNO (XEXP (pp, 0)) == FLG_REGNO
+      && GET_CODE (XEXP (pp, 1)) == COMPARE)
+    {
+      /* Adjacent cbranches must have the same operands to be
+	 redundant.  */
+      rtx pop0 = XEXP (XEXP (pp, 1), 0);
+      rtx pop1 = XEXP (XEXP (pp, 1), 1);
+#if DEBUG_CMP
+      fprintf(stderr, "adjacent cbranches\n");
+      debug_rtx(pop0);
+      debug_rtx(pop1);
+#endif
+      if (rtx_equal_p (op0, pop0)
+	  && rtx_equal_p (op1, pop1))
+	return true;
+#if DEBUG_CMP
+      fprintf(stderr, "prev cmp not same\n");
+#endif
+      return false;
+    }
+
+  /* Else the previous insn must be a SET, with either the source or
+     dest equal to operands[0], and operands[1] must be zero.  */
+
+  if (!rtx_equal_p (op1, const0_rtx))
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "operands[1] not const0_rtx\n");
+#endif
+      return false;
+    }
+  if (GET_CODE (pp) != SET)
+    {
+#if DEBUG_CMP
+      fprintf (stderr, "pp not set\n");
+#endif
+      return false;
+    }
+  if (!rtx_equal_p (op0, SET_SRC (pp))
+      && !rtx_equal_p (op0, SET_DEST (pp)))
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "operands[0] not found in set\n");
+#endif
+      return false;
+    }
+
+#if DEBUG_CMP
+  fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
+#endif
+  if ((pflags & flags_needed) == flags_needed)
+    return true;
+
+  return false;
+}
+
+/* Return the pattern for a compare.  This will be commented out if
+   the compare is redundant, else a normal pattern is returned.  Thus,
+   the assembler output says where the compare would have been.  */
+char *
+m32c_output_compare (rtx insn, rtx *operands)
+{
+  static char templ[] = ";cmp.b\t%1,%0";
+  /*                             ^ 5  */
+
+  templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
+  if (m32c_compare_redundant (insn, operands))
+    {
+#if DEBUG_CMP
+      fprintf(stderr, "cbranch: cmp not needed\n");
+#endif
+      return templ;
+    }
+
+#if DEBUG_CMP
+  fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
+#endif
+  return templ + 1;
+}
+
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
+
+/* If the frame pointer isn't used, we detect it manually.  But the
+   stack pointer doesn't have as flexible addressing as the frame
+   pointer, so we always assume we have it.  */
+
+#undef TARGET_FRAME_POINTER_REQUIRED
+#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
+
+/* The Global `targetm' Variable. */
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+#include "gt-m32c.h"
diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h
new file mode 100644
index 000000000..9cabeedb8
--- /dev/null
+++ b/gcc/config/m32c/m32c.h
@@ -0,0 +1,688 @@
+/* Target Definitions for R8C/M16C/M32C
+   Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
+   Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_M32C_H
+#define GCC_M32C_H
+
+/* Controlling the Compilation Driver, `gcc'.  */
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
+
+#undef  ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
+
+#undef  LINK_SPEC
+#define LINK_SPEC "%{h*} %{v:-V} \
+		   %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
+
+/* There are four CPU series we support, but they basically break down
+   into two families - the R8C/M16C families, with 16-bit address
+   registers and one set of opcodes, and the M32CM/M32C group, with
+   24-bit address registers and a different set of opcodes.  The
+   assembler doesn't care except for which opcode set is needed; the
+   big difference is in the memory maps, which we cover in
+   LIB_SPEC.  */
+
+#undef  ASM_SPEC
+#define ASM_SPEC "\
+%{mcpu=r8c:--m16c} \
+%{mcpu=m16c:--m16c} \
+%{mcpu=m32cm:--m32c} \
+%{mcpu=m32c:--m32c} "
+
+/* The default is R8C hardware.  We support a simulator, which has its
+   own libgloss and link map, plus one default link map for each chip
+   family.  Most of the logic here is making sure we do the right
+   thing when no CPU is specified, which defaults to R8C.  */
+#undef  LIB_SPEC
+#define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \
+%{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
+       %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
+%{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \
+	       %{mcpu=m32cm:%Tm32cm.ld} \
+	       %{mcpu=m32c:%Tm32c.ld} \
+	       %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
+"
+
+/* Run-time Target Specification */
+
+/* Nothing unusual here.  */
+#define TARGET_CPU_CPP_BUILTINS() \
+  { \
+    builtin_assert ("cpu=m32c"); \
+    builtin_assert ("machine=m32c"); \
+    builtin_define ("__m32c__=1"); \
+    if (TARGET_R8C) \
+      builtin_define ("__r8c_cpu__=1"); \
+    if (TARGET_M16C) \
+      builtin_define ("__m16c_cpu__=1"); \
+    if (TARGET_M32CM) \
+      builtin_define ("__m32cm_cpu__=1"); \
+    if (TARGET_M32C) \
+      builtin_define ("__m32c_cpu__=1"); \
+  }
+
+/* The pragma handlers need to know if we've started processing
+   functions yet, as the memregs pragma should only be given at the
+   beginning of the file.  This variable starts off TRUE and later
+   becomes FALSE.  */
+extern int ok_to_change_target_memregs;
+extern int target_memregs;
+
+/* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
+   use enums or defines for this, this and m32c.opt are the only
+   places that know (or care) what values are being used.  */
+#define TARGET_R8C	(target_cpu == 'r')
+#define TARGET_M16C	(target_cpu == '6')
+#define TARGET_M32CM	(target_cpu == 'm')
+#define TARGET_M32C	(target_cpu == '3')
+
+/* Address register sizes.  Warning: these are used all over the place
+   to select between the two CPU families in general.  */
+#define TARGET_A16	(TARGET_R8C || TARGET_M16C)
+#define TARGET_A24	(TARGET_M32CM || TARGET_M32C)
+
+#define TARGET_VERSION fprintf (stderr, " (m32c)");
+
+/* Defining data structures for per-function information */
+
+typedef struct GTY (()) machine_function
+{
+  /* How much we adjust the stack when returning from an exception
+     handler.  */
+  rtx eh_stack_adjust;
+
+  /* TRUE if the current function is an interrupt handler.  */
+  int is_interrupt;
+
+  /* TRUE if the current function is a leaf function.  Currently, this
+     only affects saving $a0 in interrupt functions.  */
+  int is_leaf;
+
+  /* Bitmask that keeps track of which registers are used in an
+     interrupt function, so we know which ones need to be saved and
+     restored.  */
+  int intr_pushm;
+  /* Likewise, one element for each memreg that needs to be saved.  */
+  char intr_pushmem[16];
+
+  /* TRUE if the current function can use a simple RTS to return, instead
+     of the longer ENTER/EXIT pair.  */
+  int use_rts;
+}
+machine_function;
+
+#define INIT_EXPANDERS m32c_init_expanders ()
+
+/* Storage Layout */
+
+#define BITS_BIG_ENDIAN 0
+#define BYTES_BIG_ENDIAN 0
+#define WORDS_BIG_ENDIAN 0
+
+/* We can do QI, HI, and SI operations pretty much equally well, but
+   GCC expects us to have a "native" format, so we pick the one that
+   matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
+   is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
+   24-bit pointers are stored in 32-bit words.  */
+#define BITS_PER_UNIT 8
+#define UNITS_PER_WORD 2
+#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
+#define POINTERS_EXTEND_UNSIGNED 1
+/* We have a problem with libgcc2.  It only defines two versions of
+   each function, one for "int" and one for "long long".  Ie it assumes
+   that "sizeof (int) == sizeof (long)".  For the M32C this is not true
+   and we need a third set of functions.  We explicitly define
+   LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
+   to get the SI and DI versions from the libgcc2.c sources, and we
+   provide our own set of HI functions in m32c-lib2.c, which is why this
+   definition is surrounded by #ifndef..#endif.  */
+#ifndef LIBGCC2_UNITS_PER_WORD
+#define LIBGCC2_UNITS_PER_WORD 4
+#endif
+
+/* These match the alignment enforced by the two types of stack operations.  */
+#define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
+#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
+
+/* We do this because we care more about space than about speed.  For
+   the chips with 16-bit busses, we could set these to 16 if
+   desired.  */
+#define FUNCTION_BOUNDARY 8
+#define BIGGEST_ALIGNMENT 8
+
+/* Since we have a maximum structure alignment of 8 there
+   is no need to enforce any alignment of bitfield types.  */
+#undef  PCC_BITFIELD_TYPE_MATTERS
+#define PCC_BITFIELD_TYPE_MATTERS 0
+
+#define STRICT_ALIGNMENT 0
+#define SLOW_BYTE_ACCESS 1
+
+/* Layout of Source Language Data Types */
+
+#define INT_TYPE_SIZE 16
+#define SHORT_TYPE_SIZE 16
+#define LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
+
+#define FLOAT_TYPE_SIZE 32
+#define DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+#define DEFAULT_SIGNED_CHAR 1
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
+
+#undef UINTPTR_TYPE
+#define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
+
+#undef  SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef  WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+
+#undef  WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+/* REGISTER USAGE */
+
+/* Register Basics */
+
+/* Register layout:
+
+        [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
+        [--------]  $r2  (16 bits)
+        [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
+        [--------]  $r3  (16 bits)
+   [---][--------]  $a0  (might be 24 bits)
+   [---][--------]  $a1  (might be 24 bits)
+   [---][--------]  $sb  (might be 24 bits)
+   [---][--------]  $fb  (might be 24 bits)
+   [---][--------]  $sp  (might be 24 bits)
+   [-------------]  $pc  (20 or 24 bits)
+             [---]  $flg (CPU flags)
+   [---][--------]  $argp (virtual)
+        [--------]  $mem0 (all 16 bits)
+          . . .
+        [--------]  $mem14
+*/
+
+#define FIRST_PSEUDO_REGISTER   20
+
+/* Note that these two tables are modified based on which CPU family
+   you select; see m32c_conditional_register_usage for details.  */
+
+/* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
+#define FIXED_REGISTERS     { 0, 0, 0, 0, \
+			      0, 0, 1, 0, \
+			      1, 1, 0, 1, \
+			      0, 0, 0, 0, 0, 0, 0, 0 }
+#define CALL_USED_REGISTERS { 1, 1, 1, 1, \
+			      1, 1, 1, 0, \
+			      1, 1, 1, 1, \
+			      1, 1, 1, 1, 1, 1, 1, 1 }
+
+/* The *_REGNO theme matches m32c.md and most register number
+   arguments; the PC_REGNUM is the odd one out.  */
+#ifndef PC_REGNO
+#define PC_REGNO 9
+#endif
+#define PC_REGNUM PC_REGNO
+
+/* Order of Allocation of Registers */
+
+#define REG_ALLOC_ORDER { \
+	0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
+        12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */	\
+	6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
+
+/* How Values Fit in Registers */
+
+#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
+#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
+#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
+#define AVOID_CCMODE_COPIES
+
+/* Register Classes */
+
+/* Most registers are special purpose in some form or another, so this
+   table is pretty big.  Class names are used for constraints also;
+   for example the HL_REGS class (HL below) is "Rhl" in the md files.
+   See m32c_reg_class_from_constraint for the mapping.  There's some
+   duplication so that we can better isolate the reason for using
+   constraints in the md files from the actual registers used; for
+   example we may want to exclude a1a0 from SI_REGS in the future,
+   without precluding their use as HImode registers.  */
+
+/* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
+/*       mmPAR */
+#define REG_CLASS_CONTENTS \
+{ { 0x00000000 }, /* NO */\
+  { 0x00000100 }, /* SP  - sp */\
+  { 0x00000080 }, /* FB  - fb */\
+  { 0x00000040 }, /* SB  - sb */\
+  { 0x000001c0 }, /* CR  - sb fb sp */\
+  { 0x00000001 }, /* R0  - r0 */\
+  { 0x00000004 }, /* R1  - r1 */\
+  { 0x00000002 }, /* R2  - r2 */\
+  { 0x00000008 }, /* R3  - r3 */\
+  { 0x00000003 }, /* R02 - r0r2 */\
+  { 0x0000000c }, /* R13 - r1r3 */\
+  { 0x00000005 }, /* HL  - r0 r1 */\
+  { 0x00000005 }, /* QI  - r0 r1 */\
+  { 0x0000000a }, /* R23 - r2 r3 */\
+  { 0x0000000f }, /* R03 - r0r2 r1r3 */\
+  { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
+  { 0x00000010 }, /* A0  - a0 */\
+  { 0x00000020 }, /* A1  - a1 */\
+  { 0x00000030 }, /* A   - a0 a1 */\
+  { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
+  { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
+  { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
+  { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
+  { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
+  { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
+  { 0x0000007f }, /* GENERAL */\
+  { 0x00000400 }, /* FLG */\
+  { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
+  { 0x000ff000 }, /* MEM */\
+  { 0x000ff003 }, /* R02_A_MEM */\
+  { 0x000ff005 }, /* A_HL_MEM */\
+  { 0x000ff00c }, /* R1_R3_A_MEM */\
+  { 0x000ff00f }, /* R03_MEM */\
+  { 0x000ff03f }, /* A_HI_MEM */\
+  { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
+  { 0x000ff1ff }, /* ALL */\
+}
+
+enum reg_class
+{
+  NO_REGS,
+  SP_REGS,
+  FB_REGS,
+  SB_REGS,
+  CR_REGS,
+  R0_REGS,
+  R1_REGS,
+  R2_REGS,
+  R3_REGS,
+  R02_REGS,
+  R13_REGS,
+  HL_REGS,
+  QI_REGS,
+  R23_REGS,
+  R03_REGS,
+  DI_REGS,
+  A0_REGS,
+  A1_REGS,
+  A_REGS,
+  AD_REGS,
+  PS_REGS,
+  SI_REGS,
+  HI_REGS,
+  R02A_REGS,
+  RA_REGS,
+  GENERAL_REGS,
+  FLG_REGS,
+  HC_REGS,
+  MEM_REGS,
+  R02_A_MEM_REGS,
+  A_HL_MEM_REGS,
+  R1_R3_A_MEM_REGS,
+  R03_MEM_REGS,
+  A_HI_MEM_REGS,
+  A_AD_CR_MEM_SI_REGS,
+  ALL_REGS,
+  LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES LIM_REG_CLASSES
+
+#define REG_CLASS_NAMES {\
+"NO_REGS", \
+"SP_REGS", \
+"FB_REGS", \
+"SB_REGS", \
+"CR_REGS", \
+"R0_REGS", \
+"R1_REGS", \
+"R2_REGS", \
+"R3_REGS", \
+"R02_REGS", \
+"R13_REGS", \
+"HL_REGS", \
+"QI_REGS", \
+"R23_REGS", \
+"R03_REGS", \
+"DI_REGS", \
+"A0_REGS", \
+"A1_REGS", \
+"A_REGS", \
+"AD_REGS", \
+"PS_REGS", \
+"SI_REGS", \
+"HI_REGS", \
+"R02A_REGS", \
+"RA_REGS", \
+"GENERAL_REGS", \
+"FLG_REGS", \
+"HC_REGS", \
+"MEM_REGS", \
+"R02_A_MEM_REGS", \
+"A_HL_MEM_REGS", \
+"R1_R3_A_MEM_REGS", \
+"R03_MEM_REGS", \
+"A_HI_MEM_REGS", \
+"A_AD_CR_MEM_SI_REGS", \
+"ALL_REGS", \
+}
+
+#define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
+
+/* We support simple displacements off address registers, nothing else.  */
+#define BASE_REG_CLASS A_REGS
+#define INDEX_REG_CLASS NO_REGS
+
+/* We primarily use the new "long" constraint names, with the initial
+   letter classifying the constraint type and following letters
+   specifying which.  The types are:
+
+   I - integer values
+   R - register classes
+   S - memory references (M was used)
+   A - addresses (currently unused)
+*/
+
+#define CONSTRAINT_LEN(CHAR,STR) \
+	((CHAR) == 'I' ? 3 \
+	 : (CHAR) == 'R' ? 3 \
+	 : (CHAR) == 'S' ? 2 \
+	 : (CHAR) == 'A' ? 2 \
+	 : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
+#define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
+	(enum reg_class) m32c_reg_class_from_constraint (CHAR, STR)
+
+#define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
+#define REGNO_OK_FOR_INDEX_P(NUM) 0
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
+#define LIMIT_RELOAD_CLASS(MODE,CLASS) \
+  (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
+
+#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
+  (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
+
+#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
+
+#define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
+
+#define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
+
+#define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
+	m32c_const_ok_for_constraint_p (VALUE, C, STR)
+#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
+#define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
+	m32c_extra_constraint_p (VALUE, C, STR)
+#define EXTRA_MEMORY_CONSTRAINT(C,STR) \
+	m32c_extra_memory_constraint (C, STR)
+#define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
+	m32c_extra_address_constraint (C, STR)
+
+/* STACK AND CALLING */
+
+/* Frame Layout */
+
+/* Standard push/pop stack, no surprises here.  */
+
+#define STACK_GROWS_DOWNWARD 1
+#define STACK_PUSH_CODE PRE_DEC
+#define FRAME_GROWS_DOWNWARD 1
+
+#define STARTING_FRAME_OFFSET 0
+#define FIRST_PARM_OFFSET(F) 0
+
+#define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
+
+#define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
+#define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
+
+/* Exception Handling Support */
+
+#define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
+#define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
+
+/* Registers That Address the Stack Frame */
+
+#ifndef FP_REGNO
+#define FP_REGNO 7
+#endif
+#ifndef SP_REGNO
+#define SP_REGNO 8
+#endif
+#define AP_REGNO 11
+
+#define STACK_POINTER_REGNUM	SP_REGNO
+#define FRAME_POINTER_REGNUM	FP_REGNO
+#define ARG_POINTER_REGNUM	AP_REGNO
+
+/* The static chain must be pointer-capable.  */
+#define STATIC_CHAIN_REGNUM A0_REGNO
+
+#define DWARF_FRAME_REGISTERS 20
+#define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
+#define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
+
+#undef ASM_PREFERRED_EH_DATA_FORMAT
+/* This is the same as the default in practice, except that by making
+   it explicit we tell binutils what size pointers to use.  */
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
+  (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
+
+/* Eliminating Frame Pointer and Arg Pointer */
+
+#define ELIMINABLE_REGS \
+  {{AP_REGNO, SP_REGNO}, \
+   {AP_REGNO, FB_REGNO}, \
+   {FB_REGNO, SP_REGNO}}
+
+#define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
+	(VAR) = m32c_initial_elimination_offset(FROM,TO)
+
+/* Passing Function Arguments on the Stack */
+
+#define PUSH_ARGS 1
+#define PUSH_ROUNDING(N) m32c_push_rounding (N)
+#define CALL_POPS_ARGS(C) 0
+
+/* Passing Arguments in Registers */
+
+typedef struct m32c_cumulative_args
+{
+  /* For address of return value buffer (structures are returned by
+     passing the address of a buffer as an invisible first argument.
+     This identifies it).  If set, the current parameter will be put
+     on the stack, regardless of type.  */
+  int force_mem;
+  /* First parm is 1, parm 0 is hidden pointer for returning
+     aggregates.  */
+  int parm_num;
+} m32c_cumulative_args;
+
+#define CUMULATIVE_ARGS m32c_cumulative_args
+#define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
+	m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
+#define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
+
+/* How Large Values Are Returned */
+
+#define DEFAULT_PCC_STRUCT_RETURN 1
+
+/* Function Entry and Exit */
+
+#define EXIT_IGNORE_STACK 0
+#define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
+#define EH_USES(REGNO) 0	/* FIXME */
+
+/* Generating Code for Profiling */
+
+#define FUNCTION_PROFILER(FILE,LABELNO)
+
+/* Implementing the Varargs Macros */
+
+/* Trampolines for Nested Functions */
+
+#define TRAMPOLINE_SIZE m32c_trampoline_size ()
+#define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
+
+/* Addressing Modes */
+
+#define HAVE_PRE_DECREMENT 1
+#define HAVE_POST_INCREMENT 1
+#define MAX_REGS_PER_ADDRESS 1
+
+/* This is passed to the macros below, so that they can be implemented
+   in m32c.c.  */
+#ifdef REG_OK_STRICT
+#define REG_OK_STRICT_V 1
+#else
+#define REG_OK_STRICT_V 0
+#endif
+
+#define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
+#define REG_OK_FOR_INDEX_P(X) 0
+
+/* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
+
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
+	if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
+	  goto WIN;
+
+#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
+
+/* Address spaces.  */
+#define ADDR_SPACE_FAR	1
+
+
+/* Condition Code Status */
+
+#define REVERSIBLE_CC_MODE(MODE) 1
+
+/* Dividing the Output into Sections (Texts, Data, ...) */
+
+#define TEXT_SECTION_ASM_OP ".text"
+#define DATA_SECTION_ASM_OP ".data"
+#define BSS_SECTION_ASM_OP ".bss"
+
+#define CTOR_LIST_BEGIN
+#define CTOR_LIST_END
+#define DTOR_LIST_BEGIN
+#define DTOR_LIST_END
+#define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
+#define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
+#define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
+#define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
+
+/* The Overall Framework of an Assembler File */
+
+#define ASM_COMMENT_START ";"
+#define ASM_APP_ON ""
+#define ASM_APP_OFF ""
+
+/* Output and Generation of Labels */
+
+#define GLOBAL_ASM_OP "\t.global\t"
+
+/* Output of Assembler Instructions */
+
+#define REGISTER_NAMES {	\
+  "r0", "r2", "r1", "r3", \
+  "a0", "a1", "sb", "fb", "sp", \
+  "pc", "flg", "argp", \
+  "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
+}
+
+#define ADDITIONAL_REGISTER_NAMES { \
+  {"r0l", 0}, \
+  {"r1l", 2}, \
+  {"r0r2", 0}, \
+  {"r1r3", 2}, \
+  {"a0a1", 4}, \
+  {"r0r2r1r3", 0} }
+
+#define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
+#define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
+#define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
+
+#undef USER_LABEL_PREFIX
+#define USER_LABEL_PREFIX "_"
+
+#define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
+#define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
+
+#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
+	m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
+
+#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
+	m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
+
+
+/* Output of Dispatch Tables */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
+	fprintf (S, "\t.word L%d\n", V)
+
+/* Assembler Commands for Exception Regions */
+
+#define DWARF_CIE_DATA_ALIGNMENT -1
+
+/* Assembler Commands for Alignment */
+
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
+	fprintf (STREAM, "\t.p2align\t%d\n", POWER);
+
+/* Controlling Debugging Information Format */
+
+#define DWARF2_ADDR_SIZE	4
+
+/* Miscellaneous Parameters */
+
+#define HAS_LONG_COND_BRANCH false
+#define HAS_LONG_UNCOND_BRANCH true
+#define CASE_VECTOR_MODE SImode
+#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
+
+#define MOVE_MAX 4
+#define TRULY_NOOP_TRUNCATION(op,ip) 1
+
+#define STORE_FLAG_VALUE 1
+
+/* 16- or 24-bit pointers */
+#define Pmode (TARGET_A16 ? HImode : PSImode)
+#define FUNCTION_MODE QImode
+
+#define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
+
+#endif
diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md
new file mode 100644
index 000000000..739f24c17
--- /dev/null
+++ b/gcc/config/m32c/m32c.md
@@ -0,0 +1,80 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_constants
+  [(R0_REGNO 0)
+   (R2_REGNO 1)
+   (R1_REGNO 2)
+   (R3_REGNO 3)
+
+   (A0_REGNO 4)
+   (A1_REGNO 5)
+   (SB_REGNO 6)
+   (FB_REGNO 7)
+
+   (SP_REGNO 8)
+   (PC_REGNO 9)
+   (FLG_REGNO 10)
+   (MEM0_REGNO 12)
+   (MEM7_REGNO 19)
+   ])
+
+(define_constants
+  [(UNS_PROLOGUE_END 1)
+   (UNS_EPILOGUE_START 2)
+   (UNS_EH_EPILOGUE 3)
+   (UNS_PUSHM 4)
+   (UNS_POPM 5)
+   (UNS_SMOVF 6)
+   (UNS_SSTR 7)
+   (UNS_SCMPU 8)
+   (UNS_SMOVU 9)
+   (UNS_FSETB 10)
+   (UNS_FREIT 11)
+   ])
+
+;; n = no change, x = clobbered.  The first 16 values are chosen such
+;; that the enum has one bit set for each flag.
+(define_attr "flags" "x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n" (const_string "n"))
+(define_asm_attributes [(set_attr "flags" "x")])
+
+(define_mode_iterator QHI [QI HI])
+(define_mode_iterator HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
+(define_mode_iterator QHPSI [QI HI (PSI "TARGET_A24")])
+(define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
+(define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
+
+(define_code_iterator eqne_cond [eq ne])
+
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop"
+  [(set_attr "flags" "n")]
+)
+
+(define_insn "no_insn"
+  [(const_int 1)]
+  ""
+  ""
+  [(set_attr "flags" "n")]
+)
diff --git a/gcc/config/m32c/m32c.opt b/gcc/config/m32c/m32c.opt
new file mode 100644
index 000000000..d19153bbe
--- /dev/null
+++ b/gcc/config/m32c/m32c.opt
@@ -0,0 +1,44 @@
+; Target Options for R8C/M16C/M32C
+; Copyright (C) 2005 2007
+; Free Software Foundation, Inc.
+; Contributed by Red Hat.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published
+; by the Free Software Foundation; either version 3, or (at your
+; option) any later version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3.  If not see
+; <http://www.gnu.org/licenses/>.
+
+msim
+Target
+-msim	Use simulator runtime
+
+mcpu=r8c
+Target RejectNegative Var(target_cpu,'r') Init('r')
+-mcpu=r8c	Compile code for R8C variants
+
+mcpu=m16c
+Target RejectNegative Var(target_cpu,'6')
+-mcpu=m16c	Compile code for M16C variants
+
+mcpu=m32cm
+Target RejectNegative Var(target_cpu,'m')
+-mcpu=m32cm	Compile code for M32CM variants
+
+mcpu=m32c
+Target RejectNegative Var(target_cpu,'3')
+-mcpu=m32c	Compile code for M32C variants
+
+memregs=
+Target RejectNegative Joined Var(target_memregs_string)
+-memregs=	Number of memreg bytes (default: 16, range: 0..16)
diff --git a/gcc/config/m32c/minmax.md b/gcc/config/m32c/minmax.md
new file mode 100644
index 000000000..25be96151
--- /dev/null
+++ b/gcc/config/m32c/minmax.md
@@ -0,0 +1,58 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; min, max
+
+(define_insn "sminqi3"
+  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa")
+	(smin:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+		 (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
+  "TARGET_A24"
+  "min.b\t%2,%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "sminhi3"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+	(smin:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+		 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+  "TARGET_A24"
+  "min.w\t%2,%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "smaxqi3"
+  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm,Raa,Raa")
+	(smax:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
+		 (match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
+  "TARGET_A24"
+  "max.b\t%2,%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "smaxhi3"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
+	(smax:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
+		 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
+  "TARGET_A24"
+  "max.w\t%2,%0"
+  [(set_attr "flags" "n")]
+  )
diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md
new file mode 100644
index 000000000..429807875
--- /dev/null
+++ b/gcc/config/m32c/mov.md
@@ -0,0 +1,491 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; move, push, extend, etc.
+
+;; Be careful to never create an alternative that has memory as both
+;; src and dest, as that makes gcc think that mem-mem moves in general
+;; are supported.  While the chip does support this, it only has two
+;; address registers and sometimes gcc requires more than that.  One
+;; example is code like this: a = *b where both a and b are spilled to
+;; the stack.
+
+(define_insn "mov<mode>_far_op1"
+  [(set (match_operand:QHI 0 "register_operand" "=Rhi")
+	(mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "Ra0"))
+			 (match_operand 2 "immediate_operand" "si"))))
+   ]
+  ""
+  "lde.<bwl>\t%D2[%1],%0"
+  [(set_attr "flags" "sz")]
+  )
+
+(define_insn "mov<mode>_far_op2"
+  [(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "Ra0"))
+			 (match_operand 1 "immediate_operand" "si")))
+	(match_operand:QHI 2 "register_operand"
+			  "=Rhi"))
+   ]
+  ""
+  "ste.<bwl>\t%2,%D1[%0]"
+  [(set_attr "flags" "sz")]
+  )
+
+;; Match push/pop before mov.b for passing char as arg,
+;; e.g. stdlib/efgcvt.c.
+(define_insn "movqi_op"
+  [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
+			  "=SF,Rhi*Rmm, Rqi*Rmm, <,          RqiSd*Rmm, SdSs,    Rqi*Rmm, Sd")
+	(match_operand:QI 1 "m32c_any_operand"
+			  "Rhi*Rmm,SF, iRqi*Rmm, iRqiSd*Rmm, >,         Rqi*Rmm, SdSs,    i"))]
+  "m32c_mov_ok (operands, QImode)"
+  "@
+    lde.b\t%1,%0
+    ste.b\t%1,%0
+    mov.b\t%1,%0
+    push.b\t%1
+    pop.b\t%0
+    mov.b\t%1,%0
+    mov.b\t%1,%0
+    mov.b\t%1,%0"
+  [(set_attr "flags" "sz,sz,sz,*,*,sz,sz,sz")]
+  )
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
+	(match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
+  ""
+  "if (m32c_prepare_move (operands, QImode)) DONE;"
+  )
+
+
+(define_insn "movhi_op"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
+			  "=SF,Rhi*Rmm, Rhi*Rmm,     Sd, SdSs,   *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
+	(match_operand:HI 1 "m32c_any_operand"
+			  " Rhi*Rmm,SF, iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
+  "m32c_mov_ok (operands, HImode)"
+  "@
+   ste.w\t%1,%0
+   lde.w\t%1,%0
+   mov.w\t%1,%0
+   mov.w\t%1,%0
+   mov.w\t%1,%0
+   ldc\t%1,%0
+   stc\t%1,%0
+   push.w\t%1
+   pop.w\t%0
+   pushc\t%1
+   popc\t%0"
+  [(set_attr "flags" "sz,sz,sz,sz,sz,n,n,n,n,n,n")]
+  )
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
+	(match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
+  ""
+  "if (m32c_prepare_move (operands, HImode)) DONE;"
+  )
+
+
+(define_insn "movpsi_op"
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
+			   "=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, RpiRaa*Rmm")
+	(match_operand:PSI 1 "m32c_any_operand"
+			   "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
+  "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
+  "@
+   mov.l:s\t%1,%0
+   mov.l\t%1,%0
+   ldc\t%1,%0
+   stc\t%1,%0
+   push.l\t%1
+   pushc\t%1
+   popc\t%0
+   #"
+  [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
+  )
+
+
+;; The intention here is to combine the add with the move to create an
+;; indexed move.  GCC doesn't always figure this out itself.
+
+(define_peephole2
+  [(set (match_operand:HPSI 0 "register_operand" "")
+	(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
+		   (match_operand:HPSI 2 "immediate_operand" "")))
+   (set (match_operand:QHSI 3 "nonimmediate_operand" "")
+	(mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
+  "REGNO (operands[0]) == REGNO (operands[1])
+   && REGNO (operands[0]) == REGNO (operands[4])
+   && (rtx_equal_p (operands[0], operands[3])
+       || (dead_or_set_p (peep2_next_insn (1), operands[4])
+          && ! reg_mentioned_p (operands[0], operands[3])))"
+  [(set (match_dup 3)
+	(mem:QHSI (plus:HPSI (match_dup 1)
+			     (match_dup 2))))]
+  "")
+
+(define_peephole2
+  [(set (match_operand:HPSI 0 "register_operand" "")
+	(plus:HPSI (match_operand:HPSI 1 "register_operand" "")
+		   (match_operand:HPSI 2 "immediate_operand" "")))
+   (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
+	(match_operand:QHSI 3 "m32c_any_operand" ""))]
+  "REGNO (operands[0]) == REGNO (operands[1])
+   && REGNO (operands[0]) == REGNO (operands[4])
+   && dead_or_set_p (peep2_next_insn (1), operands[4])
+   && ! reg_mentioned_p (operands[0], operands[3])"
+  [(set (mem:QHSI (plus:HPSI (match_dup 1)
+			     (match_dup 2)))
+	(match_dup 3))]
+  "")
+
+; Peephole to generate SImode mov instructions for storing an
+; immediate double data to a memory location.
+(define_peephole2
+  [(set (match_operand:HI 0 "memory_operand" "")
+        (match_operand 1 "const_int_operand" ""))
+   (set (match_operand:HI 2 "memory_operand" "")
+        (match_operand 3 "const_int_operand" ""))]
+   "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
+   [(set (match_dup 4) (match_dup 5))]
+   ""
+)
+
+; Some PSI moves must be split.
+(define_split
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
+	(match_operand:PSI 1 "m32c_any_operand" ""))]
+  "reload_completed && m32c_split_psi_p (operands)"
+  [(set (match_dup 2)
+	(match_dup 3))
+   (set (match_dup 4)
+	(match_dup 5))]
+  "m32c_split_move (operands, PSImode, 3);"
+  )
+
+(define_expand "movpsi"
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
+	(match_operand:PSI 1 "m32c_any_operand" ""))]
+  ""
+  "if (m32c_prepare_move (operands, PSImode)) DONE;"
+  )
+
+
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
+  ""
+  "if (m32c_split_move (operands, SImode, 0)) DONE;"
+  )
+
+; All SI moves are split if TARGET_A16
+(define_insn_and_split "movsi_splittable"
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiRaa<*Rmm,  RsiRaaSd*Rmm,  Ss")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiRaaSd*Rmm,  iRsiRaa>*Rmm,  RsiRaa*Rmm"))]
+  "TARGET_A16"
+  "#"
+  "TARGET_A16"
+  [(pc)]
+  "m32c_split_move (operands, SImode, 1); DONE;"
+  )
+
+; The movsi pattern doesn't always match because sometimes the modes
+; don't match.
+(define_insn "push_a01_l"
+  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+	(match_operand 0 "a_operand" "Raa"))]
+  ""
+  "push.l\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "movsi_24"
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand"  "=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <")
+	(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
+  "TARGET_A24"
+  "@
+   mov.l\t%1,%0
+   mov.l\t%1,%0
+   #
+   push.l\t%1"
+  [(set_attr "flags" "sz,sz,*,n")]
+  )
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
+	(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
+  ""
+  "if (m32c_split_move (operands, DImode, 0)) DONE;"
+  )
+
+(define_insn_and_split "movdi_splittable"
+  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
+	(match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
+  ""
+  "#"
+  "reload_completed"
+  [(pc)]
+  "m32c_split_move (operands, DImode, 1); DONE;"
+  )
+
+
+
+
+(define_insn "pushqi"
+  [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
+        (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
+  ""
+  "push.b\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_expand "pushhi"
+  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
+        (match_operand:HI 0 "" ""))]
+  ""
+  "if (TARGET_A16)
+     gen_pushhi_16 (operands[0]);
+   else
+     gen_pushhi_24 (operands[0]);
+   DONE;"
+  )
+
+(define_insn "pushhi_16"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
+        (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
+  "TARGET_A16"
+  "@
+   push.w\t%0
+   pushc\t%0"
+  [(set_attr "flags" "n,n")]
+  )
+
+(define_insn "pushhi_24"
+  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
+        (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
+  "TARGET_A24"
+  "push.w\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+;(define_insn "pushpi"
+;  [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
+;        (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
+;  "TARGET_A24"
+;  "@
+;   push.l\t%0
+;   pushc\t%0"
+;  )
+
+(define_insn "pushsi"
+  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+        (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
+  "TARGET_A24"
+  "push.l\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_expand "pophi"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
+        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
+  ""
+  "if (TARGET_A16)
+     gen_pophi_16 (operands[0]);
+   else
+     gen_pophi_24 (operands[0]);
+   DONE;"
+  )
+
+(define_insn "pophi_16"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
+        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
+  "TARGET_A16"
+  "@
+   pop.w\t%0
+   popc\t%0"
+  [(set_attr "flags" "n,n")]
+  )
+
+(define_insn "pophi_24"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
+        (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
+  "TARGET_A24"
+  "pop.w\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "poppsi"
+  [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
+        (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
+  "TARGET_A24"
+  "popc\t%0"
+  [(set_attr "flags" "n")]
+  )
+
+
+;; Rhl used here as an HI-mode Rxl
+(define_insn "extendqihi2"
+[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
+	(sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
+  ""
+  "exts.b\t%1"
+  [(set_attr "flags" "sz")]
+  )
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=R03")
+	(sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
+  ""
+  "*
+   if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
+   else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "extendhipsi2"
+  [(set (match_operand:PSI 0 "register_operand" "=R03")
+	(sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
+  ""
+  "*
+   if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
+   else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "extendpsisi2"
+  [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
+	(sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
+  ""
+  "; expand psi %1 to si %0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "zero_extendpsisi2"
+  [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
+	(zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
+  ""
+  "; expand psi %1 to si %0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "zero_extendhipsi2"
+  [(set (match_operand:PSI 0 "register_operand" "=Raa")
+	(truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
+  ""
+  "mov.w\t%1,%0"
+  [(set_attr "flags" "sz")]
+  )
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
+  ""
+  "mov.w\t#0,%H0"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
+  ""
+  "@
+   mov.b\t#0,%H0
+   and.w\t#255,%0"
+  [(set_attr "flags" "x,x")]
+  )
+
+(define_insn "truncsipsi2_16"
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+	(truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
+  "TARGET_A16"
+  "@
+   ; no-op trunc si %1 to psi %0
+   #
+   ldc\t%1,%0
+   stc\t%1,%0"
+  [(set_attr "flags" "n,*,n,n")]
+  )
+
+(define_insn "trunchiqi2"
+  [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
+	(truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
+  ""
+  "; no-op trunc hi %1 to qi %0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "truncsipsi2_24"
+  [(set (match_operand:PSI 0              "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
+	(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
+  "TARGET_A24"
+  "@
+   ; no-op trunc si %1 to psi %0
+   mov.l\t%1,%0
+   ldc\t%1,%0
+   stc\t%1,%0"
+  [(set_attr "flags" "n,sz,n,n")]
+  )
+
+(define_expand "truncsipsi2"
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
+	(truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
+  ""
+  ""
+  )
+
+(define_expand "reload_inqi"
+  [(set (match_operand:QI 2 "" "=&Rqi")
+	(match_operand:QI 1 "" ""))
+   (set (match_operand:QI 0 "" "")
+	(match_dup 2))
+   ]
+  ""
+  "")
+
+(define_expand "reload_outqi"
+  [(set (match_operand:QI 2 "" "=&Rqi")
+	(match_operand:QI 1 "" ""))
+   (set (match_operand:QI 0 "" "")
+	(match_dup 2))
+   ]
+  ""
+  "")
+
+(define_expand "reload_inhi"
+  [(set (match_operand:HI 2 "" "=&Rhi")
+	(match_operand:HI 1 "" ""))
+   (set (match_operand:HI 0 "" "")
+	(match_dup 2))
+   ]
+  ""
+  "")
+
+(define_expand "reload_outhi"
+  [(set (match_operand:HI 2 "" "=&Rhi")
+	(match_operand:HI 1 "" ""))
+   (set (match_operand:HI 0 "" "")
+	(match_dup 2))
+   ]
+  ""
+  "")
diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md
new file mode 100644
index 000000000..17b0b5d18
--- /dev/null
+++ b/gcc/config/m32c/muldiv.md
@@ -0,0 +1,288 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; multiply and divide
+
+; Here is the pattern for the const_int.
+(define_insn "mulqihi3_c"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
+                 (match_operand 2 "immediate_operand" "i,i")))]
+  ""
+  "mul.b\t%2,%1"
+  [(set_attr "flags" "o")]
+)
+
+; Here is the pattern for registers and such.
+(define_insn "mulqihi3_r"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+                 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
+  ""
+  "mul.b\t%2,%1"
+  [(set_attr "flags" "o")]
+)
+
+; Don't try to sign_extend a const_int.  Same for all other multiplies.
+(define_expand "mulqihi3"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+        (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+  ""
+  "{ if (GET_MODE (operands[2]) != VOIDmode)
+      operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
+)
+
+(define_insn "umulqihi3_c"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
+        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
+                 (match_operand 2 "immediate_operand" "i,i")))]
+  ""
+  "mulu.b\t%U2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_insn "umulqihi3_r"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+                 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
+  ""
+  "mulu.b\t%U2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_expand "umulqihi3"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
+        (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
+                 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+  ""
+  "{ if (GET_MODE (operands[2]) != VOIDmode)
+      operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
+)
+
+(define_insn "mulhisi3_c"
+  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
+        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
+                 (match_operand:HI 2 "immediate_operand" "i")))]
+  ""
+  "mul.w\t%2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_insn "mulhisi3_r"
+  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
+        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
+                 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
+  ""
+  "mul.w\t%2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_expand "mulhisi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
+  ""
+  "{ if (GET_MODE (operands[2]) != VOIDmode)
+      operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
+)
+
+(define_insn "umulhisi3_c"
+  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
+                 (match_operand 2 "m32c_const_u16_operand" "i")))]
+  ""
+  "mulu.w\t%u2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_insn "umulhisi3_r"
+  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
+                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
+  ""
+  "mulu.w\t%u2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_expand "umulhisi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
+                 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
+  ""
+  "{ if (GET_MODE (operands[2]) != VOIDmode)
+      operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
+)
+
+
+; GCC expects to be able to multiply pointer-sized integers too, but
+; fortunately it only multiplies by powers of two, although sometimes
+; they're negative.
+(define_insn "mulpsi3_op"
+  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
+	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
+		  (match_operand 2 "m32c_psi_scale" "Ilb")))]
+  "TARGET_A24"
+  "shl.l\t%b2,%0"
+  [(set_attr "flags" "szc")]
+  )
+
+(define_expand "mulpsi3"
+  [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
+	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
+		  (match_operand 2 "m32c_psi_scale" "Ilb")))]
+  "TARGET_A24"
+  "if (GET_CODE (operands[2]) != CONST_INT
+       || ! m32c_psi_scale (operands[2], PSImode))
+     {
+       m32c_expand_neg_mulpsi3 (operands);
+       DONE;
+     }"
+  )
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
+                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "mul.l\t%2,%1"
+  [(set_attr "flags" "o")]
+)
+
+(define_expand "divmodqi4"
+  [(set (match_dup 4)
+	(sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
+   (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
+		   (div:QI (match_dup 4)
+			   (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+	      (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
+		   (mod:QI (match_dup 4) (match_dup 2)))
+	      ])]
+  "0"
+  "operands[4] = gen_reg_rtx (HImode);"
+  )
+
+(define_insn "divmodqi4_n"
+  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+	(div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
+		(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
+	(mod:QI (match_dup 1) (match_dup 2)))
+   ]
+  "0"
+  "div.b\t%2"
+  [(set_attr "flags" "o")]
+  )
+
+(define_expand "udivmodqi4"
+  [(set (match_dup 4)
+	(zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
+   (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+		   (udiv:QI (match_dup 4)
+			   (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+	      (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
+		   (umod:QI (match_dup 4) (match_dup 2)))
+	      ])]
+  "0"
+  "operands[4] = gen_reg_rtx (HImode);"
+  )
+
+(define_insn "udivmodqi4_n"
+  [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
+	(udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
+		(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
+   (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
+	(umod:QI (match_dup 1) (match_dup 2)))
+   ]
+  "0"
+  "divu.b\t%2"
+  [(set_attr "flags" "o")]
+  )
+
+(define_expand "divmodhi4"
+  [(set (match_dup 4)
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
+   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
+		   (div:HI (match_dup 4)
+			   (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
+	      (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
+		   (mod:HI (match_dup 4) (match_dup 2)))
+	      ])]
+  ""
+  "operands[4] = gen_reg_rtx (SImode);"
+  )
+
+(define_insn "divmodhi4_n"
+  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
+	(div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
+		(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
+   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
+	(mod:HI (match_dup 1) (match_dup 2)))
+   ]
+  ""
+  "div.w\t%2"
+  [(set_attr "flags" "o")]
+  )
+
+(define_expand "udivmodhi4"
+  [(set (match_dup 4)
+	(zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
+   (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
+		   (udiv:HI (match_dup 4)
+			   (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
+	      (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
+		   (umod:HI (match_dup 4) (match_dup 2)))
+	      ])]
+  ""
+  "operands[4] = gen_reg_rtx (SImode);"
+  )
+
+(define_insn "udivmodhi4_n"
+  [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
+	(udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
+		(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
+   (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
+	(umod:HI (match_dup 1) (match_dup 2)))
+   ]
+  ""
+  "divu.w\t%2"
+  [(set_attr "flags" "o")]
+  )
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
+                (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "div.l\t%2"
+  [(set_attr "flags" "o")]
+)
+
+(define_insn "udivsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
+                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "divu.l\t%2"
+  [(set_attr "flags" "o")]
+)
+
+
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
new file mode 100644
index 000000000..533f3469c
--- /dev/null
+++ b/gcc/config/m32c/predicates.md
@@ -0,0 +1,299 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008, 2010
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Predicates
+
+; TRUE for any valid operand.  We do this because general_operand
+; refuses to match volatile memory refs.
+
+(define_predicate "m32c_any_operand"
+  (ior (match_operand 0 "general_operand")
+       (match_code "mem,const_int,const_double"))
+  {
+    return ! m32c_illegal_subreg_p (op);
+  }
+)
+
+; Likewise for nonimmediate_operand.
+
+(define_predicate "m32c_nonimmediate_operand"
+  (ior (match_operand 0 "nonimmediate_operand")
+       (match_code "mem"))
+  {
+    return ! m32c_illegal_subreg_p (op);
+  }
+)
+
+; TRUE if the operand is a pseudo-register.
+(define_predicate "m32c_pseudo"
+  (ior (and (match_code "reg")
+	    (match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
+       (and (match_code "subreg")
+	    (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+		 (match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
+       
+
+; Returning true causes many predicates to NOT match.  We allow
+; subregs for type changing, but not for size changing.
+(define_predicate "m32c_wide_subreg"
+  (and (match_code "subreg")
+       (not (match_operand 0 "m32c_pseudo")))
+  {
+    unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op));
+    unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0)));
+    sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+    sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+    return sizeo != sizei;
+  })
+
+; TRUE for r0 through r3, or a pseudo that reload could put in r0
+; through r3 (likewise for the next couple too)
+(define_predicate "r0123_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) <= R3_REGNO"))))
+
+; TRUE for r0
+(define_predicate "m32c_r0_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R0_REGNO"))))
+
+; TRUE for r1
+(define_predicate "m32c_r1_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R1_REGNO"))))
+
+; TRUE for HL_CLASS (r0 or r1)
+(define_predicate "m32c_hl_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO"))))
+
+
+; TRUE for r2
+(define_predicate "m32c_r2_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R2_REGNO"))))
+
+; TRUE for r3
+(define_predicate "m32c_r3_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == R3_REGNO"))))
+
+; TRUE for any general operand except r2.
+(define_predicate "m32c_notr2_operand"
+  (and (match_operand 0 "general_operand")
+       (ior (not (match_code "reg"))
+	    (match_test "REGNO(op) != R2_REGNO"))))
+
+; TRUE for the stack pointer.
+(define_predicate "m32c_sp_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == SP_REGNO"))))
+
+; TRUE for control registers.
+(define_predicate "cr_operand"
+  (match_code "reg")
+  "return (REGNO (op) >= SB_REGNO
+           && REGNO (op) <= FLG_REGNO);")
+
+; TRUE for $a0 or $a1.
+(define_predicate "a_operand"
+  (and (match_code "reg")
+       (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))
+
+; TRUE for $a0 or $a1 or a pseudo
+(define_predicate "ap_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))))
+
+; TRUE for r0 through r3, or a0 or a1.
+(define_predicate "ra_operand"
+  (and (and (match_operand 0 "register_operand" "")
+	    (not (match_operand 1 "cr_operand" "")))
+       (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus TRUE for memory references.
+(define_predicate "mra_operand"
+  (and (and (match_operand 0 "m32c_nonimmediate_operand" "")
+	    (not (match_operand 1 "cr_operand" "")))
+       (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus TRUE for subregs.
+(define_predicate "mras_operand"
+  (and (match_operand 0 "nonimmediate_operand" "")
+       (not (match_operand 1 "cr_operand" ""))))
+
+; As above, but no push/pop operations
+(define_predicate "mra_nopp_operand"
+  (match_operand 0 "mra_operand" "")
+{
+  if (GET_CODE (op) == MEM
+      && (GET_CODE (XEXP (op, 0)) == PRE_DEC
+	  || (GET_CODE (XEXP (op, 0)) == POST_INC)))
+    return 0;
+  return 1;
+})
+
+; TRUE for memory, r0..r3, a0..a1, or immediates.
+(define_predicate "mrai_operand"
+  (and (and (match_operand 0 "m32c_any_operand" "")
+	    (not (match_operand 1 "cr_operand" "")))
+       (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+; Likewise, plus true for subregs.
+(define_predicate "mrasi_operand"
+  (and (match_operand 0 "general_operand" "")
+       (not (match_operand 1 "cr_operand" ""))))
+
+; TRUE for r0..r3 or memory.
+(define_predicate "mr_operand"
+  (and (match_operand 0 "mra_operand" "")
+       (not (match_operand 1 "a_operand" ""))))
+
+; TRUE for a0..a1 or memory.
+(define_predicate "ma_operand"
+  (ior (match_operand 0 "a_operand" "")
+       (match_operand 1 "memory_operand" "")))
+
+; TRUE for memory operands that are not indexed
+(define_predicate "memsym_operand"
+  (and (match_operand 0 "memory_operand" "")
+       (match_test "m32c_extra_constraint_p (op, 'S', \"Si\")")))
+
+; TRUE for memory operands with small integer addresses
+(define_predicate "memimmed_operand"
+  (and (match_operand 0 "memory_operand" "")
+       (match_test "m32c_extra_constraint_p (op, 'S', \"Sp\")")))
+
+; TRUE for r1h.  This is complicated since r1h isn't a register GCC
+; normally knows about.
+(define_predicate "r1h_operand"
+  (match_code "zero_extract")
+  {
+    rtx reg = XEXP (op, 0);
+    rtx size = XEXP (op, 1);
+    rtx pos = XEXP (op, 2);
+    return (GET_CODE (reg) == REG
+	    && REGNO (reg) == R1_REGNO
+	    && GET_CODE (size) == CONST_INT
+	    && INTVAL (size) == 8
+	    && GET_CODE (pos) == CONST_INT
+	    && INTVAL (pos) == 8);
+  })
+
+; TRUE if we can shift by this amount.  Constant shift counts have a
+; limited range.
+(define_predicate "shiftcount_operand"
+  (ior (match_operand 0 "mra_operand" "")
+       (and (match_operand 2 "const_int_operand" "")
+	    (match_test "-8 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 8"))))
+(define_predicate "longshiftcount_operand"
+  (ior (match_operand 0 "mra_operand" "")
+       (and (match_operand 2 "const_int_operand" "")
+	    (match_test "-32 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 32"))))
+
+; TRUE for r0..r3, a0..a1, or sp.
+(define_predicate "mra_or_sp_operand"
+  (and (ior (match_operand 0 "mra_operand")
+	    (match_operand 1 "m32c_sp_operand"))
+       (not (match_operand 2 "m32c_wide_subreg" ""))))
+
+
+; TRUE for r2 or r3.
+(define_predicate "m32c_r2r3_operand"
+  (ior (and (match_code "reg")
+	    (ior (match_test "REGNO(op) == R2_REGNO")
+		 (match_test "REGNO(op) == R3_REGNO")))
+       (and (match_code "subreg")
+	    (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
+
+; Likewise, plus TRUE for a0..a1.
+(define_predicate "m32c_r2r3a_operand"
+  (ior (match_operand 0 "m32c_r2r3_operand" "")
+       (match_operand 0 "a_operand" "")))
+
+; These two are only for movqi - no subreg limit
+(define_predicate "mra_qi_operand"
+  (and (and (match_operand 0 "m32c_nonimmediate_operand" "")
+	    (not (match_operand 1 "cr_operand" "")))
+       (not (match_operand 1 "m32c_r2r3a_operand" ""))))
+
+(define_predicate "mrai_qi_operand"
+  (and (and (match_operand 0 "m32c_any_operand" "")
+	    (not (match_operand 1 "cr_operand" "")))
+       (not (match_operand 1 "m32c_r2r3a_operand" ""))))
+
+(define_predicate "a_qi_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (match_operand 1 "a_operand" "")))
+
+; TRUE for comparisons we support.
+(define_predicate "m32c_cmp_operator"
+  (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu"))
+
+(define_predicate "m32c_eqne_operator"
+  (match_code "eq,ne"))
+
+; TRUE for mem0
+(define_predicate "m32c_mem0_operand"
+  (ior (match_operand 0 "m32c_pseudo" "")
+       (and (match_code "reg")
+	    (match_test "REGNO(op) == MEM0_REGNO"))))
+
+; TRUE for things the call patterns can return.
+(define_predicate "m32c_return_operand"
+  (ior (match_operand 0 "m32c_r0_operand")
+       (ior (match_operand 0 "m32c_mem0_operand")
+	    (match_code "parallel"))))
+
+; TRUE for constants we can multiply pointers by
+(define_predicate "m32c_psi_scale"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
+
+; TRUE for one bit set (bit) or clear (mask) out of N bits.
+
+(define_predicate "m32c_1bit8_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
+
+(define_predicate "m32c_1bit16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilw\")")))
+
+(define_predicate "m32c_1mask8_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"ImB\")")))
+
+(define_predicate "m32c_1mask16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imw\")")))
+
+(define_predicate "m32c_const_u16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 65535")))
diff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md
new file mode 100644
index 000000000..175b2b0ab
--- /dev/null
+++ b/gcc/config/m32c/prologue.md
@@ -0,0 +1,199 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007, 2008
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Prologue and epilogue patterns
+
+(define_expand "prologue"
+  [(const_int 1)]
+  ""
+  "m32c_emit_prologue(); DONE;"
+  )
+
+; For the next two, operands[0] is the amount of stack space we want
+; to reserve.
+
+; We assume dwarf2out will process each set in sequence.
+(define_insn "prologue_enter_16"
+  [(set (mem:HI (plus:HI (reg:HI SP_REGNO) (const_int -2)))
+	(reg:HI FB_REGNO))
+   (set (reg:HI FB_REGNO)
+	(plus:HI (reg:HI SP_REGNO) (const_int -2)))
+   (set (reg:HI SP_REGNO)
+	(minus:HI (reg:HI SP_REGNO)
+	           (match_operand 0 "const_int_operand" "i")))
+   ]
+  "TARGET_A16"
+  {
+    /* This is due to binutils bug gas/4659.  */
+    if (INTVAL (operands[0]) == 2)
+      return "enter\t#0";
+    return "enter\t%0-2";
+  }
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "prologue_enter_24"
+  [(set (mem:SI (plus:PSI (reg:PSI SP_REGNO) (const_int -4)))
+	(reg:SI FB_REGNO))
+   (set (reg:PSI FB_REGNO)
+	(plus:PSI (reg:PSI SP_REGNO) (const_int -4)))
+   (set (reg:PSI SP_REGNO)
+	(minus:PSI (reg:PSI SP_REGNO)
+	           (match_operand 0 "const_int_operand" "i")))
+   ]
+  "TARGET_A24"
+  {
+    /* This is due to binutils bug gas/4659.  */
+    if (INTVAL (operands[0]) == 4)
+      return "enter\t#0";
+    return "enter\t%0-4";
+  }
+  [(set_attr "flags" "x")]
+  )
+
+; Just a comment, for debugging the assembler output.
+(define_insn "prologue_end"
+  [(unspec_volatile [(const_int 0)] UNS_PROLOGUE_END)]
+  ""
+  "; end of prologue"
+  [(set_attr "flags" "n")]
+  )
+
+
+
+(define_expand "epilogue"
+  [(const_int 1)]
+  ""
+  "m32c_emit_epilogue(); DONE;"
+  )
+
+(define_expand "eh_return"
+  [(match_operand:PSI 0 "" "")]
+  ""
+  "m32c_emit_eh_epilogue(operands[0]); DONE;"
+  )
+
+(define_insn "eh_epilogue"
+  [(set (pc)
+	(unspec_volatile [(match_operand 0 "m32c_r1_operand" "")
+			  (match_operand 1 "m32c_r0_operand" "")
+			  ] UNS_EH_EPILOGUE))]
+  ""
+  "jmp.a\t__m32c_eh_return"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_exitd_16"
+  [(set (reg:HI SP_REGNO)
+	(plus:HI (reg:HI FB_REGNO)
+	      (const_int 2)))
+   (set (reg:HI FB_REGNO)
+	(mem:HI (reg:HI FB_REGNO)))
+   (return)
+   ]
+  "TARGET_A16"
+  "exitd"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_reit_16"
+  [(set (reg:HI SP_REGNO)
+	(plus:HI (reg:HI SP_REGNO)
+	      (const_int 4)))
+   (return)
+   ]
+  "TARGET_A16"
+  "reit"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_exitd_24"
+  [(set (reg:PSI SP_REGNO)
+	(plus:PSI (reg:PSI FB_REGNO)
+	      (const_int 4)))
+   (set (reg:PSI FB_REGNO)
+	(mem:PSI (reg:PSI FB_REGNO)))
+   (return)
+   ]
+  "TARGET_A24"
+  "exitd"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_reit_24"
+  [(set (reg:PSI SP_REGNO)
+	(plus:PSI (reg:PSI SP_REGNO)
+	      (const_int 6)))
+   (return)
+   ]
+  "TARGET_A24"
+  "reit"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_freit"
+  [(unspec [(const_int 0)] UNS_FREIT)
+   (return)
+   ]
+  ""
+  "freit"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_rts"
+  [(return)
+   ]
+  ""
+  "rts"
+  [(set_attr "flags" "x")]
+  )
+
+(define_insn "epilogue_start"
+  [(unspec_volatile [(const_int 0)] UNS_EPILOGUE_START)]
+  ""
+  "; start of epilogue"
+  [(set_attr "flags" "n")]
+  )
+
+
+; These are used by the prologue/epilogue code.
+
+(define_insn "pushm"
+  [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_PUSHM)]
+  ""
+  "pushm\t%p0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "popm"
+  [(unspec [(match_operand 0 "const_int_operand" "i")] UNS_POPM)]
+  ""
+  "popm\t%p0"
+  [(set_attr "flags" "n")]
+  )
+
+(define_insn "fset_b"
+  [(unspec [(const_int 0)] UNS_FSETB)]
+  ""
+  "fset\tB"
+  [(set_attr "flags" "n")]
+  )
+
diff --git a/gcc/config/m32c/rtems.h b/gcc/config/m32c/rtems.h
new file mode 100644
index 000000000..1ef2aada6
--- /dev/null
+++ b/gcc/config/m32c/rtems.h
@@ -0,0 +1,33 @@
+/* Definitions for rtems targeting a M32C using ELF.
+   Copyright (C) 2008, Free Software Foundation, Inc.
+   Contributed by Joel Sherrill (joel@OARcorp.com).
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/* Target OS builtins.  */
+#undef TARGET_OS_CPP_BUILTINS
+#define TARGET_OS_CPP_BUILTINS()		\
+  do						\
+    {						\
+	builtin_define ("__rtems__");		\
+	builtin_define ("__USE_INIT_FINI__");	\
+	builtin_assert ("system=rtems");	\
+    }						\
+  while (0)
+
+/* Use the default */
+#undef LINK_GCC_C_SEQUENCE_SPEC
diff --git a/gcc/config/m32c/shift.md b/gcc/config/m32c/shift.md
new file mode 100644
index 000000000..b4c6bafa3
--- /dev/null
+++ b/gcc/config/m32c/shift.md
@@ -0,0 +1,352 @@
+;; Machine Descriptions for R8C/M16C/M32C
+;; Copyright (C) 2005, 2007
+;; Free Software Foundation, Inc.
+;; Contributed by Red Hat.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; bit shifting
+
+; Shifts are unusual for m32c.  We only support shifting in one
+; "direction" but the shift count is signed.  Also, immediate shift
+; counts have a limited range, and variable shift counts have to be in
+; $r1h which GCC normally doesn't even know about.
+
+; Other than compensating for the above, the patterns below are pretty
+; straightforward.
+
+(define_insn "ashlqi3_i"
+  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+	(ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
+		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   sha.b\t%2,%0
+   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "ashrqi3_i"
+  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   sha.b\t%2,%0
+   mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "lshrqi3_i"
+  [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
+	(lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   shl.b\t%2,%0
+   mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
+  [(set_attr "flags" "szc,szc")]
+  )
+
+
+(define_expand "ashlqi3"
+  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+	(ashift:QI (match_operand:QI 1 "mra_operand" "")
+		   (match_operand:QI 2 "general_operand" "")))
+   (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, 1, ASHIFT))
+     DONE;"
+  )
+
+(define_expand "ashrqi3"
+  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+	(ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
+		     (neg:QI (match_operand:QI 2 "general_operand" ""))))
+   (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
+     DONE;"
+  )
+
+(define_expand "lshrqi3"
+  [(parallel [(set (match_operand:QI 0 "mra_operand" "")
+		   (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
+				(neg:QI (match_operand:QI 2 "general_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
+     DONE;"
+  )
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+(define_insn "ashlhi3_i"
+  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
+	(ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
+		   (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   sha.w\t%2,%0
+   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "ashrhi3_i"
+  [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
+	(ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   sha.w\t%2,%0
+   mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "lshrhi3_i"
+  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
+	(lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  ""
+  "@
+   shl.w\t%2,%0
+   mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
+  [(set_attr "flags" "szc,szc")]
+  )
+
+
+(define_expand "ashlhi3"
+  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+		   (ashift:HI (match_operand:HI 1 "mra_operand" "")
+			      (match_operand:QI 2 "general_operand" "")))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, 1, ASHIFT))
+     DONE;"
+  )
+
+(define_expand "ashrhi3"
+  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+		   (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
+				(neg:QI (match_operand:QI 2 "general_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
+     DONE;"
+  )
+
+(define_expand "lshrhi3"
+  [(parallel [(set (match_operand:HI 0 "mra_operand" "")
+		   (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
+				(neg:QI (match_operand:QI 2 "general_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
+     DONE;"
+  )
+
+
+
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+
+(define_insn "ashlpsi3_i"
+  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
+	(ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+		    (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "ashrpsi3_i"
+  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
+	(ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "lshrpsi3_i"
+  [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
+	(lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
+		      (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   shl.l\t%2,%0
+   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
+  [(set_attr "flags" "szc,szc")]
+  )
+
+
+(define_expand "ashlpsi3"
+  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+		   (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
+			       (match_operand:QI 2 "shiftcount_operand" "")))
+	      (clobber (match_scratch:HI 3 ""))])]
+  "TARGET_A24"
+  "if (m32c_prepare_shift (operands, 1, ASHIFT))
+     DONE;"
+  )
+
+(define_expand "ashrpsi3"
+  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+		   (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
+				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  "TARGET_A24"
+  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
+     DONE;"
+  )
+
+(define_expand "lshrpsi3"
+  [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
+		   (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
+				 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  "TARGET_A24"
+  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
+     DONE;"
+  )
+
+; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+; The m16c has a maximum shift count of -16..16, even when in a
+; register.  It's optimal to use multiple shifts of -8..8 rather than
+; loading larger constants into R1H multiple time.  The m32c can shift
+; -32..32 either via immediates or in registers.  Hence, separate
+; patterns.
+
+
+(define_insn "ashlsi3_16"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		   (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A16"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "ashrsi3_16"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A16"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  [(set_attr "flags" "oszc,oszc")]
+  )
+
+(define_insn "lshrsi3_16"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A16"
+  "@
+   shl.l\t%2,%0
+   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
+  [(set_attr "flags" "szc,szc")]
+  )
+
+
+
+(define_insn "ashlsi3_24"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		   (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  )
+
+(define_insn "ashrsi3_24"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   sha.l\t%2,%0
+   mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+  )
+
+(define_insn "lshrsi3_24"
+  [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
+	(lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
+		     (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
+   (clobber (match_scratch:HI 3 "=X,R1w"))]
+  "TARGET_A24"
+  "@
+   shl.l\t%2,%0
+   mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
+  )
+
+
+
+
+(define_expand "ashlsi3"
+  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+		   (ashift:SI (match_operand:SI 1 "r0123_operand" "")
+			      (match_operand:QI 2 "mrai_operand" "")))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, 1, ASHIFT))
+     DONE;"
+  )
+
+(define_expand "ashrsi3"
+  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+		   (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
+				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
+     DONE;"
+  )
+
+(define_expand "lshrsi3"
+  [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
+		   (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
+				(neg:QI (match_operand:QI 2 "mrai_operand" ""))))
+	      (clobber (match_scratch:HI 3 ""))])]
+  ""
+  "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
+     DONE;"
+  )
diff --git a/gcc/config/m32c/t-m32c b/gcc/config/m32c/t-m32c
new file mode 100644
index 000000000..30b8f6f0b
--- /dev/null
+++ b/gcc/config/m32c/t-m32c
@@ -0,0 +1,69 @@
+# Target Makefile Fragment for R8C/M16C/M32C
+# Copyright (C) 2005, 2006, 2007, 2008, 2009
+# Free Software Foundation, Inc.
+# Contributed by Red Hat.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+LIB1ASMSRC = m32c/m32c-lib1.S
+
+LIB1ASMFUNCS = \
+	__m32c_memregs \
+	__m32c_eh_return \
+	__m32c_mulsi3 \
+	__m32c_cmpsi2 \
+	__m32c_ucmpsi2 \
+	__m32c_jsri16
+
+LIB2FUNCS_EXTRA = $(srcdir)/config/m32c/m32c-lib2.c $(srcdir)/config/m32c/m32c-lib2-trapv.c
+
+# floating point emulation libraries
+
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT'				> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c			>> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+# target-specific files
+
+md_file = md
+
+MD_FILES = m32c predicates addsub bitops blkmov cond jump minmax mov muldiv prologue shift
+
+# Doing it this way lets the gen* programs report the right line numbers.
+
+md : $(MD_FILES:%=$(srcdir)/config/m32c/%.md) $(srcdir)/config/m32c/t-m32c
+	for md in $(MD_FILES); do \
+	  echo "(include \"$(srcdir)/config/m32c/$$md.md\")"; \
+	done > md
+
+m32c-pragma.o: $(srcdir)/config/m32c/m32c-pragma.c $(RTL_H) $(TREE_H) $(CONFIG_H) $(TM_H)
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+
+# We support four CPU series, but R8C and M16C share one multilib, and
+# M32C and M32CM share another.
+
+MULTILIB_OPTIONS = mcpu=m32cm
+MULTILIB_DIRNAMES = m32cm
+MULTILIB_MATCHES = mcpu?m32cm=mcpu?m32c mcpu?r8c=mcpu?m16c
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o