diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc')
332 files changed, 15757 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/20020118-1.c b/gcc/testsuite/gcc.target/powerpc/20020118-1.c new file mode 100644 index 000000000..49197b490 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20020118-1.c @@ -0,0 +1,19 @@ +/* { dg-do run { target powerpc*-*-* } }*/ +/* VxWorks only guarantees 64 bits of alignment (STACK_BOUNDARY == 64). */ +/* { dg-skip-if "" { "powerpc*-*-vxworks*" } { "*" } { "" } } */ + +/* Test local alignment. Test new target macro STARTING_FRAME_PHASE. */ +/* Origin: Aldy Hernandez <aldyh@redhat.com>. */ + +extern void abort(void); + +int main () +{ + int darisa[4] __attribute__((aligned(16))) ; + int *stephanie = (int *) darisa; + + if ((unsigned long) stephanie % 16 != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc/testsuite/gcc.target/powerpc/20030218-1.c new file mode 100644 index 000000000..2a1c4e6d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20030218-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* Test vectors that can interconvert without a cast. */ + +__ev64_opaque__ opp; +int vint __attribute__((vector_size (8))); +short vshort __attribute__((vector_size (8))); +float vfloat __attribute__((vector_size (8))); + +int +main (void) +{ + __ev64_opaque__ george = { 1, 2 }; /* { dg-error "opaque vector types cannot be initialized" } */ + + opp = vfloat; + vshort = opp; + vfloat = vshort; /* { dg-error "incompatible types when assigning" } */ + + /* Just because this is a V2SI, it doesn't make it an opaque. */ + vint = vshort; /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */ + /* { dg-error "incompatible types when assigning" "" { target *-*-* } 22 } */ + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc/testsuite/gcc.target/powerpc/20030505.c new file mode 100644 index 000000000..2bef590bf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20030505.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-W -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +#define __vector __attribute__((vector_size(8))) + +typedef float __vector __ev64_fs__; + +__ev64_opaque__ *p1; +__ev64_fs__ *p2; +int *x; + +extern void f (__ev64_opaque__ *); /* { dg-message "expected.*but argument is of type" } */ + +int main () +{ + f (x); /* { dg-warning "incompatible pointer type" } */ + f (p1); + f (p2); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20040121-1.c b/gcc/testsuite/gcc.target/powerpc/20040121-1.c new file mode 100644 index 000000000..f819a4949 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20040121-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mcpu=G5 " } */ + +long long (*y)(int t); +long long get_alias_set (int t) +{ + return y(t); +} diff --git a/gcc/testsuite/gcc.target/powerpc/20040622-1.c b/gcc/testsuite/gcc.target/powerpc/20040622-1.c new file mode 100644 index 000000000..c699296d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20040622-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -mlong-double-128" } */ +/* { dg-do compile { target { { rs6000-*-* } || { powerpc*-*-* && lp64 } } } } */ +/* Make sure compiler doesn't generate [reg+reg] address mode + for long doubles. */ +union arg { + int intarg; + long double longdoublearg; +}; +long double d; +int va(int n, union arg **argtable) +{ + (*argtable)[n].longdoublearg = d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20041111-1.c b/gcc/testsuite/gcc.target/powerpc/20041111-1.c new file mode 100644 index 000000000..94de2f03a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20041111-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-mcpu=power4 -O2" } */ + +extern unsigned long long set_mask[65]; +extern unsigned long long xyzzy(int) __attribute__((pure)); + +int valid (int x) +{ + return(xyzzy(x) & set_mask[x]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-1.c b/gcc/testsuite/gcc.target/powerpc/20050603-1.c new file mode 100644 index 000000000..041551ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050603-1.c @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +#include <locale.h> +#include <stdlib.h> +register int *testreg asm ("r29"); + +int x; +int y; +int *ext_func (int *p) { return p; } + +void test_reg_save_restore (int*) __attribute__((noinline)); +void +test_reg_save_restore (int *p) +{ + setlocale (LC_ALL, "C"); + testreg = ext_func(p); +} +main() { + testreg = &x; + test_reg_save_restore (&y); + if (testreg != &y) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc/testsuite/gcc.target/powerpc/20050603-3.c new file mode 100644 index 000000000..0f328e171 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-options "-O2" } */ +struct Q +{ + long x:20; + long y:4; + long z:8; +}b; +/* This should generate a single rl[w]imi. */ +void rotins (unsigned int x) +{ + b.y = (x<<12) | (x>>20); +} + +/* { dg-final { scan-assembler-not "inm" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/20050830-1.c b/gcc/testsuite/gcc.target/powerpc/20050830-1.c new file mode 100644 index 000000000..4a8f71a98 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050830-1.c @@ -0,0 +1,13 @@ +/* Make sure the doloop optimization is done for this loop. */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "bdn" } } */ +extern int a[]; +int foo(int w) { + int n = w; + while (n >= 512) + { + a[n] = 42; + n -= 256; + } + } diff --git a/gcc/testsuite/gcc.target/powerpc/20081204-1.c b/gcc/testsuite/gcc.target/powerpc/20081204-1.c new file mode 100644 index 000000000..8a973d0ec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20081204-1.c @@ -0,0 +1,9 @@ +/* Test for ICE arising from inconsistent use of TARGET_E500 versus + TARGET_HARD_FLOAT && !TARGET_FPRS. */ +/* { dg-do compile } */ +/* { dg-options "-mcpu=750 -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +static int comp(const void *a,const void *b){ + return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b); +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c new file mode 100644 index 000000000..2971e553e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c @@ -0,0 +1,18 @@ +/* Test generation of dlmzb for strlen on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "dlmzb\\. " } } */ + +typedef __SIZE_TYPE__ size_t; + +size_t strlen(const char *); + +size_t +strlen8(const long long *s) +{ + return strlen((const char *)s); +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c new file mode 100644 index 000000000..e65ba08eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c @@ -0,0 +1,15 @@ +/* Test generation of macchw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c new file mode 100644 index 000000000..6263818c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c @@ -0,0 +1,17 @@ +/* Test generation of macchw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c new file mode 100644 index 000000000..18d448c06 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of macchwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c new file mode 100644 index 000000000..7728c8b68 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of macchwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c new file mode 100644 index 000000000..2211cd158 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of machhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhw " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c new file mode 100644 index 000000000..4c54f27b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of machhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c new file mode 100644 index 000000000..44d8ea68c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of machhwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c new file mode 100644 index 000000000..0fc96d1bd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of machhwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c new file mode 100644 index 000000000..43ec01914 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of maclhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c new file mode 100644 index 000000000..d79df5285 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of maclhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c new file mode 100644 index 000000000..0d65a5d34 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of maclhwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c new file mode 100644 index 000000000..5b148d66c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of maclhwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c new file mode 100644 index 000000000..510e0c81c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c @@ -0,0 +1,15 @@ +/* Test generation of mulchw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c new file mode 100644 index 000000000..14b4df1c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c @@ -0,0 +1,17 @@ +/* Test generation of mulchw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c new file mode 100644 index 000000000..a0ecdac65 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of mulchwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchwu " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c new file mode 100644 index 000000000..c4da99273 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of mulchwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchwu\\. " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c new file mode 100644 index 000000000..efdd8cdbb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of mulhhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhw " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c new file mode 100644 index 000000000..cfa00034e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of mulhhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c new file mode 100644 index 000000000..c6f7a2452 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of mulhhwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c new file mode 100644 index 000000000..9b647e7d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of mulhhwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c new file mode 100644 index 000000000..ea28b5542 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of mullhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c new file mode 100644 index 000000000..76bbb6403 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of mullhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c new file mode 100644 index 000000000..152dfe9b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c @@ -0,0 +1,15 @@ +/* Test generation of mullhwu on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c new file mode 100644 index 000000000..ff4b8eca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c @@ -0,0 +1,17 @@ +/* Test generation of mullhwu. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c new file mode 100644 index 000000000..dd258efe5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c @@ -0,0 +1,15 @@ +/* Test generation of nmacchw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmacchw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c new file mode 100644 index 000000000..2a470b9e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c @@ -0,0 +1,17 @@ +/* Test generation of nmacchw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmacchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c new file mode 100644 index 000000000..f699a3fc4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of nmachhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmachhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c new file mode 100644 index 000000000..07a30c13f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of nmachhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmachhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c new file mode 100644 index 000000000..91eba842a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c @@ -0,0 +1,15 @@ +/* Test generation of nmaclhw on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmaclhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c new file mode 100644 index 000000000..83717a4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c @@ -0,0 +1,17 @@ +/* Test generation of nmaclhw. on 405. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmaclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c b/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c new file mode 100644 index 000000000..c69a7c91b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c @@ -0,0 +1,17 @@ +/* Test generation of dlmzb for strlen on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "dlmzb\\. " } } */ + +typedef __SIZE_TYPE__ size_t; + +size_t strlen(const char *); + +size_t +strlen8(const long long *s) +{ + return strlen((const char *)s); +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c b/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c new file mode 100644 index 000000000..464eff43b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c @@ -0,0 +1,14 @@ +/* Test generation of macchw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c b/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c new file mode 100644 index 000000000..bfe55d486 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c @@ -0,0 +1,16 @@ +/* Test generation of macchw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c new file mode 100644 index 000000000..1db6c6e71 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of macchwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c new file mode 100644 index 000000000..eb0b9251c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of macchwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c new file mode 100644 index 000000000..78aac5cb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of machhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhw " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c new file mode 100644 index 000000000..caf05eb41 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of machhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c new file mode 100644 index 000000000..7f1cab988 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of machhwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c new file mode 100644 index 000000000..88a23087b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of machhwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c new file mode 100644 index 000000000..327d2fbea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of maclhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c new file mode 100644 index 000000000..3e92d7ac8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of maclhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c new file mode 100644 index 000000000..248e54e8b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of maclhwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c new file mode 100644 index 000000000..c27988e2b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of maclhwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c b/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c new file mode 100644 index 000000000..14b11e2f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c @@ -0,0 +1,14 @@ +/* Test generation of mulchw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulchw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c b/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c new file mode 100644 index 000000000..d09561cb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c @@ -0,0 +1,16 @@ +/* Test generation of mulchw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulchw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c new file mode 100644 index 000000000..44bb325ce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of mulchwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulchwu " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c new file mode 100644 index 000000000..cc72f6193 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of mulchwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulchwu\\. " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c new file mode 100644 index 000000000..4b27396ed --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of mulhhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulhhw " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c new file mode 100644 index 000000000..4cfb7ebf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of mulhhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulhhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c new file mode 100644 index 000000000..b255a9bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of mulhhwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulhhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c new file mode 100644 index 000000000..e82bbc678 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of mulhhwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulhhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c new file mode 100644 index 000000000..910885753 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of mullhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c new file mode 100644 index 000000000..023eb7187 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of mullhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c b/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c new file mode 100644 index 000000000..3636e4c4e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c @@ -0,0 +1,14 @@ +/* Test generation of mullhwu on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c b/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c new file mode 100644 index 000000000..93bc9f390 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c @@ -0,0 +1,16 @@ +/* Test generation of mullhwu. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c b/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c new file mode 100644 index 000000000..2fc782688 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c @@ -0,0 +1,14 @@ +/* Test generation of nmacchw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmacchw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c b/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c new file mode 100644 index 000000000..3931ec530 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c @@ -0,0 +1,16 @@ +/* Test generation of nmacchw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmacchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c new file mode 100644 index 000000000..62362d03c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of nmachhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmachhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c new file mode 100644 index 000000000..22dac059c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of nmachhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmachhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c b/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c new file mode 100644 index 000000000..1fe13b137 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c @@ -0,0 +1,14 @@ +/* Test generation of nmaclhw on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmaclhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c b/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c new file mode 100644 index 000000000..f2abc4ccf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c @@ -0,0 +1,16 @@ +/* Test generation of nmaclhw. on 440. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmaclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + if (!a) + return 10; + return a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/980827-1.c b/gcc/testsuite/gcc.target/powerpc/980827-1.c new file mode 100644 index 000000000..c2c92337a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/980827-1.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { { *-*-linux* && ilp32 } && powerpc_fprs } } } */ +/* { dg-options -O2 } */ + +extern void exit (int); +extern void abort (void); + +double dval = 0; + +void splat (double d); + +int main(void) +{ + splat(0); + if (dval == 0) + abort(); + exit (0); +} + +void splat (double d) +{ + union { + double f; + unsigned int l[2]; + } u; + + u.f = d + d; + u.l[1] |= 1; + asm volatile ("stfd %0,dval@sdarel(13)" : : "f" (u.f)); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-1.c new file mode 100644 index 000000000..b1809fe2c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-1.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Program to test PowerPC AltiVec instructions. */ + +#include <altivec.h> + +extern void abort (void); + +vector int a1 = { 100, 200, 300, 400 }; +vector int a2 = { 500, 600, 700, 800 }; +vector int addi = { 600, 800, 1000, 1200 }; +vector int avgi = { 300, 400, 500, 600 }; + +vector float f1 = { 1.0, 2.0, 3.0, 4.0 }; +vector float f2 = { 5.0, 6.0, 7.0, 8.0 }; +vector float f3; +vector float addf = { 6.0, 8.0, 10.0, 12.0 }; + +vector int k; +vector float f, g, h; + +int main () +{ + k = vec_add (a1, a2); + if (!vec_all_eq (addi, k)) + abort (); + + k = vec_avg (a1, a2); + if (!vec_all_eq (k, avgi)) + abort (); + + h = vec_add (f1, f2); + if (!vec_all_eq (h, addf)) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc/testsuite/gcc.target/powerpc/altivec-10.c new file mode 100644 index 000000000..f532eebbf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-10.c @@ -0,0 +1,79 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */ + +#include <altivec.h> + +extern void exit (int); +extern void abort (void); + +typedef union +{ + float f[4]; + unsigned int i[4]; + vector float v; +} vec_float_t; + +void +check_vec_all_num () +{ + vec_float_t a, b, c; + + a.i[0] = 0xfffa5a5a; + a.f[1] = 1.0; + a.f[2] = 1.0; + a.f[3] = 1.0; + + b.f[0] = 1.0; + b.f[1] = 1.0; + b.f[2] = 1.0; + b.f[3] = 1.0; + + c.i[0] = 0xfffa5a5a; + c.i[1] = 0xfffa5a5a; + c.i[2] = 0xfffa5a5a; + c.i[3] = 0xfffa5a5a; + + if (vec_all_numeric (a.v)) + abort (); + + if (vec_all_nan (a.v)) + abort (); + + if (!vec_all_numeric (b.v)) + abort (); + + if (vec_all_nan (b.v)) + abort (); + + if (vec_all_numeric (c.v)) + abort (); + + if (!vec_all_nan (c.v)) + abort (); + +} + +void +check_cmple() +{ + vector float a = {1.0, 2.0, 3.0, 4.0}; + vector float b = {1.0, 3.0, 2.0, 5.0}; + vector bool int aux; + vector signed int le = {-1, -1, 0, -1}; + + aux = vec_cmple (a, b); + + if (!vec_all_eq (aux, le)) + abort (); +} + + +int +main() +{ + check_cmple (); + check_vec_all_num (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-11.c b/gcc/testsuite/gcc.target/powerpc/altivec-11.c new file mode 100644 index 000000000..7e3510c31 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-11.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mno-vsx -mabi=altivec" } */ +/* { dg-final { scan-assembler-not "lvx" } } */ +#include <altivec.h> + +void foo (vector int); +void foo_s (vector short); +void foo_c (vector char); + +/* All constants should be loaded into vector register without + load from memory. */ +void +bar (void) +{ + foo ((vector int) {0, 0, 0, 0}); + foo ((vector int) {1, 1, 1, 1}); + foo ((vector int) {15, 15, 15, 15}); + foo ((vector int) {-16, -16, -16, -16}); + foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001}); + foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f}); + foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0}); + foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101}); + foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f}); + foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0}); + foo ((vector int) {0x10101010, 0x10101010, 0x10101010, 0x10101010}); + foo ((vector int) {0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e}); + foo ((vector int) {0x100010, 0x100010, 0x100010, 0x100010}); + foo ((vector int) {0x1e001e, 0x1e001e, 0x1e001e, 0x1e001e}); + foo ((vector int) {0x10, 0x10, 0x10, 0x10}); + foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e}); + + foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0}); + foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1}); + foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15}); + foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16}); + foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0, + 0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0}); + foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f, + 0xf0f, 0xf0f, 0xf0f, 0xf0f}); + foo_s ((vector short int) {0x1010, 0x1010, 0x1010, 0x1010, + 0x1010, 0x1010, 0x1010, 0x1010}); + foo_s ((vector short int) {0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e, + 0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e}); + + foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}); + foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1}); + foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15, + 15, 15, 15, 15, 15, 15, 15, 15}); + foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16, + -16, -16, -16, -16, -16, -16, -16, -16}); + foo_c ((vector char) {16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16}); + foo_c ((vector char) {30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30}); + +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-12.c b/gcc/testsuite/gcc.target/powerpc/altivec-12.c new file mode 100644 index 000000000..39d26940d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-12.c @@ -0,0 +1,93 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Program to test PowerPC AltiVec instructions. */ + +#include <altivec.h> + +extern void abort (void); +#define CHECK_IF(E) if(!(E)) abort() + +vector int a1 = (vector int){ 100, 200, 300, 400 }; +vector int a2 = (vector int){ 500, 600, 700, 800 }; +vector int addi = (vector int){ 600, 800, 1000, 1200 }; +vector int avgi = (vector int){ 300, 400, 500, 600 }; + +vector float f1 = (vector float){ 1.0, 2.0, 3.0, 4.0 }; +vector float f2 = (vector float){ 5.0, 6.0, 7.0, 8.0 }; +vector float f3; +vector float addf1 = (vector float){ 6.0, 8.0, 10.0, 12.0 }; +vector float addf2 = (vector float){ 6.1, 8.1, 10.1, 12.1 }; +vector float addf3 = (vector float){ 6.0, 8.0, 9.9, 12.1 }; +vector int k; +vector float f, g, h; + +int main () +{ + k = vec_add (a1, a2); + CHECK_IF (vec_all_eq (addi, k)); + CHECK_IF (vec_all_ge (addi, k)); + CHECK_IF (vec_all_le (addi, k)); + CHECK_IF (vec_any_eq (addi, k)); + CHECK_IF (vec_any_ge (addi, k)); + CHECK_IF (vec_any_le (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + + k = vec_avg (a1, a2); + CHECK_IF (vec_all_eq (k, avgi)); + + h = vec_add (f1, f2); + CHECK_IF (vec_all_eq (h, addf1)); + CHECK_IF (vec_all_ge (h, addf1)); + CHECK_IF (vec_all_le (h, addf1)); + CHECK_IF (vec_any_eq (h, addf1)); + CHECK_IF (vec_any_ge (h, addf1)); + CHECK_IF (vec_any_le (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + + CHECK_IF (vec_all_gt (addf2, addf1)); + CHECK_IF (vec_any_gt (addf2, addf1)); + CHECK_IF (vec_all_ge (addf2, addf1)); + CHECK_IF (vec_any_ge (addf2, addf1)); + CHECK_IF (vec_all_ne (addf2, addf1)); + CHECK_IF (vec_any_ne (addf2, addf1)); + CHECK_IF (!vec_all_lt (addf2, addf1)); + CHECK_IF (!vec_any_lt (addf2, addf1)); + CHECK_IF (!vec_all_le (addf2, addf1)); + CHECK_IF (!vec_any_le (addf2, addf1)); + CHECK_IF (!vec_all_eq (addf2, addf1)); + CHECK_IF (!vec_any_eq (addf2, addf1)); + + CHECK_IF (vec_any_eq (addf3, addf1)); + CHECK_IF (vec_any_ne (addf3, addf1)); + CHECK_IF (vec_any_lt (addf3, addf1)); + CHECK_IF (vec_any_le (addf3, addf1)); + CHECK_IF (vec_any_gt (addf3, addf1)); + CHECK_IF (vec_any_ge (addf3, addf1)); + CHECK_IF (!vec_all_eq (addf3, addf1)); + CHECK_IF (!vec_all_ne (addf3, addf1)); + CHECK_IF (!vec_all_lt (addf3, addf1)); + CHECK_IF (!vec_all_le (addf3, addf1)); + CHECK_IF (!vec_all_gt (addf3, addf1)); + CHECK_IF (!vec_all_ge (addf3, addf1)); + + CHECK_IF (vec_all_numeric (addf3)); + CHECK_IF (vec_all_in (addf1, addf2)); + + CHECK_IF (vec_step (vector bool char) == 16); + CHECK_IF (vec_step (addf3) == 4); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c new file mode 100644 index 000000000..22ff951b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ +/* Author: Ziemowit Laski <zlaski@apple.com> */ + +/* This test case exercises intrinsic/argument combinations that, + while not in the Motorola AltiVec PIM, have nevertheless crept + into the AltiVec vernacular over the years. */ + +#include <altivec.h> + +void foo (void) +{ + vector bool int boolVec1 = (vector bool int) vec_splat_u32(3); + vector bool short boolVec2 = (vector bool short) vec_splat_u16(3); + vector bool char boolVec3 = (vector bool char) vec_splat_u8(3); + + boolVec1 = vec_sld( boolVec1, boolVec1, 4 ); + boolVec2 = vec_sld( boolVec2, boolVec2, 2 ); + boolVec3 = vec_sld( boolVec3, boolVec3, 1 ); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-14.c b/gcc/testsuite/gcc.target/powerpc/altivec-14.c new file mode 100644 index 000000000..55acb0b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-14.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +#include <altivec.h> + +vector bool long vbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector signed long vsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector unsigned long vul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector bool long *pvbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector signed long *pvsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector unsigned long *pvul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + +void fvbl (vector bool long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +void fvsl (vector signed long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +void fvul (vector unsigned long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + +int main () +{ + vector bool long lvbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + vector signed long lvsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + vector unsigned long lvul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-15.c b/gcc/testsuite/gcc.target/powerpc/altivec-15.c new file mode 100644 index 000000000..4e48cb765 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-15.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +/* Test whether the C front-end is not excessively picky about + the integral types and literals that AltiVec instrinsics will + accept. */ + +vector int vi = { 1, 2, 3, 4 }; + +int +main (void) +{ + unsigned long ul = 2; + signed long sl = 2; + unsigned int ui = 2; + signed int si = 2; + float fl = 2.0; + + vec_dst (&vi, ul, '\0'); + vec_dst (&vi, sl, 0); + vec_dst (&vi, ui, '\0'); + vec_dst (&vi, si, 0); + vec_dstst (&vi, (short)fl, '\0'); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-16.c b/gcc/testsuite/gcc.target/powerpc/altivec-16.c new file mode 100644 index 000000000..7f7d2b013 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-16.c @@ -0,0 +1,22 @@ +/* This is a compile-only test for interaction of "-maltivec" and "-save-temps". */ +/* Author: Ziemowit Laski <zlaski@apple.com>. */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-save-temps -maltivec" } */ + +#include <altivec.h> + +#define vector_float vector float +#define vector_float_foo vector float foo +#define vector_float_bar_eq vector float bar = + +/* NB: Keep the following split across three lines. */ +vector +int +a1 = { 100, 200, 300, 400 }; + +vector_float f1 = { 1.0, 2.0, 3.0, 4.0 }; +vector_float_foo = { 3.0, 4.0, 5.0, 6.0 }; +vector_float_bar_eq { 8.0, 7.0, 6.0, 5.0 }; + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-17.c b/gcc/testsuite/gcc.target/powerpc/altivec-17.c new file mode 100644 index 000000000..8b1083268 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-17.c @@ -0,0 +1,11 @@ +/* Verify a statement in the GCC Manual that GCC allows the use of a + typedef name as a vector type specifier. */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec" } */ + +typedef unsigned int ui; +typedef signed char sc; +__vector ui vui; +__vector sc vsc; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-18.c b/gcc/testsuite/gcc.target/powerpc/altivec-18.c new file mode 100644 index 000000000..5d9885820 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-18.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec" } */ +/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */ +/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */ +/* { dg-final { scan-assembler "vcmpgtsh" } } */ +/* { dg-final { scan-assembler "vcmpgtsw" } } */ + +/* Verify a statement in the GCC Manual that vector type specifiers can + omit "signed" or "unsigned". The default is the default signedness + of the base type, which differs depending on the ABI. */ + +#include <altivec.h> + +extern vector char vc1, vc2; +extern vector short vs1, vs2; +extern vector int vi1, vi2; + +int signedness (void) +{ + return vec_all_le (vc1, vc2) + && vec_all_le (vs1, vs2) + && vec_all_le (vi1, vi2); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-19.c b/gcc/testsuite/gcc.target/powerpc/altivec-19.c new file mode 100644 index 000000000..80f305a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-19.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ +/* { dg-final { scan-assembler "dst" } } */ + +void foo ( char* image ) +{ + while ( 1 ) + { + __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 ); + image += 48; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-2.c new file mode 100644 index 000000000..4f341dd42 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Program to test the vector_size attribute. This needs to run on a + target that has vectors, so use AltiVec. */ + +#define vector __attribute__((vector_size(16))) + +vector int foobar; + +/* Only floats and integrals allowed. We don't care if they map to SIs. */ +struct X { int frances; }; +vector struct X hotdog; /* { dg-error "invalid vector type" } */ + +/* Arrays of vectors. */ +vector char b[10], ouch; + +/* Pointers of vectors. */ +vector short *shoe, polish; + +int xxx[sizeof(foobar) == 16 ? 69 : -1]; + +int nc17[sizeof(shoe) == sizeof (char *) ? 69 : -1]; + +code () +{ + *shoe = polish; + b[1] = ouch; +} + +vector short +hoop () +{ + return polish; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc/testsuite/gcc.target/powerpc/altivec-20.c new file mode 100644 index 000000000..b2c29a979 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-20.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target powerpc_altivec_ok } } */ +/* { dg-options "-maltivec -mcpu=G5 -O2" } */ + +#include <altivec.h> + +void foo( float scalar) +{ + unsigned long width; + unsigned long x; + vector float vColor; + vector unsigned int selectMask; + vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) ); + + float *destRow; + vector float store, load0; + + for( ; x < width; x++) + { + load0 = vec_sel( vColor, load0, selectMask ); + vec_st( store, 0, destRow ); + store = load0; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-21.c b/gcc/testsuite/gcc.target/powerpc/altivec-21.c new file mode 100644 index 000000000..906aa197a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-21.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +extern void preansi(); + +typedef void (*pvecfunc) (); + +void foo(pvecfunc pvf) { + vector int v = (vector int){1, 2, 3, 4}; +#ifndef __LP64__ + preansi (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */ + (*pvf) (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */ +#endif /* __LP64__ */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-22.c b/gcc/testsuite/gcc.target/powerpc/altivec-22.c new file mode 100644 index 000000000..3c07309e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-22.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O3 -maltivec" } */ +/* { dg-final { scan-assembler-not "mfcr" } } */ + +#include <altivec.h> + +int foo(vector float x, vector float y) { + if (vec_all_eq(x,y)) return 3245; + else return 12; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-23.c b/gcc/testsuite/gcc.target/powerpc/altivec-23.c new file mode 100644 index 000000000..3b039f73b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-23.c @@ -0,0 +1,24 @@ +/* Verify that it is possible to define variables of composite types + containing vector types. We used to crash handling the + initializer of automatic ones. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec" } */ + +#include <altivec.h> + +typedef vector int vt; +typedef struct { vt x; int y[sizeof(vt) / sizeof (int)]; } st; +#define INIT { 1, 2, 3, 4 } + +void f () +{ + vt x = INIT; + vt y[1] = { INIT }; + st s = { INIT, INIT }; +} + +vt x = INIT; +vt y[1] = { INIT }; +st s = { INIT, INIT }; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-24.c b/gcc/testsuite/gcc.target/powerpc/altivec-24.c new file mode 100644 index 000000000..d296fe246 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-24.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +extern void abort (void); + +typedef int v4si __attribute__ ((vector_size (16))); + +#define MAGIC_NUMBER 12345 + +v4si my_vect; +int my_array[4] __attribute__ ((aligned (16))); + +void initialize (int a) +{ + my_vect = (v4si) {0, a, 2, 3}; + vec_st (my_vect, 0, my_array); +} + +int verify (void) +{ + if (my_array[1] != MAGIC_NUMBER) + abort (); +} + +int main (void) +{ + initialize (MAGIC_NUMBER); + verify (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-25.c b/gcc/testsuite/gcc.target/powerpc/altivec-25.c new file mode 100644 index 000000000..a3bd0fd00 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-25.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -Wall" } */ + + +#define vector __attribute__((__vector_size__(16) )) +vector int f() +{ + int t = 4; + return (vector int){t,t,t,t}; +} +vector int f1() +{ + return (vector int){4,4,4,4}; +} + +/* We should be able to materialize the constant vector without + any lvewx instructions as it is constant. */ +/* { dg-final { scan-assembler-not "lvewx" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-26.c b/gcc/testsuite/gcc.target/powerpc/altivec-26.c new file mode 100644 index 000000000..689d13a51 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-26.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* A compiler implementing context-sensitive keywords must define this + preprocessor macro so that altivec.h does not provide the vector, + pixel, etc. macros. */ + +#ifndef __APPLE_ALTIVEC__ +#error __APPLE_ALTIVEC__ not pre-defined +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-27.c b/gcc/testsuite/gcc.target/powerpc/altivec-27.c new file mode 100644 index 000000000..7db0ea01f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-27.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#define f0() void x0 (vector float x) { } +f0 () + +#define f1(type) void x1##type (vector type x) { } +f1 (float) + +#define f2(v, type) void x2##type (v type x) { } +f2 (vector, float) + +#define f3(type) void x3##type (vector bool type x) { } +f3 (int) + +#define f4(v, type) void x4##type (v bool type x) { } +f4 (vector, int) + +#define f5(b, type) void x5##type (vector b type x) { } +f5 (bool, int) + +#define f6(v, b, type) void x6##type (v b type x) { } +f6 (vector, bool, int) + +#define f7(v, b, type) void x7##type (v type b x) { } +f7 (vector, bool, int) + +int vector = 6; + +#define v1(v) int x8 (int v) { return v; } +v1(vector) diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-28.c b/gcc/testsuite/gcc.target/powerpc/altivec-28.c new file mode 100644 index 000000000..db6c25ac7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-28.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#define B bool +#define P pixel +#define I int +#define BI bool int +#define PI pixel int + +vector B int i; +vector P int j; +vector B I k; +vector P I l; +vector BI m; +vector PI n; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-29.c b/gcc/testsuite/gcc.target/powerpc/altivec-29.c new file mode 100644 index 000000000..10a25ecbb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-29.c @@ -0,0 +1,23 @@ +/* PR target/39558 */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -save-temps" } */ + +#define ATTRIBUTE_UNUSED __attribute__((unused)) + +int *foo (int *vector) +{ + return vector; +} + +int *bar (int *vector ATTRIBUTE_UNUSED) +{ + return vector; +} + +int *baz (int *vector __attribute__((unused))) +{ + return vector; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-3.c new file mode 100644 index 000000000..d388ad299 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-3.c @@ -0,0 +1,80 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +extern void exit (int); +extern void abort (void); + +typedef int int4 __attribute__ ((vector_size (16))); +typedef float float4 __attribute__ ((vector_size (16))); + +int4 a1 = (int4) { 100, 200, 300, 400 }; +int4 a2 = (int4) { 500, 600, 700, 800 }; + +float4 f1 = (float4) { 1.0, 2.0, 3.0, 4.0 }; +float4 f2 = (float4) { 5.0, 6.0, 7.0, 8.0 }; + +int i3[4] __attribute__((aligned(16))); +int j3[4] __attribute__((aligned(16))); +float h3[4] __attribute__((aligned(16))); +float g3[4] __attribute__((aligned(16))); + +#define vec_store(dst, src) \ + __builtin_vec_st (src, 0, (__typeof__ (src) *) dst) + +#define vec_add_int4(x, y) \ + __builtin_altivec_vaddsws (x, y) + +#define vec_add_float4(x, y) \ + __builtin_altivec_vaddfp (x, y) + +#define my_abs(x) (x > 0.0F ? x : -x) + +void +compare_int4 (int *a, int *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (a[i] != b[i]) + abort (); +} + +void +compare_float4 (float *a, float *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (my_abs(a[i] - b[i]) >= 1.0e-6) + abort (); +} + +void +main1 () +{ + int loc1 = 600, loc2 = 800; + int4 a3 = (int4) { loc1, loc2, 1000, 1200 }; + int4 itmp; + double locf = 12.0; + float4 f3 = (float4) { 6.0, 8.0, 10.0, 12.0 }; + float4 ftmp; + + vec_store (i3, a3); + itmp = vec_add_int4 (a1, a2); + vec_store (j3, itmp); + compare_int4 (i3, j3); + + vec_store (g3, f3); + ftmp = vec_add_float4 (f1, f2); + vec_store (h3, ftmp); + compare_float4 (g3, h3); +} + +int +main () +{ + main1 (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-30.c b/gcc/testsuite/gcc.target/powerpc/altivec-30.c new file mode 100644 index 000000000..99783191d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-30.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <stdbool.h> +#include <altivec.h> + +#define f0(type) void x0##type (vector bool type x) { } +f0 (int) + +#define f1(v, type) void x1##type (v bool type x) { } +f1 (vector, int) + +#define f2(b, type) void x2##type (vector b type x) { } +f2 (bool, int) + +#define f3(v, b, type) void x3##type (v b type x) { } +f3 (vector, bool, int) + +#define f4(v, b, type) void x4##type (v type b x) { } +f4 (vector, bool, int) + +#define B bool +#define I int +#define BI bool int +#define VBI vector bool int + +vector bool int a; +vector B int b; +vector B I c; +vector BI d; +VBI e; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-31.c b/gcc/testsuite/gcc.target/powerpc/altivec-31.c new file mode 100644 index 000000000..233efe1be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-31.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#define f0(type) void x0##type (vector _Bool type x) { } +f0 (int) + +#define f1(v, type) void x1##type (v _Bool type x) { } +f1 (vector, int) + +#define f2(b, type) void x2##type (vector b type x) { } +f2 (_Bool, int) + +#define f3(v, b, type) void x3##type (v b type x) { } +f3 (vector, _Bool, int) + +#define f4(v, b, type) void x4##type (v type b x) { } +f4 (vector, _Bool, int) + +#define B _Bool +#define I int +#define BI _Bool int +#define VBI vector _Bool int + +vector _Bool int a; +vector B int b; +vector B I c; +vector BI d; +VBI e; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-32.c b/gcc/testsuite/gcc.target/powerpc/altivec-32.c new file mode 100644 index 000000000..fd9f4bcca --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-32.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power6 -maltivec" } */ +/* { dg-final { scan-assembler "vsel" } } */ +/* { dg-final { scan-assembler "vrfim" } } */ +/* { dg-final { scan-assembler "vrfip" } } */ +/* { dg-final { scan-assembler "vrfiz" } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +float a[SIZE] __attribute__((__aligned__(32))); +float b[SIZE] __attribute__((__aligned__(32))); +float c[SIZE] __attribute__((__aligned__(32))); +float d[SIZE] __attribute__((__aligned__(32))); +float e[SIZE] __attribute__((__aligned__(32))); + +extern float floorf (float); +extern float ceilf (float); +extern float truncf (float); +extern float copysignf (float, float); + +void +vector_floor (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = floorf (b[i]); +} + +void +vector_ceil (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = ceilf (b[i]); +} + +void +vector_trunc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = truncf (b[i]); +} + +void +vector_copysign (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = copysignf (b[i], c[i]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-33.c b/gcc/testsuite/gcc.target/powerpc/altivec-33.c new file mode 100644 index 000000000..8e912679d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-33.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mno-vsx" } */ + +/* We should only produce one vspltw as we already splatted the value. */ +/* { dg-final { scan-assembler-times "vspltw" 1 } } */ + +#include <altivec.h> + +vector float f(vector float a) +{ + vector float b = vec_splat (a, 2); + return vec_splat (b, 0); +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-34.c b/gcc/testsuite/gcc.target/powerpc/altivec-34.c new file mode 100644 index 000000000..8e6372bfb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-34.c @@ -0,0 +1,24 @@ +/* PR target/49621 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -maltivec" } */ + +#include <altivec.h> + +int +foo (void) +{ + vector unsigned a, b, c; + unsigned k = 1; + + a = (vector unsigned) { 0, 0, 0, 1 }; + b = c = (vector unsigned) { 0, 0, 0, 0 }; + + a = vec_add (a, vec_splats (k)); + b = vec_add (b, a); + c = vec_sel (c, a, b); + + if (vec_any_eq (b, c)) + return 1; + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-4.c new file mode 100644 index 000000000..2c78f6586 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-4.c @@ -0,0 +1,65 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#define vector __attribute__((vector_size(16))) + +static int vector x, y, z; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + z = __builtin_altivec_vadduwm (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = __builtin_altivec_vcmpbfp_p (0, f, g); + int1 = __builtin_altivec_vcmpeqfp_p (0, f, g); + int1 = __builtin_altivec_vcmpequb_p (0, c, d); + int1 = __builtin_altivec_vcmpequh_p (0, s, t); + int1 = __builtin_altivec_vcmpequw_p (0, i, j); + int1 = __builtin_altivec_vcmpgefp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtfp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtsb_p (0, c, d); + int1 = __builtin_altivec_vcmpgtsh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtsw_p (0, i, j); + int1 = __builtin_altivec_vcmpgtub_p (0, c, d); + int1 = __builtin_altivec_vcmpgtuh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtuw_p (0, i, j); + + __builtin_altivec_mtvscr (i); + __builtin_altivec_dssall (); + s = __builtin_altivec_mfvscr (); + __builtin_altivec_dss (3); + + __builtin_altivec_dst (pi, int1 + int2, 3); + __builtin_altivec_dstst (pi, int1 + int2, 3); + __builtin_altivec_dststt (pi, int1 + int2, 3); + __builtin_altivec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) __builtin_altivec_lvsl (int1 + 69, pi); + uc = (vector unsigned char) __builtin_altivec_lvsr (int1 + 69, pi); + + c = __builtin_altivec_lvebx (int1, pi); + s = __builtin_altivec_lvehx (int1, pi); + i = __builtin_altivec_lvewx (int1, pi); + i = __builtin_altivec_lvxl (int1, pi); + i = __builtin_altivec_lvx (int1, pi); + + __builtin_altivec_stvx (i, int2, pi); + __builtin_altivec_stvebx (c, int2, pi); + __builtin_altivec_stvehx (s, int2, pi); + __builtin_altivec_stvewx (i, int2, pi); + __builtin_altivec_stvxl (i, int2, pi); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-5.c b/gcc/testsuite/gcc.target/powerpc/altivec-5.c new file mode 100644 index 000000000..ae85cdbdc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#define vector __attribute__((vector_size(16))) + +void foo (const unsigned long x, + vector signed int a, vector signed int b) +{ + unsigned char d[64]; + + __builtin_altivec_stvewx (b, 0, d); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc/testsuite/gcc.target/powerpc/altivec-6.c new file mode 100644 index 000000000..51d411688 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-6.c @@ -0,0 +1,66 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#include <altivec.h> + +/* These denote "generic" GCC vectors. */ +static int __attribute__((vector_size(16))) x, y, z; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + z = vec_add (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = vec_all_in (f, g); + int1 = vec_all_ge (f, g); + int1 = vec_all_eq (c, d); + int1 = vec_all_ne (s, t); + int1 = vec_any_eq (i, j); + int1 = vec_any_ge (f, g); + int1 = vec_all_ngt (f, g); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + + vec_mtvscr (i); + vec_dssall (); + s = (vector signed short) vec_mfvscr (); + vec_dss (3); + + vec_dst (pi, int1 + int2, 3); + vec_dstst (pi, int1 + int2, 3); + vec_dststt (pi, int1 + int2, 3); + vec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) vec_lvsl (int1 + 69, (signed int *) pi); + uc = (vector unsigned char) vec_lvsr (int1 + 69, (signed int *) pi); + + c = vec_lde (int1, (signed char *) pi); + s = vec_lde (int1, (signed short *) pi); + i = vec_lde (int1, (signed int *) pi); + i = vec_ldl (int1, pi); + i = vec_ld (int1, pi); + + vec_st (i, int2, pi); + vec_ste (c, int2, (signed char *) pi); + vec_ste (s, int2, (signed short *) pi); + vec_ste (i, int2, (signed int *) pi); + vec_stl (i, int2, pi); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c new file mode 100644 index 000000000..30a1ee520 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c @@ -0,0 +1,46 @@ +/* Origin: Aldy Hernandez <aldyh@redhat.com> */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +int **intp; +int *var_int; +unsigned int **uintp; +vector pixel *varpixel; +vector signed char *vecchar; +vector signed int *vecint; +vector signed short *vecshort; +vector unsigned char *vecuchar; +vector unsigned int *vecuint; +vector unsigned short *vecushort; +vector float *vecfloat; + +int main () +{ + *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]); + *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); + *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); + *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); + *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); + *vecint++ = vec_ld(var_int[0], intp[1]); + *vecint++ = vec_lde(var_int[0], intp[1]); + *vecint++ = vec_ldl(var_int[0], intp[1]); + *vecint++ = vec_lvewx(var_int[0], intp[1]); + *vecint++ = vec_unpackh(vecshort[0]); + *vecint++ = vec_unpackl(vecshort[0]); + *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]); + *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]); + *vecuint++ = vec_ld(var_int[0], uintp[1]); + *vecuint++ = vec_lvx(var_int[0], uintp[1]); + *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); + *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-8.c b/gcc/testsuite/gcc.target/powerpc/altivec-8.c new file mode 100644 index 000000000..6668cf2db --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-8.c @@ -0,0 +1,19 @@ +/* Origin: Aldy Hernandez <aldyh@redhat.com> */ +/* Test rs6000_legitimate_address. PRE_INC should be invalid. */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector signed short *hannah; + +int +main () +{ + *hannah++ = __builtin_altivec_vspltish (5); + *hannah++ = __builtin_altivec_vspltish (6); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-9.c b/gcc/testsuite/gcc.target/powerpc/altivec-9.c new file mode 100644 index 000000000..b34dc1b51 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-9.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -g" } */ + +/* PR9564 */ + +extern int vfork(void); + +void +boom (void) +{ + char buf[65536]; + vfork(); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c new file mode 100644 index 000000000..20d29bf05 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Basic test for the new VMX intrinsics. */ +#include <altivec.h> + +int f(vector int a, int b) +{ + return vec_extract (a, b); +} +short f1(vector short a, int b) +{ + return vec_extract (a, b); +} +vector short f2(vector short a, int b) +{ + return vec_insert (b, a, b); +} +vector float f3(vector float a, int b) +{ + return vec_insert (b, a, b); +} + +float g(void); + +vector float f4(float b, int t) +{ + return vec_promote (g(), t); +} +vector float f5(float b) +{ + return vec_splats (g()); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c new file mode 100644 index 000000000..fdb375c9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c @@ -0,0 +1,141 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ +/* Test the vec_extract VMX intrinsics. */ +#include <altivec.h> + +extern void abort (void); + +vector int a = {0, 1, 2, 3}; +vector short b = {0, 1, 2, 3, 4, 5, 6, 7}; + +int f(vector int a, int b) +{ + return vec_extract (a, b); +} + +int f0 (vector int a) +{ + return vec_extract (a, 0); +} +int f1 (vector int a) +{ + return vec_extract (a, 1); +} +int f2 (vector int a) +{ + return vec_extract (a, 2); +} +int f3 (vector int a) +{ + return vec_extract (a, 3); +} +int f4 (vector int a) +{ + return vec_extract (a, 4); +} + +int g(vector short a, int b) +{ + return vec_extract (a, b); +} + +int g0 (vector short a) +{ + return vec_extract (a, 0); +} +int g1 (vector short a) +{ + return vec_extract (a, 1); +} +int g2 (vector short a) +{ + return vec_extract (a, 2); +} +int g3 (vector short a) +{ + return vec_extract (a, 3); +} + +int g4 (vector short a) +{ + return vec_extract (a, 4); +} +int g5 (vector short a) +{ + return vec_extract (a, 5); +} +int g6 (vector short a) +{ + return vec_extract (a, 6); +} +int g7 (vector short a) +{ + return vec_extract (a, 7); +} +int g8 (vector short a) +{ + return vec_extract (a, 8); +} +int main1(void) __attribute__((noinline)); +int main1(void) +{ + int i; + /* Check vec_extract with a non constant element numbering */ + for(i=0;i<10;i++) + { + if (f(a, i) != (i&0x3)) + abort (); + } + + /* Check vec_extract with a constant element numbering */ + if (f0(a) != 0) + abort (); + if (f1(a) != 1) + abort (); + if (f2(a) != 2) + abort (); + if (f3(a) != 3) + abort (); + /* Check that vec_extract works with a constant element higher than + the number of elements. */ + if (f4(a) != 0) + abort (); + + /* Check vec_extract with a non constant element numbering */ + for(i=0;i<10;i++) + { + if (g(b, i) != (i&0x7)) + abort (); + } + + /* Check vec_extract with a constant element numbering */ + if (g0(b) != 0) + abort (); + if (g1(b) != 1) + abort (); + if (g2(b) != 2) + abort (); + if (g3(b) != 3) + abort (); + if (g4(b) != 4) + abort (); + if (g5(b) != 5) + abort (); + if (g6(b) != 6) + abort (); + if (g7(b) != 7) + abort (); + /* Check that vec_extract works with a constant element higher than + the number of elements. */ + if (g8(b) != 0) + abort (); + + return 0; +} + +int main(void) +{ + return main1 (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c new file mode 100644 index 000000000..b941ab186 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ +/* Test the vec_splats and vec_promote VMX intrinsics. */ +#include <altivec.h> + +extern void abort (void); + +vector int a = {0, 0, 0, 0}; +int main1(int t) __attribute__((noinline)); +int main1(int t) +{ + int i; + vector int b = vec_splats(0); + if (__builtin_memcmp (&a, &b, sizeof(vector int))) + abort (); + + b = vec_splats(t); + if (__builtin_memcmp (&a, &b, sizeof(vector int))) + abort (); + + b = vec_promote(0, 1); + if (vec_extract (b, 1) != 0) + abort (); + + b = vec_promote(t, t); + if (vec_extract (b, t) != 0) + abort (); + + return 0; +} + +int main(void) +{ + return main1 (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c new file mode 100644 index 000000000..c694691d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c @@ -0,0 +1,42 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Test the vec_splats and vec_promote VMX intrinsics. */ +#include <altivec.h> + +extern void abort (void); + +vector int a[] = {{0, 0, 0, 0}, {1,0,0,0}, {1,2,0,0},{1,2,3,0},{1,2,3,4},{5,2,3,4},{5,6,3,4}}; +vector int c = {0,6,3,4}; +vector int d = {0,0,3,4}; +int main1(int t) __attribute__((noinline)); +int main1(int t) +{ + int i; + vector int b = vec_splats(0); + for(i = 0;i<sizeof(a)/sizeof(a[0])-1;i++) + { + if (__builtin_memcmp (&b, &a[i], sizeof(vector int))) + abort (); + b = vec_insert(i+1, b, i); + } + if (__builtin_memcmp (&b, &a[i], sizeof(vector int))) + abort (); + + b = vec_insert(0, b, 0); + if (__builtin_memcmp (&b, &c, sizeof(vector int))) + abort (); + + b = vec_insert(0, b, 1); + if (__builtin_memcmp (&b, &d, sizeof(vector int))) + abort (); + + return 0; +} + +int main(void) +{ + return main1 (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c new file mode 100644 index 000000000..95f109d1a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Basic test for the new VMX intrinsics and error messages. */ +#include <altivec.h> + +int main(int argc, char **argv) +{ +vector float t; + vec_promote(); /* { dg-error "vec_promote only accepts 2" } */ + vec_promote(1.0f); /* { dg-error "vec_promote only accepts 2" } */ + vec_promote(1.0f, 2, 3); /* { dg-error "vec_promote only accepts 2" } */ + vec_extract (); /* { dg-error "vec_extract only accepts 2" } */ + vec_extract (t); /* { dg-error "vec_extract only accepts 2" } */ + vec_extract (t, 2); + vec_extract (t, 2, 5, 6); /* { dg-error "vec_extract only accepts 2" } */ + vec_splats (); /* { dg-error "vec_splats only accepts 1" } */ + vec_splats (t, 3); /* { dg-error "vec_splats only accepts 1" } */ + vec_insert (); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t, 3); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t, 3, 2, 4, 6, 6); /* { dg-error "vec_insert only accepts 3" } */ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c new file mode 100644 index 000000000..5d62f18e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +#include <altivec.h> + +/* This used to ICE with reloading of a constant address. */ + +vector float f(void) +{ + vector float * a = (void*)16; + return vec_lvlx (0, a); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c new file mode 100644 index 000000000..ae7769400 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "vor" 2 } } */ +#include <altivec.h> + +/* Make sure that lvlx and lvrx are not combined into one insn and + we still get a vor. */ + +vector unsigned char +lvx_float (long off, float *p) +{ + vector unsigned char l, r; + + l = (vector unsigned char) vec_lvlx (off, p); + r = (vector unsigned char) vec_lvrx (off, p); + return vec_or(l, r); +} + +vector unsigned char +lvxl_float (long off, float *p) +{ + vector unsigned char l, r; + + l = (vector unsigned char) vec_lvlxl (off, p); + r = (vector unsigned char) vec_lvrxl (off, p); + return vec_or(l, r); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c b/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c new file mode 100644 index 000000000..dda5eb0c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c @@ -0,0 +1,57 @@ +/* { dg-do run { target { powerpc*-*-* && cell_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! cell_hw } } } } */ +/* { dg-require-effective-target powerpc_ppu_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +#include <altivec.h> +#include <string.h> + +extern void abort (void); + +typedef short int sint16; +typedef signed char int8; + +int main1(void) __attribute__((noinline)); +int main1(void) +{ + sint16 test_vector[4] = { 1678, -2356, 19246, -17892 }; + int8 test_dst[128] __attribute__(( aligned( 16 ))); + float test_out[4] __attribute__(( aligned( 16 ))); + int p; + + for( p = 0; p < 24; ++p ) + { + memset( test_dst, 0, 128 ); + memcpy( &test_dst[p], test_vector, 8 ); + { + vector float VR, VL, V; + /* load the righthand section of the misaligned vector */ + VR = (vector float) vec_lvrx( 8, &test_dst[p] ); + VL = (vector float) vec_lvlx( 0, &test_dst[p] ); + /* Vector Shift Left Double by Octet Immediate, move the right hand section into the bytes */ + VR = vec_vsldoi( VR, VR, 2 << 2 ); + /* or those two together */ + V = vec_vor( VL, VR ); + /* sign extend */ + V = (vector float) vec_vupkhsh((vector bool short)V ); + /* fixed to float by S16_SHIFT_BITS bits */ + V = (vector float) vec_vcfsx ((vector signed int)V, 5 ); + + vec_stvx( V, 0, &test_out[0] ); + if (test_out[0] != 52.437500) + abort (); + if (test_out[1] != -73.625000) + abort (); + if (test_out[2] != 601.437500) + abort (); + if (test_out[3] != -559.125000) + abort (); + } + } +return 0; +} + + +int main(void) +{ + return main1(); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-consts.c b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c new file mode 100644 index 000000000..2c5bc99cf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c @@ -0,0 +1,318 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -O2" } */ + +/* Check that "easy" AltiVec constants are correctly synthesized. */ + +extern void abort (void); + +typedef __attribute__ ((vector_size (16))) unsigned char v16qi; +typedef __attribute__ ((vector_size (16))) unsigned short v8hi; +typedef __attribute__ ((vector_size (16))) unsigned int v4si; + +char w[16] __attribute__((aligned(16))); + + +/* Emulate the vspltis? instructions on a 16-byte array of chars. */ + +void vspltisb (char *v, int val) +{ + int i; + for (i = 0; i < 16; i++) + v[i] = val; +} + +void vspltish (char *v, int val) +{ + int i; + for (i = 0; i < 16; i += 2) + v[i] = val >> 7, v[i + 1] = val; +} + +void vspltisw (char *v, int val) +{ + int i; + for (i = 0; i < 16; i += 4) + v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val; +} + + +/* Use three different check functions for each mode-instruction pair. + The callers have no typecasting and no addressable vectors, to make + the test more robust. */ + +void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2) +{ + if (memcmp (&v1, v2, 16)) + abort (); +} + +void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2) +{ + if (memcmp (&v1, v2, 16)) + abort (); +} + +void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2) +{ + if (memcmp (&v1, v2, 16)) + abort (); +} + + +/* V16QI tests. */ + +void v16qi_vspltisb () +{ + v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 }; + vspltisb (w, 15); + check_v16qi (v, w); +} + +void v16qi_vspltisb_neg () +{ + v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 }; + vspltisb (w, -5); + check_v16qi (v, w); +} + +void v16qi_vspltisb_addself () +{ + v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 }; + vspltisb (w, 30); + check_v16qi (v, w); +} + +void v16qi_vspltisb_neg_addself () +{ + v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 }; + vspltisb (w, -24); + check_v16qi (v, w); +} + +void v16qi_vspltish () +{ + v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 }; + vspltish (w, 15); + check_v16qi (v, w); +} + +void v16qi_vspltish_addself () +{ + v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 }; + vspltish (w, 30); + check_v16qi (v, w); +} + +void v16qi_vspltish_neg () +{ + v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 }; + vspltish (w, -5); + check_v16qi (v, w); +} + +void v16qi_vspltisw () +{ + v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 }; + vspltisw (w, 15); + check_v16qi (v, w); +} + +void v16qi_vspltisw_addself () +{ + v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 }; + vspltisw (w, 30); + check_v16qi (v, w); +} + +void v16qi_vspltisw_neg () +{ + v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 }; + vspltisw (w, -5); + check_v16qi (v, w); +} + + +/* V8HI tests. */ + +void v8hi_vspltisb () +{ + v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F }; + vspltisb (w, 15); + check_v8hi (v, w); +} + +void v8hi_vspltisb_addself () +{ + v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E }; + vspltisb (w, 30); + check_v8hi (v, w); +} + +void v8hi_vspltisb_neg () +{ + v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB }; + vspltisb (w, -5); + check_v8hi (v, w); +} + +void v8hi_vspltish () +{ + v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 }; + vspltish (w, 15); + check_v8hi (v, w); +} + +void v8hi_vspltish_neg () +{ + v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 }; + vspltish (w, -5); + check_v8hi (v, w); +} + +void v8hi_vspltish_addself () +{ + v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 }; + vspltish (w, 30); + check_v8hi (v, w); +} + +void v8hi_vspltish_neg_addself () +{ + v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 }; + vspltish (w, -24); + check_v8hi (v, w); +} + +void v8hi_vspltisw () +{ + v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 }; + vspltisw (w, 15); + check_v8hi (v, w); +} + +void v8hi_vspltisw_addself () +{ + v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 }; + vspltisw (w, 30); + check_v8hi (v, w); +} + +void v8hi_vspltisw_neg () +{ + v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 }; + vspltisw (w, -5); + check_v8hi (v, w); +} + +/* V4SI tests. */ + +void v4si_vspltisb () +{ + v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F }; + vspltisb (w, 15); + check_v4si (v, w); +} + +void v4si_vspltisb_addself () +{ + v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E }; + vspltisb (w, 30); + check_v4si (v, w); +} + +void v4si_vspltisb_neg () +{ + v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB }; + vspltisb (w, -5); + check_v4si (v, w); +} + +void v4si_vspltish () +{ + v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F }; + vspltish (w, 15); + check_v4si (v, w); +} + +void v4si_vspltish_addself () +{ + v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E }; + vspltish (w, 30); + check_v4si (v, w); +} + +void v4si_vspltish_neg () +{ + v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB }; + vspltish (w, -5); + check_v4si (v, w); +} + +void v4si_vspltisw () +{ + v4si v = { 15, 15, 15, 15 }; + vspltisw (w, 15); + check_v4si (v, w); +} + +void v4si_vspltisw_neg () +{ + v4si v = { -5, -5, -5, -5 }; + vspltisw (w, -5); + check_v4si (v, w); +} + +void v4si_vspltisw_addself () +{ + v4si v = { 30, 30, 30, 30 }; + vspltisw (w, 30); + check_v4si (v, w); +} + +void v4si_vspltisw_neg_addself () +{ + v4si v = { -24, -24, -24, -24 }; + vspltisw (w, -24); + check_v4si (v, w); +} + + + +int main () +{ + v16qi_vspltisb (); + v16qi_vspltisb_neg (); + v16qi_vspltisb_addself (); + v16qi_vspltisb_neg_addself (); + v16qi_vspltish (); + v16qi_vspltish_addself (); + v16qi_vspltish_neg (); + v16qi_vspltisw (); + v16qi_vspltisw_addself (); + v16qi_vspltisw_neg (); + + v8hi_vspltisb (); + v8hi_vspltisb_addself (); + v8hi_vspltisb_neg (); + v8hi_vspltish (); + v8hi_vspltish_neg (); + v8hi_vspltish_addself (); + v8hi_vspltish_neg_addself (); + v8hi_vspltisw (); + v8hi_vspltisw_addself (); + v8hi_vspltisw_neg (); + + v4si_vspltisb (); + v4si_vspltisb_addself (); + v4si_vspltisb_neg (); + v4si_vspltish (); + v4si_vspltish_addself (); + v4si_vspltish_neg (); + v4si_vspltisw (); + v4si_vspltisw_neg (); + v4si_vspltisw_addself (); + v4si_vspltisw_neg_addself (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-macros.c b/gcc/testsuite/gcc.target/powerpc/altivec-macros.c new file mode 100644 index 000000000..c07eaa36a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-macros.c @@ -0,0 +1,64 @@ +/* Copyright (C) 2007 Free Software Foundation, Inc. */ + +/* { dg-do preprocess } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Conditional macros should not be expanded by pragmas. */ +#pragma __vector +_Pragma ("__vector") + +/* Redefinition of conditional macros. */ +/* No warning should be generated. */ + +#define __vector __new_vector +#define __pixel __new_pixel +#define __bool __new_bool +#define vector new_vector +#define pixel new_pixel +#define bool new_bool + +/* Definition of conditional macros. */ +/* No warning should be generated. */ + +#undef __vector +#define __vector __new_vector + +#undef __pixel +#define __pixel __new_pixel + +#undef __bool +#define __bool __new_bool + +#undef vector +#define vector new_vector + +#undef pixel +#define pixel new_pixel + +#undef bool +#define bool new_bool + +/* Re-definition of "unconditional" macros. */ +/* Warnings should be generated as usual. */ + +#define __vector __newer_vector +#define __pixel __newer_pixel +#define __bool __newer_bool +#define vector newer_vector +#define pixel newer_pixel +#define bool newer_bool + +/* { dg-warning "redefined" "__vector redefined" { target *-*-* } 45 } */ +/* { dg-warning "redefined" "__pixel redefined" { target *-*-* } 46 } */ +/* { dg-warning "redefined" "__bool redefined" { target *-*-* } 47 } */ +/* { dg-warning "redefined" "vector redefined" { target *-*-* } 48 } */ +/* { dg-warning "redefined" "pixel redefined" { target *-*-* } 49 } */ +/* { dg-warning "redefined" "bool redefined" { target *-*-* } 50 } */ + +/* { dg-message "location of the previous" "prev __vector defn" { target *-*-* } 25 } */ +/* { dg-message "location of the previous" "prev __pixel defn" { target *-*-* } 28 } */ +/* { dg-message "location of the previous" "prev __bool defn" { target *-*-* } 31 } */ +/* { dg-message "location of the previous" "prev vector defn" { target *-*-* } 34 } */ +/* { dg-message "location of the previous" "prev pixel defn" { target *-*-* } 37 } */ +/* { dg-message "location of the previous" "prev bool defn" { target *-*-* } 40 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c b/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c new file mode 100644 index 000000000..a7b81bbad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -fpreprocessed" } */ + +/* Program to test AltiVec with -fpreprocessed. */ +int foo(__attribute__((altivec(vector__))) float x, + __attribute__((altivec(vector__))) float y) +{ + if (__builtin_vec_vcmpeq_p (2, (x), (y))) + return 3245; + else + return 12; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-splat.c b/gcc/testsuite/gcc.target/powerpc/altivec-splat.c new file mode 100644 index 000000000..91ab72d78 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-splat.c @@ -0,0 +1,49 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -O2" } */ + +/* Testcase by Richard Guenther and Steven Bosscher. + Check that "easy" AltiVec constants are correctly synthesized + if they need to be reloaded. */ + +typedef __attribute__ ((vector_size (16))) unsigned char v16qi; +typedef __attribute__ ((vector_size (16))) unsigned short v8hi; +typedef __attribute__ ((vector_size (16))) unsigned int v4si; + +#define REGLIST \ + "77", "78", "79", "80", "81", "82", "83", "84", "85", "86", \ + "87", "88", "89", "90", "91", "92", "93", "94", "95", "96", \ + "97", "98", "99", "100", "101", "102", "103", "104", "105", "106", \ + "107", "108" + + +#define TEST(a, result, b) \ + void a##_##b (int h) \ + { \ + volatile a tmp; \ + while (h-- > 0) \ + { \ + asm ("" : : : REGLIST); \ + tmp = (a) (result) __builtin_altivec_##b (5); \ + } \ + } \ + \ + void a##_##b##_neg (int h) \ + { \ + volatile a tmp; \ + while (h-- > 0) \ + { \ + asm ("" : : : REGLIST); \ + tmp = (a) (result) __builtin_altivec_##b (-5); \ + } \ + } + +TEST(v16qi, v16qi, vspltisb) +TEST(v16qi, v8hi, vspltish) +TEST(v16qi, v4si, vspltisw) +TEST(v8hi, v16qi, vspltisb) +TEST(v8hi, v8hi, vspltish) +TEST(v8hi, v4si, vspltisw) +TEST(v4si, v16qi, vspltisb) +TEST(v4si, v8hi, vspltish) +TEST(v4si, v4si, vspltisw) diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c new file mode 100644 index 000000000..9096892ee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c @@ -0,0 +1,91 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +/* Valid AltiVec vector types should be accepted with no warnings. */ + +__vector char vc; +__vector unsigned char vuc; +__vector signed char vsc; +__vector __bool char vbc; +__vector short vh; +__vector signed short vsh; +__vector unsigned short vuh; +__vector short int vhi; +__vector signed short int vshi; +__vector unsigned short int vuhi; +__vector __bool short vbh; +__vector __bool short int vbhi; +__vector int vi; +__vector unsigned int vui; +__vector signed int vsi; +__vector __bool int vbi; +__vector unsigned vuj; +__vector signed vsj; +__vector __bool vbj; +__vector float vf; +__vector _Bool vb; + +/* These should be rejected as invalid AltiVec types. */ + +__vector long long vll; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long vull; /* { dg-error "AltiVec types" "" } */ +__vector signed long long vsll; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long vbll; /* { dg-error "AltiVec types" "" } */ +__vector long long int vlli; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long int vulli; /* { dg-error "AltiVec types" "" } */ +__vector signed long long int vslli; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long int vblli; /* { dg-error "AltiVec types" "" } */ +__vector double vd1; /* { dg-error "AltiVec types" "" } */ +__vector long double vld; /* { dg-error "AltiVec types" "" } */ +__vector _Complex float vcf; /* { dg-error "AltiVec types" "" } */ +__vector _Complex double vcd; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long double vcld; /* { dg-error "AltiVec types" "" } */ +__vector _Complex signed char vcsc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned char vcuc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex short vcss; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned short vcus; /* { dg-error "AltiVec types" "" } */ +__vector _Complex int vcsi; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned int vcui; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long vcsl; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long vcul; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long long vcsll; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long long vcull; /* { dg-error "AltiVec types" "" } */ +__vector __complex float v_cf; /* { dg-error "AltiVec types" "" } */ +__vector __complex double v_cd; /* { dg-error "AltiVec types" "" } */ +__vector __complex long double v_cld; /* { dg-error "AltiVec types" "" } */ +__vector __complex signed char v_csc; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned char v_cuc; /* { dg-error "AltiVec types" "" } */ +__vector __complex short v_css; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned short v_cus; /* { dg-error "AltiVec types" "" } */ +__vector __complex int v_csi; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned int v_cui; /* { dg-error "AltiVec types" "" } */ +__vector __complex long v_csl; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long v_cul; /* { dg-error "AltiVec types" "" } */ +__vector __complex long long v_csll; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long long v_cull; /* { dg-error "AltiVec types" "" } */ + +/* These should be rejected because the component types are invalid. We + don't care about the actual error messages here. */ + +__vector __bool unsigned char vbuc; /* { dg-error "" "" } */ +__vector __bool signed char vbsc; /* { dg-error "" "" } */ +__vector __bool unsigned short vbuh; /* { dg-error "" "" } */ +__vector __bool signed short vbsh; /* { dg-error "" "" } */ +__vector __bool unsigned int vbui; /* { dg-error "" "" } */ +__vector __bool signed int vbsi; /* { dg-error "" "" } */ +__vector __bool unsigned vbuj; /* { dg-error "" "" } */ +__vector __bool signed vbsj; /* { dg-error "" "" } */ +__vector signed float vsf; /* { dg-error "" "" } */ +__vector unsigned float vuf; /* { dg-error "" "" } */ +__vector short float vsf; /* { dg-error "" "" } */ +__vector signed double vsd; /* { dg-error "" "" } */ +__vector unsigned double vud; /* { dg-error "" "" } */ +__vector short double vsd; /* { dg-error "" "" } */ +__vector __bool float vbf; /* { dg-error "" "" } */ +__vector __bool double vbd; /* { dg-error "" "" } */ +__vector __bool short float blf; /* { dg-error "" "" } */ +__vector __bool short double vlbd; /* { dg-error "" "" } */ + +/* { dg-message "note: previous" "prev vsf" { target *-*-* } 79 } */ +/* { dg-message "note: previous" "prev vsd" { target *-*-* } 82 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c new file mode 100644 index 000000000..cee6c8f26 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +/* These should get warnings for 32-bit code. */ + +__vector long vl; /* { dg-warning "deprecated" "" } */ +__vector unsigned long vul; /* { dg-warning "deprecated" "" } */ +__vector signed long vsl; /* { dg-warning "deprecated" "" } */ +__vector __bool long int vbli; /* { dg-warning "deprecated" "" } */ +__vector long int vli; /* { dg-warning "deprecated" "" } */ +__vector unsigned long int vuli; /* { dg-warning "deprecated" "" } */ +__vector signed long int vsli; /* { dg-warning "deprecated" "" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c new file mode 100644 index 000000000..ea371ce77 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +/* These should be rejected for 64-bit code. */ + +__vector long vl; /* { dg-error "invalid for 64" "" } */ +__vector unsigned long vul; /* { dg-error "invalid for 64" "" } */ +__vector signed long vsl; /* { dg-error "invalid for 64" "" } */ +__vector __bool long int vbli; /* { dg-error "invalid for 64" "" } */ +__vector long int vli; /* { dg-error "invalid for 64" "" } */ +__vector unsigned long int vuli; /* { dg-error "invalid for 64" "" } */ +__vector signed long int vsli; /* { dg-error "invalid for 64" "" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c new file mode 100644 index 000000000..52fa91453 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-warn-altivec-long -mno-vsx" } */ + +/* These should not get warnings for 32-bit code when the warning is + disabled. */ + +__vector long vl; +__vector unsigned long vul; +__vector signed long vsl; +__vector __bool long int vbli; +__vector long int vli; +__vector unsigned long int vuli; +__vector signed long int vsli; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c new file mode 100644 index 000000000..1349ae590 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c @@ -0,0 +1,82 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */ + +#include <stdarg.h> + +extern void exit (int); +extern void abort (void); + +#define vector __attribute__((vector_size (16))) + +const vector unsigned int v1 = {10,11,12,13}; +const vector unsigned int v2 = {20,21,22,23}; +const vector unsigned int v3 = {30,31,32,33}; +const vector unsigned int v4 = {40,41,42,43}; + +void foo(vector unsigned int a, ...) +{ + va_list args; + vector unsigned int v; + + va_start (args, a); + if (memcmp (&a, &v1, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v2, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v3, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v4, sizeof (v)) != 0) + abort (); + va_end (args); +} + +void bar(vector unsigned int a, ...) +{ + va_list args; + vector unsigned int v; + int b; + + va_start (args, a); + if (memcmp (&a, &v1, sizeof (v)) != 0) + abort (); + b = va_arg (args, int); + if (b != 2) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v2, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v3, sizeof (v)) != 0) + abort (); + va_end (args); +} + + +int main1(void) +{ + /* In this call, in the Darwin ABI, the first argument goes into v2 + the second one into r9-r10 and memory, + and the next two in memory. */ + foo ((vector unsigned int){10,11,12,13}, + (vector unsigned int){20,21,22,23}, + (vector unsigned int){30,31,32,33}, + (vector unsigned int){40,41,42,43}); + /* In this call, in the Darwin ABI, the first argument goes into v2 + the second one into r9, then r10 is reserved and + there are two words of padding in memory, and the next two arguments + go after the padding. */ + bar ((vector unsigned int){10,11,12,13}, 2, + (vector unsigned int){20,21,22,23}, + (vector unsigned int){30,31,32,33}); + return 0; +} + +int main (void) +{ + return main1 (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c new file mode 100644 index 000000000..3689f9749 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c @@ -0,0 +1,605 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include <altivec.h> + +int printf(const char * , ...); +extern void abort(); + +void foo(char *bS, char *bS_edge, int field_MBAFF, int top){ + char intra[16] __attribute__ ((aligned(16))); + signed short mv_const[8] __attribute__((aligned(16))); + + vector signed short v_three, v_ref_mask00, v_ref_mask01, v_vec_maskv, v_vec_maskh; + vector unsigned char v_permv, v_permh, v_bS, v_bSh, v_bSv, v_cbp_maskv, v_cbp_maskvn, v_cbp_maskh, v_cbp_maskhn, v_intra_maskh, v_intra_maskv, v_intra_maskhn, v_intra_maskvn; + vector unsigned char tmp7, tmp8, tmp9, tmp10, v_c1, v_cbp1, v_cbp2, v_pocl, v_poch; + vector signed short v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; + vector signed short idx0; + vector signed short tmp00, tmp01, tmp02, tmp03; + vector unsigned char v_zero = (vector unsigned char) {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p'}; + v_three = (vector signed short) vec_ld (0, (vector signed short *) mv_const); + + vector unsigned char v_coef_mask = vec_ld(0, (vector unsigned char *)mv_const); + vector unsigned char v_coef_mask_hi = vec_splat(v_coef_mask, 0); + vector unsigned char v_coef_mask_lo = vec_splat(v_coef_mask, 1); + v_coef_mask = vec_sld(v_coef_mask_hi, v_coef_mask_lo, 8); + vector unsigned char v_bit_mask = vec_sub(vec_splat_u8(7), vec_lvsl(0, (unsigned char *)0)); + v_bit_mask = vec_sld(vec_sld(v_bit_mask, v_bit_mask, 8), v_bit_mask, 8); + v_bit_mask = vec_sl(vec_splat_u8(1), v_bit_mask); + tmp5 = (vector signed short) vec_and(v_coef_mask, v_bit_mask); + + intra[0] = 1; + tmp8 = vec_ld (0, (vector unsigned char *) intra); + tmp9 = vec_ld (0, (vector unsigned char *) mv_const); + tmp10 = vec_ld (0, (vector unsigned char *) mv_const); + v_permv = vec_ld (0, (vector unsigned char *) mv_const); + v_permh = vec_ld (0, (vector unsigned char *) mv_const); + tmp6 = vec_ld (0, (vector signed short *) mv_const); + + tmp8 = vec_splat((vector unsigned char) tmp8, 0); + tmp9 = vec_splat((vector unsigned char) tmp9, 12); + tmp10 = vec_splat((vector unsigned char) tmp10, 12); + tmp9 = vec_sld ((vector unsigned char) tmp9,(vector unsigned char) tmp8, 12); + tmp10 = vec_sld ((vector unsigned char) tmp10, (vector unsigned char) tmp8, 12); + v_intra_maskv = vec_or (tmp9, tmp8); + v_intra_maskh = vec_or (tmp10, tmp8); + v_intra_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskv, (vector unsigned char) v_zero); + v_intra_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskh, (vector unsigned char) v_zero); + + tmp9 = vec_lvsl (4 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permv); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskv = vec_or (v_cbp1, v_cbp2); + + tmp9 = vec_lvsl (12 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permh); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskh = vec_or (v_cbp1, v_cbp2); + + v_cbp_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + intra[0] =0; + intra[1] =1; + intra[2] =2; + intra[3] =3; + intra[4] =4; + intra[5] = 5; + intra[6] =6; + intra[7] =7; + intra[8] =8; + intra[9] =9; + intra[10] =9; + intra[11] =9; + intra[12] = 0xff; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v0 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v1 = vec_sld (v0, v0, 15); + v1 = (vector signed short) vec_pack (v1, v0); + + v2 = vec_sld (v1, v1, 2); + v3 = vec_sld (v1, v1, 10); + + v4 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v2); + v5 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v3); + v6 = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3); + } + else { + v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (0, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v4); + tmp4 = vec_and (tmp4, v5); + tmp1 = vec_and (tmp1, v6); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + v0 = vec_ld (0, (vector signed short *) mv_const); + v1 = vec_ld (16, (vector signed short *) mv_const); + v4 = vec_ld (64, (vector signed short *) mv_const); + v5 = vec_ld (80, (vector signed short *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v8, + (vector unsigned char) v8, (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v9, (vector unsigned char) v9, + (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + v2 = vec_ld (32, (vector signed short *) mv_const); + v3 = vec_ld (48, (vector signed short *) mv_const); + v6 = vec_ld (96, (vector signed short *) mv_const); + v7 = vec_ld (112,(vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned int) tmp00, (vector unsigned int) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned int) tmp02, (vector unsigned int) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskv = vec_or (tmp0, tmp2); + v_vec_maskv = vec_or (v_vec_maskv, tmp3); + + intra[0] = 1; + intra[1] = 1; + intra[2] = 2; + intra[3] = 3; + intra[4] = 2; + intra[5] = 2; + intra[6] = 2; + intra[7] = 1; + intra[8] = 1; + intra[9] = 5; + intra[10] = 5; + intra[11] = 5; + + intra[13] = 0; + intra[14] = 0; + intra[15] = 0; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v8 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v9 = vec_sld (v8, v8, 15); + v9 = (vector signed short) vec_pack (v9, v8); + + v10 = vec_sld (v9, v9, 2); + v11 = vec_sld (v9, v9, 10); + + v8 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v10); + v9 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v11); + v10 = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11); + } + else { + v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + +if (1){ + int m; + unsigned char toto2[16] __attribute__((aligned(16))); + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + + printf("\nv_zero\n"); + + vec_st (v_zero, 0, (unsigned char *) toto2); + for (m=0; m< 16; m++) {printf("%c ", toto2[m]);} + printf("\n"); +} + + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + +if (1){ + vector unsigned char vres = + (vector unsigned char){'a','1','b','2','c','3','d','4','e','5','f','6','g','7','h','8'}; + unsigned char toto2[16] __attribute__((aligned(16))); + int m; + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + printf("\n"); + if (!vec_all_eq (vres, v_c1)) + abort(); +} + + v_pocl = vec_ld (32, (vector unsigned char *) mv_const); + v_poch = vec_ld (48, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v8); + tmp4 = vec_and (tmp4, v9); + tmp1 = vec_and (tmp1, v10); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + + v_permv= vec_ld (0, (vector unsigned char *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + tmp2 = vec_perm (v0, v0, v_permv); + tmp3 = vec_sub (vec_max (v8, v0), vec_min (v8, v0)); + tmp4 = vec_sub (vec_max (v8, tmp2), vec_min (v8, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v2, v2, v_permv); + tmp5 = vec_sub (vec_max (v9, v2), vec_min (v9, v2)); + tmp6 = vec_sub (vec_max (v9, tmp2), vec_min (v9, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v1, v1, v_permv); + tmp3 = vec_sub (vec_max (v0, v1), vec_min (v0, v1)); + tmp4 = vec_sub (vec_max (v0, tmp2), vec_min (v0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v3, v3, v_permv); + tmp5 = vec_sub (vec_max (v2, v3), vec_min (v2, v3)); + tmp6 = vec_sub (vec_max (v2, tmp2), vec_min (v2, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v4, v4, v_permv); + tmp3 = vec_sub (vec_max (v1, v4), vec_min (v1, v4)); + tmp4 = vec_sub (vec_max (v1, tmp2), vec_min (v1, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v6, v6, v_permv); + tmp5 = vec_sub (vec_max (v3, v6), vec_min (v3, v6)); + tmp6 = vec_sub (vec_max (v3, tmp2), vec_min (v3, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + + tmp2 = vec_perm (v5, v5, v_permv); + tmp3 = vec_sub (vec_max (v4, v5), vec_min (v4, v5)); + tmp4 = vec_sub (vec_max (v4, tmp2), vec_min (v4, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v7, v7, v_permv); + tmp5 = vec_sub (vec_max (v6, v7), vec_min (v6, v7)); + tmp6 = vec_sub (vec_max (v6, tmp2), vec_min (v6, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned short) tmp00, (vector unsigned short) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned short) tmp02, (vector unsigned short) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskh = vec_or (tmp0, tmp2); + v_vec_maskh = vec_or (v_vec_maskh, tmp3); + + + v_intra_maskvn = vec_nor (v_intra_maskv, v_intra_maskv); + v_intra_maskhn = vec_nor (v_intra_maskh, v_intra_maskh); + v_cbp_maskvn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskhn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + v_cbp_maskv = vec_and (v_cbp_maskv, v_intra_maskvn); + v_cbp_maskh = vec_and (v_cbp_maskh, v_intra_maskhn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_intra_maskvn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_cbp_maskvn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_intra_maskhn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_cbp_maskhn); + + tmp9 = vec_splat_u8(2); + tmp8 = vec_splat_u8(1); + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + + v_bSv = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskv); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskv); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskv); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSv = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSv); + + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + v_bSh = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskh); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskh); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskh); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSh = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSh); + + v_permh = (vector unsigned char) vec_ld (0 , (vector unsigned char *) mv_const); + v_permv = (vector unsigned char) vec_ld (0, (vector unsigned char *) mv_const); + v_bSv = vec_and (v_bSv, v_permv); + v_bSh = vec_and (v_bSh, v_permh); + + vec_st (v_bSv, 0, (unsigned char *) mv_const); + vec_st (v_bSh, 0, (unsigned char *) mv_const); + + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSh = vec_mergeh (v_bSh, v_bSh); + v_bSh = vec_mergeh (v_bSh, v_bSh); + + vec_st (v_bSv, 0, (vector unsigned char *) mv_const); + vec_st (v_bSh, 0,(vector unsigned char *) mv_const); +} + + +int main(int argc, char **argv) +{ + char toto[32] __attribute__((aligned(16))); + + foo(toto, toto, 0, 0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c b/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c new file mode 100644 index 000000000..a2aa11145 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Check that "volatile" type qualifier is propagated to vector type. */ + +#include <altivec.h> + +vector float *f (volatile vector float *a) +{ + return a; /* { dg-warning "discards 'volatile' qualifier" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/asm-es-1.c b/gcc/testsuite/gcc.target/powerpc/asm-es-1.c new file mode 100644 index 000000000..fe3e899d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/asm-es-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +static inline void __attribute__((always_inline)) +f1 (void) +{ + long unused; + asm volatile ("" : "=es" (unused) :: "memory"); +} + +static void __attribute__((noinline)) +f2 (long *val) +{ + *val = 0x1234; +} + +static long __attribute__((noinline)) +test (void) +{ + f1 (); + { + long val; + f2 (&val); + return val; + } +} + +int +main (void) +{ + return test () != 0x1234; +} diff --git a/gcc/testsuite/gcc.target/powerpc/asm-es-2.c b/gcc/testsuite/gcc.target/powerpc/asm-es-2.c new file mode 100644 index 000000000..d2b46913b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/asm-es-2.c @@ -0,0 +1,37 @@ +/* { dg-options "-O2" } */ +void +f1 (int *p, int x) +{ + asm ("asm1 %0" : "=es" (p[x])); +} + +void +f2 (int *p) +{ + while (1) + { + p += 4; + asm ("asm2%U0 %0" : "=m<>" (*p)); + } +} + +void +f3 (int *p) +{ + while (1) + { + p += 4; + asm ("asm3%U0 %0" : "=es" (*p)); + } +} + +void +f4 (int *p) +{ + asm ("asm4 %0" : "=es" (p[100])); +} + +/* { dg-final { scan-assembler "asm1 %?r?3,%?r?4" } } */ +/* { dg-final { scan-assembler "asm2u 16\\(%?r?3\\)" } } */ +/* { dg-final { scan-assembler "asm3 0\\(%?r?3\\)" } } */ +/* { dg-final { scan-assembler "asm4 400\\(%?r?3\\)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/asm-y.c b/gcc/testsuite/gcc.target/powerpc/asm-y.c new file mode 100644 index 000000000..7d5a6a617 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/asm-y.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* Test that %yN does not cause an internal error if used incorrectly. */ + +int f(int *a) +{ + asm ("#%y0" : "=m"(a[2])); /* { dg-error "try using the 'Z' constraint" } */ + asm ("#%y0" : "=m"(a[1])); /* { dg-error "try using the 'Z' constraint" } */ + asm ("#%y0" : "=m"(a[0])); +} diff --git a/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c b/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c new file mode 100644 index 000000000..e86aa8a5d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mavoid-indexed-addresses -mno-altivec -mno-vsx" } */ + +/* { dg-final { scan-assembler-not "lbzx" } } + +/* Ensure that an indexed load is not generated with + -mavoid-indexed-addresses. */ + +char +do_one (char *base, unsigned long offset) +{ + return base[offset]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/block-move-1.c b/gcc/testsuite/gcc.target/powerpc/block-move-1.c new file mode 100644 index 000000000..7b6623fbe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/block-move-1.c @@ -0,0 +1,14 @@ +/* Test that we bump up low values of -mblock-move-inline-limit */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mblock-move-inline-limit=8" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *memcpy (void *, const void *, size_t); + +void +cpy16 (void *x, void *y) +{ + memcpy (x, y, 16); +} + +/* { dg-final { scan-assembler-not "memcpy" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/block-move-2.c b/gcc/testsuite/gcc.target/powerpc/block-move-2.c new file mode 100644 index 000000000..ffaf9ef05 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/block-move-2.c @@ -0,0 +1,14 @@ +/* Test that we honor -mblock-move-inline-limit. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mblock-move-inline-limit=128" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *memcpy (void *, const void *, size_t); + +void +cpy128 (void *x, void *y) +{ + memcpy (x, y, 128); +} + +/* { dg-final { scan-assembler-not "memcpy" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bswap-run.c b/gcc/testsuite/gcc.target/powerpc/bswap-run.c new file mode 100644 index 000000000..484908a81 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap-run.c @@ -0,0 +1,102 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-options "-O2 -std=gnu99" } */ + +extern void abort (void); + +static unsigned char bytes[] = { 0, 1, 2, 0x80, 0xff }; + +unsigned short b16a (unsigned short *p) { return __builtin_bswap16 (*p); } +void b16b (unsigned short *p, unsigned short a) { *p = __builtin_bswap16 (a); } +int b16c (unsigned short a) { return __builtin_bswap16 (a); } + +unsigned int b32a (unsigned int *p) { return __builtin_bswap32 (*p); } +void b32b (unsigned int *p, unsigned int a) { *p = __builtin_bswap32 (a); } +static unsigned int b32c (unsigned int a) { return __builtin_bswap32 (a); } + +unsigned long long b64a (unsigned long long *p) { return __builtin_bswap64 (*p); } +void b64b (unsigned long long *p, unsigned long long a) { *p = __builtin_bswap64 (a); } +unsigned long long b64c (unsigned long long a) { return __builtin_bswap64 (a); } + +int +main (void) +{ + unsigned i1, i2, i3, i4, i5; + unsigned b1, b2, b3, b4, b5; + unsigned short b16_inp, b16_exp, b16_var; + unsigned int b32_inp, b32_exp, b32_var; + unsigned long long b64_inp, b64_exp, b64_var; + + for (i1 = 0; i1 < sizeof (bytes); i1++) + { + b1 = bytes[i1]; + for (i2 = 0; i2 < sizeof (bytes); i2++) + { + b2 = bytes[i2]; + b16_inp = (b1 << 8) | b2; + b16_exp = (b2 << 8) | b1; + + if (b16a (&b16_inp) != b16_exp) + abort (); + + b16b (&b16_var, b16_inp); + if (b16_var != b16_exp) + abort (); + + if (b16c (b16_inp) != b16_exp) + abort (); + + for (i3 = 0; i3 < sizeof (bytes); i3++) + { + b3 = bytes[i3]; + for (i4 = 0; i4 < sizeof (bytes); i4++) + { + b4 = bytes[i4]; + b32_inp = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4; + b32_exp = (b4 << 24) | (b3 << 16) | (b2 << 8) | b1; + + if (b32a (&b32_inp) != b32_exp) + abort (); + + b32b (&b32_var, b32_inp); + if (b32_var != b32_exp) + abort (); + + if (b32c (b32_inp) != b32_exp) + abort (); + + for (i5 = 0; i5 < sizeof (bytes); i5++) + { + b5 = bytes[i5]; + b64_inp = (((unsigned long long)b32_inp) << 32) | b5; + b64_exp = (((unsigned long long)b5) << 56) | b32_exp; + + if (b64a (&b64_inp) != b64_exp) + abort (); + + b64b (&b64_var, b64_inp); + if (b64_var != b64_exp) + abort (); + + if (b64c (b64_inp) != b64_exp) + abort (); + + b64_inp = (((unsigned long long)b5) << 56) | b32_inp; + b64_exp = (((unsigned long long)b32_exp) << 32) | b5; + + if (b64a (&b64_inp) != b64_exp) + abort (); + + b64b (&b64_var, b64_inp); + if (b64_var != b64_exp) + abort (); + + if (b64c (b64_inp) != b64_exp) + abort (); + } + } + } + } + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bswap16.c b/gcc/testsuite/gcc.target/powerpc/bswap16.c new file mode 100644 index 000000000..5eea4f774 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap16.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "lhbrx" } } */ +/* { dg-final { scan-assembler "sthbrx" } } */ + +unsigned short us; +unsigned int load_bswap16 (unsigned short *p) { return __builtin_bswap16 (*p); } +void store_bswap16 (unsigned int a) { us = __builtin_bswap16 (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/bswap32.c b/gcc/testsuite/gcc.target/powerpc/bswap32.c new file mode 100644 index 000000000..1b1e189aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap32.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "lwbrx" } } */ +/* { dg-final { scan-assembler "stwbrx" } } */ + +unsigned int ui; +unsigned int load_bswap32 (unsigned int *p) { return __builtin_bswap32 (*p); } +void store_bswap32 (unsigned int a) { ui = __builtin_bswap32 (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-1.c b/gcc/testsuite/gcc.target/powerpc/bswap64-1.c new file mode 100644 index 000000000..480e1cd7c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap64-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mno-popcntd -mcpu=power5" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-final { scan-assembler "lwbrx" } } */ +/* { dg-final { scan-assembler "stwbrx" } } */ + +unsigned long ul; +unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); } +void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-2.c b/gcc/testsuite/gcc.target/powerpc/bswap64-2.c new file mode 100644 index 000000000..6c3d8ca05 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap64-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mpopcntd" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-final { scan-assembler "ldbrx" } } */ +/* { dg-final { scan-assembler "stdbrx" } } */ + +unsigned long ul; +unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); } +void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-3.c b/gcc/testsuite/gcc.target/powerpc/bswap64-3.c new file mode 100644 index 000000000..7f1138cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap64-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mcpu=cell" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_ppu_ok } */ +/* { dg-final { scan-assembler "ldbrx" } } */ +/* { dg-final { scan-assembler "stdbrx" } } */ + +unsigned long ul; +unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); } +void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-4.c b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c new file mode 100644 index 000000000..826999cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-options "-O2 -mpowerpc64" } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-final { scan-assembler-times "lwbrx" 2 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 2 } } */ + +long long swap_load (long long *a) { return __builtin_bswap64 (*a); } +long long swap_reg (long long a) { return __builtin_bswap64 (a); } +void swap_store (long long *a, long long b) { *a = __builtin_bswap64 (b); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c new file mode 100644 index 000000000..f2bc7ffb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c new file mode 100644 index 000000000..220be5716 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c new file mode 100644 index 000000000..4b437291e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c new file mode 100644 index 000000000..d73328ac4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c new file mode 100644 index 000000000..cc6adba80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c new file mode 100644 index 000000000..9c748d973 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c new file mode 100644 index 000000000..abdb3b0ca --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c new file mode 100644 index 000000000..ec7fc3031 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c new file mode 100644 index 000000000..aa1da5245 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target powerpc_fprs } } */ +/* { dg-options "-O2 -fpic" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "lfs" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c new file mode 100644 index 000000000..312642e68 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target powerpc_fprs } } */ +/* { dg-options "-O2" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "lfs" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/const-compare.c b/gcc/testsuite/gcc.target/powerpc/const-compare.c new file mode 100644 index 000000000..a09957d34 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/const-compare.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-darwin* && lp64 } } } */ +/* { dg-options "-O1 -static" } */ +typedef unsigned long long uint64_t; + +static int +match(name, pat) + uint64_t *name, *pat; +{ + int ok=0, negate_range; + uint64_t c, k; + + c = *pat++; + switch (c & 0xffffffffffULL) { + case ((uint64_t)(('[')|0x8000000000ULL)): + if ((negate_range = ((*pat & 0xffffffffffULL) == ((uint64_t)(('!')|0x8000000000ULL)) )) != '\0') + ++pat; + while (((c = *pat++) & 0xffffffffffULL) ) + if ((*pat & 0xffffffffffULL) == ((uint64_t)(('-')|0x8000000000ULL))) + { + pat += 2; + } + + if (ok == negate_range) + return(0); + break; + } + return(*name == '\0'); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c new file mode 100644 index 000000000..3b13c6236 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler "li r3,12345\n\t(bl|jbsr) " } } */ + +/* Check that zero-size structures don't affect parameter passing. */ + +struct empty { }; +extern void foo (struct empty e, int a); +void bar (void) { + struct empty e; + foo (e, 12345); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c new file mode 100644 index 000000000..68540b8a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct b +{ + long long t; + int i; +}; + +struct c +{ + double d; + int i; +}; + +struct n +{ + long long ll; + int tt; + struct c d; + struct b h; + int t; +}; +int f[sizeof(struct n)!=48?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c new file mode 100644 index 000000000..5d01572a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct A +{ + long long a; + unsigned char b; +}; + +struct D +{ + unsigned char y; + struct A x; + unsigned char z; +}; + +struct E +{ + long long d; + unsigned char e; +}; + +struct y +{ + struct A b2; + struct D b3; + struct E b4; +}; + +int f[sizeof(struct y)!=56?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c new file mode 100644 index 000000000..5f5764368 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-final { scan-assembler ".comm\[\t \]_x,12,2" } } */ +/* { dg-final { scan-assembler-not ".space 7" } } */ +/* PR 23071 */ + +struct Test { + double D __attribute__((packed,aligned(4))); + short X; +} x; + +struct { + char x; + struct Test t; +} b = { 1, { 2, 3 } }; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c new file mode 100644 index 000000000..4764831e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-darwin* } } */ + +/* You might think you'd need -maltivec for this, but actually you + don't; GCC will happily do everything in GPRs, and it still + tests that the ABI is correct. */ + +#include <stdio.h> +#include <stdlib.h> + +#define vector __attribute__((vector_size(16))) + +int main(void) +{ + vector unsigned int v = { 100, 200, 300, 400 }; + vector unsigned int w = { 4, 5, 6, 7 }; + char x[64]; + sprintf (x, "%lvu,%d,%lvu", v, 1, w); + if (strcmp (x, "100 200 300 400,1,4 5 6 7") != 0) + { + puts (x); + abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c new file mode 100644 index 000000000..021abc8fe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ +struct f +{ + int i; + long long ll; +}; + +int f[sizeof(struct f)!=12?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c new file mode 100644 index 000000000..d146c46ed --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ +struct f +{ + long long ll; + int i; +}; + +int f[sizeof(struct f)!=16?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c new file mode 100644 index 000000000..4965c5bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct A +{ + long long a; + unsigned char b; +}; + +struct B +{ + struct A x; + unsigned char z; +}; + +struct C +{ + long d; + unsigned char e; +}; + +struct z +{ + struct A b2; + struct B b3; + struct C b4; +}; + +int f[sizeof(struct z)!=48?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c new file mode 100644 index 000000000..1892e15bc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct a +{ + int tt; + long long t; + int i; +}; + +struct g +{ + int tt; + struct a d; + int t; +}; + +int f[sizeof(struct g)!=24?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c new file mode 100644 index 000000000..8af61ddac --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct b +{ + long long t; + int i; +}; +struct h +{ + int tt; + struct b d; + int t; +}; + +int f[sizeof(struct h)!=24?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c new file mode 100644 index 000000000..eac0d12d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ + +struct c +{ + double d; + int i; +}; + +struct j +{ + int tt; + struct c d; + int t; +}; + +int f[sizeof(struct j)!=24?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c new file mode 100644 index 000000000..fa5bd017f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct b +{ + long long t; + int i; +}; + +struct l +{ + int i; + double d; +}; +struct k +{ + int tt; + struct l d; + struct b h; + int t; +}; + +int f[sizeof(struct k)!=36?-1:1]; diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c new file mode 100644 index 000000000..2f147d073 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c @@ -0,0 +1,11 @@ +/* Check that sizeof(bool) is 4 if we don't use special options. */ +/* Matt Austern <austern@apple.com> */ +/* { dg-do run { target { powerpc*-*-darwin* && ilp32 } } } */ + +int dummy1[sizeof(_Bool) - 3]; +int dummy2[5 - sizeof(_Bool)]; + +int main() +{ + return sizeof(_Bool) == 4 ? 0 : 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c new file mode 100644 index 000000000..fdbe1a2a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c @@ -0,0 +1,12 @@ +/* Check that sizeof(bool) is 1 if we use the -mone-byte-bool option. */ +/* Matt Austern <austern@apple.com> */ +/* { dg-do run { target powerpc*-*-darwin* } } */ +/* { dg-options "-mone-byte-bool" } */ + +int dummy1[sizeof(_Bool)]; +int dummy2[2 - sizeof(_Bool)]; + +int main() +{ + return sizeof(_Bool) == 1 ? 0 : 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c new file mode 100644 index 000000000..71ee094bf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-mcpu=G3 -funwind-tables" } */ +/* { dg-final { scan-assembler "bl save_world" } } */ +/* { dg-final { scan-assembler ".byte\t0x6b" } } */ + +/* Verify that on Darwin, even with -mcpu=G3, __builtin_eh_return + saves Altivec registers using save_world, and reports their + location in its EH information. */ + +long offset; +void *handler; + +extern void setup_offset(void); + +void foo(void) +{ + __builtin_unwind_init (); + setup_offset(); + __builtin_eh_return (offset, handler); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c b/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c new file mode 100644 index 000000000..8e4259af3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c @@ -0,0 +1,119 @@ +/* { dg-do run { target powerpc*-*-darwin* } } */ +/* { dg-options "" } */ +/* No options so 'long long' can be used. */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +typedef unsigned long long uint64_t; +typedef uint64_t ldbits[2]; + +union ldu +{ + ldbits lb; + long double ld; +}; + +static const struct { + ldbits a; + ldbits b; + ldbits result; +} single_tests[] = { + /* Test of values that add to near +Inf. */ + { { 0x7FEFFFFFFFFFFFFFLL, 0xFC88000000000000LL }, + { 0x7C94000000000000LL, 0x0000000000000000LL }, + { 0x7FEFFFFFFFFFFFFFLL, 0x7C80000000000000LL } }, + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x792FFFFFFFFFFFFFLL, 0x0000000000000000LL }, + { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } }, + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x7930000000000000LL, 0xF5DFFFFFFFFFFFFFLL }, + /* correct result is: { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } */ + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Test of values that add to +Inf. */ + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x7930000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Tests of Inf addition. */ + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Test of Inf addition producing NaN. */ + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0xFFF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x0000000000000000LL } }, + /* Tests of NaN addition. */ + { { 0x7FF8000000000000LL, 0x0000000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x7FF8000000000000LL } }, + { { 0x7FF8000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x7FF8000000000000LL } }, + /* Addition of positive integers, with interesting rounding properties. */ + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0x4650000000000009LL, 0xC2FFFFFFFFFFFFF2LL }, + /* correct result is: { 0x4691000000000001LL, 0xC32C000000000000LL } */ + { 0x4691000000000001LL, 0xc32bfffffffffffeLL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0x4650000000000008LL, 0x42F0000000000010LL }, + { 0x4691000000000001LL, 0xC32E000000000000LL } }, + { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL }, + { 0x4340000000000000LL, 0x3FF0000000000000LL }, + { 0x46A0000000000000LL, 0x0000000000000000LL } }, + { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL }, + { 0x4340000000000000LL, 0x0000000000000000LL }, + { 0x46A0000000000000LL, 0xBFF0000000000000LL } }, + /* Subtraction of integers, with cancellation. */ + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC690000000000000LL, 0xC330000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC330000000000000LL, 0x0000000000000000LL }, + { 0x4690000000000000LL, 0x0000000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC330000000000000LL, 0x3FA0000000000000LL }, + { 0x4690000000000000LL, 0x3FA0000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC690000000000000LL, 0x3FA0000000000000LL }, + /* correct result is: { 0x4330000000000000LL, 0x3FA0000000000000LL } */ + { 0x4330000000000000LL, 0x0000000000000000LL } } +}; + +static int fail = 0; + +static void +run_single_tests (void) +{ + size_t i; + for (i = 0; i < sizeof (single_tests) / sizeof (single_tests[0]); i++) + { + union ldu a, b, result, expected; + memcpy (a.lb, single_tests[i].a, sizeof (ldbits)); + memcpy (b.lb, single_tests[i].b, sizeof (ldbits)); + memcpy (expected.lb, single_tests[i].result, sizeof (ldbits)); + result.ld = a.ld + b.ld; + if (memcmp (result.lb, expected.lb, + result.ld == result.ld ? sizeof (ldbits) : sizeof (double)) + != 0) + { + printf ("FAIL: %016llx %016llx + %016llx %016llx\n", + a.lb[0], a.lb[1], b.lb[0], b.lb[1]); + printf (" = %016llx %016llx not %016llx %016llx\n", + result.lb[0], result.lb[1], expected.lb[0], expected.lb[1]); + fail = 1; + } + } +} + +int main(void) +{ + run_single_tests(); + if (fail) + abort (); + else + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c new file mode 100644 index 000000000..0692b3d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c @@ -0,0 +1,22 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc64 } */ +/* { dg-options "-mcpu=G5" } */ + +#include <stdlib.h> + +int msw(long long in) +{ + union { + long long ll; + int i[2]; + } ud; + ud.ll = in; + return ud.i[0]; +} + +int main() +{ + if (msw(1) != 0) + abort(); + exit(0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c b/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c new file mode 100644 index 000000000..9e53b7b22 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mpowerpc64" } */ + +typedef struct Nlm_rect { + short sh1; + short sh2; + short sh3; + short sh4; +} S8; + +typedef struct udv_mouse_select { + short Action_type; + S8 rcClip; + int pgp; + } UDVselect; + +UDVselect ms; +int UDV(S8 rcClip); + +int main() +{ + ms.rcClip.sh1 = 1; + ms.rcClip.sh4 = 4; + return UDV(ms.rcClip); +} + +int UDV(S8 rcClip){ + + return !(rcClip.sh1 == 1 && rcClip.sh4 == 4); +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c new file mode 100644 index 000000000..c45a90f0f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c @@ -0,0 +1,19 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-skip-if "need to be able to execute AltiVec" { ! { powerpc_altivec_ok && vmx_hw } } } */ +/* { dg-options "-maltivec" } */ + +/* With altivec turned on, Darwin wants to save the world but we did not mark lr as being saved any more + as saving the lr is not needed for saving altivec registers. */ + +int main (void) +{ + __label__ l1; + void __attribute__((used)) q(void) + { + goto l1; + } + + l1:; + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c b/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c new file mode 100644 index 000000000..be4e43892 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c @@ -0,0 +1,87 @@ +/* Check for Darwin m64 that we do not try to pass & return by value for a + struct exceeding the number of arg FPRs (the struct here straddles the + split-point). */ +/* { dg-do run { target { powerpc*-*-darwin* && lp64 } } } */ + +extern void abort (void); + +/*#define DEBUG*/ + +#ifdef DEBUG +extern int printf (const char *, ...); +extern int printf$LDBL128 (const char *, ...); +#endif + +typedef struct fourteen { + long double a, b, c, d, e, f, g; +} fourteen_t ; + +fourteen_t foo (fourteen_t, fourteen_t) __attribute__ ((noinline)); + +fourteen_t +foo (fourteen_t aa, fourteen_t bb) +{ + fourteen_t r; + + r.a = aa.a + bb.a; + r.b = aa.b + bb.b; + r.c = aa.c + bb.c; + r.d = aa.d + bb.d; + r.e = aa.e + bb.e; + r.f = aa.f + bb.f; + r.g = aa.g + bb.g; + +#ifdef DEBUG +#ifdef __ppc64__ + printf +#else + printf$LDBL128 +#endif + ("%Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg: " + "%Lg %Lg %Lg %Lg %Lg %Lg %Lg\n", + aa.a, aa.b, aa.c, aa.d, aa.e, aa.f, aa.g, + bb.a, bb.b, bb.c, bb.d, bb.e, bb.f, bb.g, + r.a, r.b, r.c, r.d, r.e, r.f, r.g); + printf ("aa.g %ll16x %ll16x\nbb.g %ll16x %ll16x\n", + *(unsigned long long*)&aa.g, + *(unsigned long long*)(((char *)&aa.g)+8), + *(unsigned long long*)&bb.g, + *(unsigned long long*)(((char *)&bb.g)+8)); + +#endif + + __asm__ (""); /* double make sure we don't get inlined */ + return r; +} + +int +main (void) +{ + fourteen_t x = { 1.L, 2.L, 3.L, 4.L, 5.L, 6.L,-12.3456789123456789L }; + fourteen_t y = { 8.L, 9.L, 10.L, 11.L, 12.L, 13.L, 12.3456789123456789L }; + fourteen_t z ; + long double zz; + + z = foo (x,y); + zz = x.g + y.g; +#ifdef DEBUG +#ifdef __ppc64__ + printf +#else + printf$LDBL128 +#endif + (" z: %Lg %Lg %Lg %Lg %Lg %Lg %Lg\n" + "ret: %ll16x %ll16x\nzz : %ll16x %ll16x\n", + z.a, z.b, z.c, z.d, z.e, z.f, z.g, + *(unsigned long long*)&z.g, + *(unsigned long long*)(((char *)&z.g)+8), + *(unsigned long long*)&zz, + *(unsigned long long*)(((char *)&zz)+8)); +#endif + + /* Yes, we really do want to do an equality test here. */ + if (z.g != zz) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c b/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c new file mode 100644 index 000000000..e185cdf0e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c @@ -0,0 +1,634 @@ +/* Darwin 64-bit ABI testing */ +/* { dg-do run { target { powerpc*-*-darwin* && lp64 } } } */ +/* { dg-options "-std=c99 -maltivec" } */ + +/* Set this if 8-byte structs are being passed as integers. */ +/* #define STRUCT8INT */ + +#include <stdarg.h> +#include <stdio.h> +#include <complex.h> +#include <altivec.h> + +extern void abort (void); + +struct s3c { char ch[3]; }; +struct ssc { short sh; char ch; }; +struct sif { int i; float f; }; +struct sfi { float f; int i; }; +struct sfii { float f; int i; int j; }; +struct sfil { float f; int i; long l; }; +struct sfif { float f; int i; float g; }; +struct sfill { float f; int i; long l, m; }; +struct sfl { float f; long l; }; +struct sfldl { float f; long l1; double d; long l2; }; +struct sfpp { float f; char *p1; char *p2; }; + + +struct sff { float f1, f2; }; +struct sfff { float f1, f2, f3; }; +struct sffff { float f1, f2, f3, f4; }; + +struct sfD { float f; long double D; }; + +struct sidi { int i1; double d; int i2; }; + +struct sdd { double d1, d2; }; +struct sddd { double d1, d2, d3; }; +struct sdddd { double d1, d2, d3, d4; }; +struct s3d { double d[3]; }; + +struct vr { union { int ielts[4]; float felts[4]; } elts; }; + +typedef struct +{ + unsigned long gprs[32]; + double fprs[32]; + struct vr vrs[32]; + unsigned char stack[1000]; +} reg_parms_t; + +reg_parms_t gparms; + +#define TESTFN(RET,NAME,PARAMS) \ +RET NAME PARAMS; \ +RET dummy_ ## NAME PARAMS \ +{ \ + __asm__("b end_" #NAME "\n_" # NAME ":\n\t" SAVE_STATE "b _dummy_" # NAME "\n\tend_" #NAME ":\n\n" ); \ +} + +#define SAVE_STATE \ +SAVE_GPR(0) \ +SAVE_GPR(1) \ +SAVE_GPR(3) \ +SAVE_GPR(4) \ +SAVE_GPR(5) \ +SAVE_GPR(6) \ +SAVE_GPR(7) \ +SAVE_GPR(8) \ +SAVE_GPR(9) \ +SAVE_GPR(10) \ +SAVE_FPR(0) \ +SAVE_FPR(1) \ +SAVE_FPR(2) \ +SAVE_FPR(3) \ +SAVE_FPR(4) \ +SAVE_FPR(5) \ +SAVE_FPR(6) \ +SAVE_FPR(7) \ +SAVE_FPR(8) \ +SAVE_FPR(9) \ +SAVE_FPR(10) \ +SAVE_FPR(12) \ +SAVE_FPR(13) \ +SAVE_VR(0) \ +SAVE_VR(1) \ +SAVE_VR(2) \ +SAVE_VR(3) \ +SAVE_VR(4) \ +SAVE_STACK(112) \ +SAVE_STACK(120) \ +SAVE_STACK(128) \ +SAVE_STACK(136) \ +SAVE_STACK(144) \ + + +#ifdef __LP64__ +#define SAVE_GPR(N) "std r" #N "," #N "*8(r25)\n\t" +#define SAVE_FPR(N) "stfd f" #N "," #N "*8+256(r25)\n\t" +#define SAVE_VR(N) "li r26," #N "*16+512\n\tstvx v" #N ",r25,r26\n\t" +#define SAVE_STACK(N) "ld r26," #N "(r1)\n\tstd r26," #N "+1024(r25)\n\t" +#else +#define SAVE_GPR(N) "stw r" #N "," #N "*4(r25)\n\t" +#define SAVE_FPR(N) "stfd f" #N "," #N "*8+128(r25)\n\t" +#define SAVE_VR(N) +#define SAVE_STACK(N) +#endif + +TESTFN(void, fffi, (float x, float y, int z)) + +#define clearall \ +__asm__ volatile ( \ +"\n\t" \ +"li r3,0x333\n\t" \ +"li r4,0x444 \n\t" \ +"li r5,0x555\n\t" \ +"li r6,0x666\n\t" \ +"li r7,0x777\n\t" \ +"li r8,0x888\n\t" \ +"li r9,0x999\n\t" \ +"li r10,0xaaa\n\t" \ +"fsub f0,f0,f0\n\t" \ +"fsub f1,f1,f1\n\t" \ +"fsub f2,f2,f2\n\t" \ +"fsub f3,f3,f3\n\t" \ +"fsub f4,f4,f4\n\t" \ +"fsub f5,f5,f5\n\t" \ +"fsub f6,f6,f6\n\t" \ +"fsub f7,f7,f7\n\t" \ +"vsubuwm v0,v0,v0\n\t" \ +"vsubuwm v1,v1,v1\n\t" \ +"vsubuwm v2,v2,v2\n\t" \ +"vsubuwm v3,v3,v3\n\t" \ +"vsubuwm v4,v4,v4\n\t" \ +: : : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "v0", "v1", "v2", "v3", "v4" ); + +TESTFN(void, fii, (int a, int b)) +TESTFN(void, fid, (int i, double d)) +TESTFN(void, fc, (complex float z)) +TESTFN(void, fffff, (float f1, float f2, float f3, float f4)) +TESTFN(void, fdddd, (double d1, double d2, double d3, double d4)) +TESTFN(void, f_s3c_ssc, (struct s3c s1, struct ssc s2)) +TESTFN(void, f_sff, (struct sff s)) +TESTFN(void, f_sfff, (struct sfff s)) +TESTFN(void, f_sffff, (struct sffff s)) +TESTFN(void, f_sdd, (struct sdd s)) +TESTFN(void, f_sddd, (struct sddd s)) +TESTFN(void, f_sdddd, (struct sdddd s)) +TESTFN(void, f_s3d, (struct s3d s)) +TESTFN(void, f_sif, (int i, struct sif s)) +TESTFN(void, fi_sif, (int i, struct sif s)) +TESTFN(void, fi_sif_i, (int i, struct sif s, int j)) +TESTFN(void, f_sfi, (int i, struct sfi s)) +TESTFN(void, fi_sfi, (int i, struct sfi s)) +TESTFN(void, fi_sfi_if, (int i, struct sfi s, int j, float f)) +TESTFN(void, fi_sfill, (int i, struct sfill s)) +TESTFN(void, fi_sfill_i, (int i, struct sfill s, int j)) +TESTFN(void, f_sfl, (struct sfl s)) +TESTFN(void, f_sfl_sfl_sfl_sfl_sfl, (struct sfl s1, struct sfl s2, struct sfl s3, struct sfl s4, struct sfl s5)) +TESTFN(void, fi_sff, (int i, struct sff s)) +TESTFN(void, f_sfpp_p, (struct sfpp s, char *p)) +TESTFN(void, f_sfldl, (struct sfldl s)) +TESTFN(void, fi_sff_i, (int i, struct sff s, int j)) +TESTFN(void, f_sfD_sfD_sfD_sfD_sfD, (struct sfD s1, struct sfD s2, struct sfD s3, struct sfD s4, struct sfD s5)) +TESTFN(void, fi_sidi, (int i, struct sidi s)) +TESTFN(void, fifvf_sfi_dots, (int i, float f, vector float vf, struct sfi s, ...)) +TESTFN(void, fifvf_sfii_dots, (int i, float f, vector float vf, struct sfii s, ...)) + +int numerrs; + +#ifndef SKIP +static __attribute__ ((noinline)) void +check_gpr (int line, int reg, long expected) +{ + if (gparms.gprs[reg] != expected) + { + printf("%d: r%d is 0x%lx, expected 0x%lx\n", + line, reg, gparms.gprs[reg], expected); + ++numerrs; + } +} + +static __attribute__ ((noinline)) void +check_gpr_double (int line, int reg, double expected) +{ + double tmp = *((double *) &(gparms.gprs[reg])); + if (tmp != expected) + { + printf("%d: r%d is %f (0x%llx), expected %f (0x%llx)\n", + line, reg, + tmp, *((long long *) &tmp), + expected, *((long long *) &expected)); + ++numerrs; + } +} + +static __attribute__ ((noinline)) void +check_gpr_float_pair (int line, int reg, float exp1, float exp2) +{ + float tmp1 = *((float *) &(gparms.gprs[reg])); + float tmp2 = *(((float *) &(gparms.gprs[reg])) + 1); + + if (tmp1 != exp1 || tmp2 != exp2) + { + printf("%d: r%d is %f / %f (0x%llx), expected %f (0x%x) / %f (0x%x)\n", + line, reg, + tmp1, tmp2, *((long long *) &(gparms.gprs[reg])), + exp1, *((int *) &exp1), + exp2, *((int *) &exp2)); + ++numerrs; + } +} + +static __attribute__ ((noinline)) void +check_fpr (int line, int reg, double expected) +{ + if (gparms.fprs[reg] != expected) + { + printf("%d: f%d is %f (0x%llx), expected %f (0x%llx)\n", + line, reg, + gparms.fprs[reg], *((long long *) &(gparms.fprs[reg])), + expected, *((long long *) &expected)); + ++numerrs; + } +} + +static __attribute__ ((noinline)) void +check_vr_int (int reg, int n1, int n2, int n3, int n4) +{ + if (gparms.vrs[reg].elts.ielts[0] != n1 + || gparms.vrs[reg].elts.ielts[1] != n2 + || gparms.vrs[reg].elts.ielts[2] != n3 + || gparms.vrs[reg].elts.ielts[3] != n4) + { + printf("v%d is (%d,%d,%d,%d) (0x%x,0x%x,0x%x,0x%x),\n" + " expected (%d,%d,%d,%d) (0x%x,0x%x,0x%x,0x%x)\n", + reg, + gparms.vrs[reg].elts.ielts[0], + gparms.vrs[reg].elts.ielts[1], + gparms.vrs[reg].elts.ielts[2], + gparms.vrs[reg].elts.ielts[3], + gparms.vrs[reg].elts.ielts[0], + gparms.vrs[reg].elts.ielts[1], + gparms.vrs[reg].elts.ielts[2], + gparms.vrs[reg].elts.ielts[3], + n1, n2, n3, n4, + n1, n2, n3, n4 + ); + ++numerrs; + } +} + +static __attribute__ ((noinline)) void +check_vr_float (int reg, float f1, float f2, float f3, float f4) +{ + if (gparms.vrs[reg].elts.felts[0] != f1 + || gparms.vrs[reg].elts.felts[1] != f2 + || gparms.vrs[reg].elts.felts[2] != f3 + || gparms.vrs[reg].elts.felts[3] != f4) + { + printf("v%d is (%f,%f,%f,%f) (0x%x,0x%x,0x%x,0x%x),\n" + " expected (%f,%f,%f,%f) (0x%x,0x%x,0x%x,0x%x)\n", + reg, + gparms.vrs[reg].elts.felts[0], + gparms.vrs[reg].elts.felts[1], + gparms.vrs[reg].elts.felts[2], + gparms.vrs[reg].elts.felts[3], + gparms.vrs[reg].elts.ielts[0], + gparms.vrs[reg].elts.ielts[1], + gparms.vrs[reg].elts.ielts[2], + gparms.vrs[reg].elts.ielts[3], + f1, f2, f3, f4, + *((int *) &f1), *((int *) &f2), *((int *) &f3), *((int *) &f4) + ); + ++numerrs; + } +} +#endif + +int main (void) +{ + complex float cpx = 4.45f + I * 4.92f; + struct s3c s3c_loc; + struct ssc ssc_loc; + struct sfi sfi_loc; + struct sfi sfi_loc2 = { 6.3f, 0x1108 }; + struct sfii sfii_loc; + struct sfii sfii_loc2 = { 6.9f, 0x1110, 0x6372 }; + vector float vf_loc = (vector float) { 7.1f, 7.2f, 7.3f, 7.4f }; + vector int vi_loc = (vector int) { 0xabc, 0xdef, 0xfed, 0xcba }; + + __asm__ ("mr r25,%0" : : "b" (&gparms) ); + + clearall; + fii(1, 2); + check_gpr (__LINE__, 3, 1); + check_gpr (__LINE__, 4, 2); + + clearall; + fid(45, 4.5); + check_gpr (__LINE__, 3, 45); + check_fpr (__LINE__, 1, 4.5); + + clearall; + fffi(1.2f, 3.4f, 456); + check_fpr(__LINE__, 1, 1.2f); + + clearall; + fc(cpx); + /* Two floats are packed into r3 */ + check_gpr_float_pair (__LINE__, 3, 4.45f, 4.92f); + + clearall; + fffff (4.1f, 4.2f, 4.3f, 4.4f); + check_fpr (__LINE__, 1, 4.1f); + check_fpr (__LINE__, 4, 4.4f); + + clearall; + fdddd (4.1, 4.2, 4.3, 4.4); + check_fpr (__LINE__, 1, 4.1); + check_fpr (__LINE__, 4, 4.4); + + { + struct sff sff_loc = { 2.1f, 2.2f }; + clearall; + f_sff(sff_loc); +#ifdef STRUCT8INT + check_gpr_float_pair (__LINE__, 3, 2.1f, 2.2f); +#else + check_fpr(__LINE__, 1, 2.1f); + check_fpr(__LINE__, 2, 2.2f); +#endif + clearall; + fi_sff_i(65, sff_loc, 66); + check_gpr(__LINE__, 3, 65); +#ifdef STRUCT8INT + check_gpr_float_pair (__LINE__, 4, 2.1f, 2.2f); +#else + check_fpr(__LINE__, 1, 2.1f); + check_fpr(__LINE__, 2, 2.2f); +#endif + check_gpr(__LINE__, 5, 66); + } + + { + struct sfff sfff_loc = { 3.1f, 3.2f, 3.3f }; + clearall; + f_sfff(sfff_loc); + check_fpr(__LINE__, 1, 3.1f); + check_fpr(__LINE__, 2, 3.2f); + check_fpr(__LINE__, 3, 3.3f); + clearall; + f_sfff(sfff_loc); + check_fpr(__LINE__, 1, 3.1f); + check_fpr(__LINE__, 2, 3.2f); + check_fpr(__LINE__, 3, 3.3f); + } + + { + struct sffff sffff_loc = { 4.1f, 4.2f, 4.3f, 4.4f }; + clearall; + f_sffff(sffff_loc); + check_gpr_float_pair(__LINE__, 3, 4.1f, 4.2f); + check_gpr_float_pair(__LINE__, 4, 4.3f, 4.4f); + } + + { + struct sdd sdd_loc = { 2.1, 2.2 }; + clearall; + f_sdd(sdd_loc); + /* 16-byte struct is passed in two GPRs. */ + check_gpr_double(__LINE__, 3, 2.1); + check_gpr_double(__LINE__, 4, 2.2); + } + + { + struct sddd sddd_loc = { 3.1, 3.2, 3.3 }; + clearall; + f_sddd(sddd_loc); + check_fpr(__LINE__, 1, 3.1); + check_fpr(__LINE__, 2, 3.2); + check_fpr(__LINE__, 3, 3.3); + } + + { + struct sdddd sdddd_loc = { 4.1, 4.2, 4.3, 4.4 }; + clearall; + f_sdddd(sdddd_loc); + check_fpr(__LINE__, 1, 4.1); + check_fpr(__LINE__, 2, 4.2); + check_fpr(__LINE__, 3, 4.3); + check_fpr(__LINE__, 4, 4.4); + } + + { + struct s3d s3d_loc = { 89.92, 4.89, 90.9 }; + clearall; + f_s3d(s3d_loc); + check_gpr_double (__LINE__, 3, 89.92); + check_gpr_double (__LINE__, 4, 4.89); + check_gpr_double (__LINE__, 5, 90.9); + } + + { + s3c_loc.ch[0] = 'A'; + s3c_loc.ch[1] = 'B'; + s3c_loc.ch[2] = 'C'; + ssc_loc.sh = 0x1234; + ssc_loc.ch = 'D'; + clearall; + f_s3c_ssc(s3c_loc, ssc_loc); + } + + { + struct sif sif_loc_n = { 334, 4.3f }; + long floatcast; + floatcast = *((int *) &(sif_loc_n.f)); + clearall; + fi_sif(29, sif_loc_n); + check_gpr (__LINE__, 3, 29); + check_gpr (__LINE__, 4, 334LL << 32 | floatcast); +#ifdef STRUCT8INT +#else + check_fpr (__LINE__, 1, 4.3f); +#endif + clearall; + fi_sif_i(31, sif_loc_n, 33); + check_gpr (__LINE__, 3, 31); + check_gpr (__LINE__, 4, 334LL << 32 | floatcast); +#ifdef STRUCT8INT +#else + check_fpr (__LINE__, 1, 4.3f); +#endif + check_gpr (__LINE__, 5, 33); + } + + { + struct sfi sfi_loc_n = { 4.145f, 335 }; + clearall; + fi_sfi(29, sfi_loc_n); + check_gpr (__LINE__, 3, 29); +#ifdef STRUCT8INT + check_gpr (__LINE__, 4, 0x4084a3d70000014fLL); +#else + check_fpr (__LINE__, 1, 4.145f); + check_gpr (__LINE__, 4, 335); +#endif + } + + { + struct sfi sfi_loc_n = { 4.145f, 335 }; + clearall; + fi_sfi_if (29, sfi_loc_n, 65, 9.8f); + check_gpr (__LINE__, 3, 29); +#ifdef STRUCT8INT + check_gpr (__LINE__, 4, 0x4084a3d70000014fLL); +#else + check_fpr (__LINE__, 1, 4.145f); + check_gpr (__LINE__, 4, 335); +#endif + check_gpr (__LINE__, 5, 65); + check_gpr (__LINE__, 6, 0x666); +#ifdef STRUCT8INT + check_fpr (__LINE__, 1, 9.8f); +#else + check_fpr (__LINE__, 2, 9.8f); +#endif + check_gpr (__LINE__, 7, 0x777); + } + + { + struct sfill sfill_loc_n = { 4.145f, 335, 10000000000LL, 20000000000LL }; + clearall; + fi_sfill(29, sfill_loc_n); + check_gpr (__LINE__, 3, 29); + check_fpr (__LINE__, 1, 4.145f); + check_gpr (__LINE__, 4, 335); + check_gpr (__LINE__, 5, 10000000000LL); + check_gpr (__LINE__, 6, 20000000000LL); + } + + { + struct sfl sfl_loc_n = { 4.145f, 335 }; + clearall; + f_sfl (sfl_loc_n); + check_gpr_float_pair (__LINE__, 3, 4.145f, 0.0f); + check_gpr (__LINE__, 4, 335); + check_gpr (__LINE__, 5, 0x555); + clearall; + f_sfl_sfl_sfl_sfl_sfl (sfl_loc_n, sfl_loc_n, sfl_loc_n, sfl_loc_n, sfl_loc_n); + check_gpr_float_pair (__LINE__, 3, 4.145f, 0.0f); + check_gpr (__LINE__, 4, 335); + check_gpr (__LINE__, 6, 335); + check_gpr (__LINE__, 8, 335); + check_gpr (__LINE__, 10, 335); + } + + { + struct sfldl sfldl_loc_n = { 4.145f, 335, 3.3, 336 }; + clearall; + f_sfldl (sfldl_loc_n); + check_fpr (__LINE__, 1, 4.145f); + check_gpr (__LINE__, 4, 335); + check_fpr (__LINE__, 2, 3.3); + check_gpr (__LINE__, 6, 336); + } + + { + char *p1 = "abc"; + char *p2 = "def"; + char *p3 = "ghi"; + struct sfpp sfpp_loc_n = { 4.145f, p1, p2 }; + clearall; + f_sfpp_p(sfpp_loc_n, p3); + check_fpr (__LINE__, 1, 4.145f); + check_gpr (__LINE__, 4, (long) p1); + check_gpr (__LINE__, 5, (long) p2); + check_gpr (__LINE__, 6, (long) p3); + } + + { + struct sff sff_loc_n = { 4.145f, 335.3f }; + clearall; + fi_sff(29, sff_loc_n); + check_gpr (__LINE__, 3, 29); +#ifdef STRUCT8INT + check_gpr_float_pair (__LINE__, 4, 4.145f, 335.3f); +#else + check_fpr (__LINE__, 1, 4.145f); + check_fpr (__LINE__, 2, 335.3f); +#endif + } + + { + struct sfD sfD_loc_n = { 4.145f, 335.335 }; + clearall; + f_sfD_sfD_sfD_sfD_sfD (sfD_loc_n, sfD_loc_n, sfD_loc_n, sfD_loc_n, sfD_loc_n); + check_fpr (__LINE__, 1, 4.145f); + check_fpr (__LINE__, 2, 335.335); + check_fpr (__LINE__, 4, 4.145f); + check_fpr (__LINE__, 5, 335.335); + check_fpr (__LINE__, 7, 4.145f); + check_fpr (__LINE__, 10, 4.145f); + check_fpr (__LINE__, 13, 4.145f); + } + + { + struct sidi sidi_loc_n = { 257, 4.14515, 258 }; + clearall; + fi_sidi(16, sidi_loc_n); + check_gpr (__LINE__, 3, 16); + check_fpr (__LINE__, 1, 4.14515); + check_gpr (__LINE__, 4, 257LL << 32); + check_gpr (__LINE__, 5, 0x555); + check_gpr (__LINE__, 6, 258LL << 32); + } + + sfi_loc.f = 5.2f; + sfi_loc.i = 98; + clearall; + fifvf_sfi_dots(41, 4.3f, vf_loc, sfi_loc, 4.63f, vi_loc, sfi_loc2); + __asm__ ("\n"); + check_gpr (__LINE__, 3, 41); + check_fpr (__LINE__, 1, 4.3f); /* float skips r4 */ + check_vr_float(2, 7.1f, 7.2f, 7.3f, 7.4f); /* vector skips r5/r6 */ +#ifdef STRUCT8INT + check_gpr (__LINE__, 7, 0x40a6666600000062); +#else + check_fpr (__LINE__, 2, sfi_loc.f); + check_gpr (__LINE__, 7, sfi_loc.i); +#endif + /* start of varying parameters */ +#ifdef STRUCT8INT + check_fpr (__LINE__, 2, 4.63f); +#else + check_fpr (__LINE__, 3, 4.63f); +#endif + check_gpr_double (__LINE__, 8, 4.63f); + /* vector takes up r9/r10 */ + /* sfi_loc2 on stack */ + + clearall; + sfii_loc.f = 5.2f; + sfii_loc.i = 98; + sfii_loc.j = 777; + clearall; + fifvf_sfii_dots(41, 4.3f, vf_loc, sfii_loc, 4.63f, vi_loc, sfii_loc2); + __asm__ ("\n"); + check_gpr (__LINE__, 3, 41); + check_fpr (__LINE__, 1, 4.3f); /* float skips r4 */ + check_vr_float(2, 7.1f, 7.2f, 7.3f, 7.4f); /* vector skips r5/r6 */ + check_fpr (__LINE__, 2, sfii_loc.f); + check_gpr (__LINE__, 7, sfii_loc.i); + check_gpr (__LINE__, 8, ((long)sfii_loc.j) << 32); + /* start of varying parameters */ + check_fpr (__LINE__, 3, 4.63f); + check_gpr_double (__LINE__, 9, 4.63f); + /* vector takes up r10/stack (?) */ + /* sfii_loc2 on stack */ + + if (numerrs > 0) + abort (); + return 0; +} + +int dumpall() +{ + int i; + + printf("\n"); + for (i = 3; i <= 10; ++i) +#ifdef __LP64__ + printf("r%d=0x%16.16lx ", i, gparms.gprs[i]); +#else + printf("r%d=0x%8.8x ", i, gparms.gprs[i]); +#endif + printf("\n"); + for (i = 1; i <= 13; ++i) + printf("f%d=%8.8f ", i, gparms.fprs[i]); + printf("\n"); + for (i = 0; i <= 4; ++i) + printf("v%d=(%x,%x,%x,%x) ", i, + gparms.vrs[i].elts.ielts[0], gparms.vrs[i].elts.ielts[1], + gparms.vrs[i].elts.ielts[2], gparms.vrs[i].elts.ielts[3]); + printf("\n"); + for (i = 112; i < 152; ++i) + { + if (i > 112 && i % 8 == 0) + printf(" | "); + printf("%02x", gparms.stack[i]); + } + printf("\n"); +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp-dd.c b/gcc/testsuite/gcc.target/powerpc/dfp-dd.c new file mode 100644 index 000000000..85da90705 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp-dd.c @@ -0,0 +1,33 @@ +/* Test generation of DFP instructions for POWER6. */ +/* Origin: Janis Johnson <janis187@us.ibm.com> */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -mcpu=power6" } */ + +/* { dg-final { scan-assembler "dadd" } } */ +/* { dg-final { scan-assembler "ddiv" } } */ +/* { dg-final { scan-assembler "dmul" } } */ +/* { dg-final { scan-assembler "dsub" } } */ +/* { dg-final { scan-assembler-times "dcmpu" 6 } } */ +/* { dg-final { scan-assembler-times "dctfix" 2 } } */ +/* { dg-final { scan-assembler-times "drintn" 2 } } */ +/* { dg-final { scan-assembler-times "dcffixq" 2 } } */ + +extern _Decimal64 a, b, c; +extern int result; +extern int si; +extern long long di; + +void add (void) { a = b + c; } +void div (void) { a = b / c; } +void mul (void) { a = b * c; } +void sub (void) { a = b - c; } +void eq (void) { result = a == b; } +void ne (void) { result = a != b; } +void lt (void) { result = a < b; } +void le (void) { result = a <= b; } +void gt (void) { result = a > b; } +void ge (void) { result = a >= b; } +void ddsi (void) { si = a; } +void dddi (void) { di = a; } +void sidd (void) { a = si; } +void didd (void) { a = di; } diff --git a/gcc/testsuite/gcc.target/powerpc/dfp-td.c b/gcc/testsuite/gcc.target/powerpc/dfp-td.c new file mode 100644 index 000000000..752ba8874 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp-td.c @@ -0,0 +1,33 @@ +/* Test generation of DFP instructions for POWER6. */ +/* Origin: Janis Johnson <janis187@us.ibm.com> */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -mcpu=power6" } */ + +/* { dg-final { scan-assembler "daddq" } } */ +/* { dg-final { scan-assembler "ddivq" } } */ +/* { dg-final { scan-assembler "dmulq" } } */ +/* { dg-final { scan-assembler "dsubq" } } */ +/* { dg-final { scan-assembler-times "dcmpuq" 6 } } */ +/* { dg-final { scan-assembler-times "dctfixq" 2 } } */ +/* { dg-final { scan-assembler-times "drintnq" 2 } } */ +/* { dg-final { scan-assembler-times "dcffixq" 2 } } */ + +extern _Decimal128 a, b, c; +extern int result; +extern int si; +extern long long di; + +void add (void) { a = b + c; } +void div (void) { a = b / c; } +void mul (void) { a = b * c; } +void sub (void) { a = b - c; } +void eq (void) { result = a == b; } +void ne (void) { result = a != b; } +void lt (void) { result = a < b; } +void le (void) { result = a <= b; } +void gt (void) { result = a > b; } +void ge (void) { result = a >= b; } +void tdsi (void) { si = a; } +void tddi (void) { di = a; } +void sitd (void) { a = si; } +void ditd (void) { a = di; } diff --git a/gcc/testsuite/gcc.target/powerpc/doloop-1.c b/gcc/testsuite/gcc.target/powerpc/doloop-1.c new file mode 100644 index 000000000..d4bc45415 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/doloop-1.c @@ -0,0 +1,17 @@ +/* Make sure both loops are recognized as doloops. + If so, "bdnz" will be generated on ppc; if not, + you will get "ble" or "blt" or "bge". */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +void foo (int count, char* pca, char* pcb) { + int i; + if (count > 10) + for (i = 0; i < count; ++i) + pcb += i; + else + for (i = 0; i < count; ++i) + pca += i; + *pca = *pcb; +} +/* { dg-final { scan-assembler "bdnz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/e500-1.c b/gcc/testsuite/gcc.target/powerpc/e500-1.c new file mode 100644 index 000000000..76a0e4a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/e500-1.c @@ -0,0 +1,14 @@ +/* Test functioning of command option -mno-isel */ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-O2 -mno-isel" } */ + +/* { dg-final { scan-assembler-not "isel" } } */ + +int +foo (int x, int y) +{ + if (x < y) + return x; + else + return y; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ehreturn.c b/gcc/testsuite/gcc.target/powerpc/ehreturn.c new file mode 100644 index 000000000..abada8300 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ehreturn.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mminimal-toc -mno-multiple" } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ + +void foo () +{ + long l; void *p; + volatile int x; + + __builtin_unwind_init (); + x = 12; + __builtin_eh_return (l, p); +} + +/* { dg-final { scan-assembler "st\[wd\] 30," } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/gcse-1.c b/gcc/testsuite/gcc.target/powerpc/gcse-1.c new file mode 100644 index 000000000..799cde1dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/gcse-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { *-*-linux* && ilp32 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "@ha" 1 } } */ + + +/* Test for PR 7003, address of array loaded int register + twice without any need. */ + +extern const char flags [256]; + +unsigned char * f (unsigned char * s) { + while (flags[*++s]); + while (!flags[*++s]); + return s; +} diff --git a/gcc/testsuite/gcc.target/powerpc/indexed-addr.c b/gcc/testsuite/gcc.target/powerpc/indexed-addr.c new file mode 100644 index 000000000..6933b23e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/indexed-addr.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler "3,\.*3,\.*4" } } + +/* Ensure that indexed address are output with base address in rA position + and index in rB position. */ + +char +do_one (char *base, unsigned long offset) +{ + return base[offset]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/leaf.c b/gcc/testsuite/gcc.target/powerpc/leaf.c new file mode 100644 index 000000000..079418930 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/leaf.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target rs6000-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "\tstwu 1,-\[0-9\]*(1)\n" } } */ + +int Leaf (int i) +{ + return i + 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/longcall-1.c b/gcc/testsuite/gcc.target/powerpc/longcall-1.c new file mode 100644 index 000000000..e7187f17a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/longcall-1.c @@ -0,0 +1,13 @@ +/* PR target/35100 */ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-fpic" } */ + +void foo (void) __attribute__((__longcall__)); +int baz (void) __attribute__((__longcall__)); + +int +bar (void) +{ + foo (); + return baz () + 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/loop_align.c b/gcc/testsuite/gcc.target/powerpc/loop_align.c new file mode 100644 index 000000000..489380f2f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/loop_align.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7 -falign-functions=16" } */ +/* { dg-final { scan-assembler ".p2align 5,,31" } } */ + +void f(double *a, double *b, double *c, int n) { + int i; + for (i=0; i < n; i++) + a[i] = b[i] + c[i]; +} diff --git a/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c b/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c new file mode 100644 index 000000000..9e0b8656c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mpowerpc64 -mdynamic-no-pic" } */ + +long long knight_attacks[64]; +long long InitializeAttackBoards(void); + +int main() +{ + return InitializeAttackBoards(); +} + +long long InitializeAttackBoards(void) +{ + + int i,j; + + for(i=0;i<64;i++) { } + + for(i=0;i<64;i++) { + knight_attacks[i]=0; + for(j=0;j<8;j++) { + knight_attacks[i]= 0; + } + } + + return knight_attacks[0]; + +} + diff --git a/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c b/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c new file mode 100644 index 000000000..10cce470a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target powerpc*-apple-darwin* } } */ +/* { dg-options "-S" } */ + +typedef void PF (void); + +static void f(void) { +} + +void f1(void) { +} + +extern void f2(void) { +} + +static void f3(void); + +void pe(void) +{ +} + +PF* g (void) { f(); return f; } +PF* x (void) { return f1; } +PF* y (void) { f2(); return f2; } +PF* z (void) { return f3; } +PF* w (void) { pe(); return pe; } + +int main() +{ + (*g())(); + (*x())(); + (*y())(); + (*z())(); + (*w())(); + return 0; +} + +void f3(void) { +} + +/* { dg-final { scan-assembler-not "non_lazy_ptr" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c b/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c new file mode 100644 index 000000000..7337e99b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c @@ -0,0 +1,36 @@ +/* { dg-require-effective-target stdint_types } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=power5" } */ + +/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores + to test whether lwbrx/stwbrx is generated for normal power systems. */ + +#include <stdint.h> +#define __const_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + + +/* This byte swap implementation is used by the Linux kernel and the + GNU C library. */ + +uint64_t +swap64_load (uint64_t *in) +{ + return __const_swab64 (*in); +} + +void +swap64_store (uint64_t *out, uint64_t in) +{ + *out = __const_swab64 (in); +} + +/* { dg-final { scan-assembler-times "lwbrx" 2 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c b/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c new file mode 100644 index 000000000..9dcd824c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c @@ -0,0 +1,36 @@ +/* { dg-require-effective-target stdint_types } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores + to test whether ldbrx/stdbrx is generated for power7. */ + +#include <stdint.h> +#define __const_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + + +/* This byte swap implementation is used by the Linux kernel and the + GNU C library. */ + +uint64_t +swap64_load (uint64_t *in) +{ + return __const_swab64 (*in); +} + +void +swap64_store (uint64_t *out, uint64_t in) +{ + *out = __const_swab64 (in); +} + +/* { dg-final { scan-assembler "ldbrx" } } */ +/* { dg-final { scan-assembler "stdbrx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c b/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c new file mode 100644 index 000000000..34cc8236f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c @@ -0,0 +1,55 @@ +/* { dg-require-effective-target stdint_types } */ +/* { dg-options "-O2 -mcpu=power5" } */ + +#include <stdint.h> + +/* This is a clone of gcc-dg/optimize-bswapsi-1.c, redone to use load and stores + to test whether lwbrx/stwbrx is generated for normal power systems. */ + +#define __const_swab32(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +/* This byte swap implementation is used by the Linux kernel and the + GNU C library. */ + +uint32_t +swap32_a_load (uint32_t *in) +{ + return __const_swab32 (*in); +} + +/* The OpenSSH byte swap implementation. */ +uint32_t +swap32_b_load (uint32_t *in) +{ + uint32_t a; + + a = (*in << 16) | (*in >> 16); + a = ((a & 0x00ff00ff) << 8) | ((a & 0xff00ff00) >> 8); + + return a; +} + +void +swap32_a_store (uint32_t *out, uint32_t in) +{ + *out = __const_swab32 (in); +} + +/* The OpenSSH byte swap implementation. */ +void +swap32_b_store (uint32_t *out, uint32_t in) +{ + uint32_t a; + + a = (in << 16) | (in >> 16); + a = ((a & 0x00ff00ff) << 8) | ((a & 0xff00ff00) >> 8); + + *out = a; +} + +/* { dg-final { scan-assembler-times "lwbrx" 2 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c b/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c new file mode 100644 index 000000000..a80a46f40 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c @@ -0,0 +1,15 @@ +/* Test that registers used by out of line restore functions does not get renamed. + AIX, and 64 bit targets uses r1, which rnreg stays away from. + Linux 32 bits targets uses r11, which is susceptible to be renamed */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Os -frename-registers -fdump-rtl-rnreg" } */ +/* "* renamed" or "* no available better choice" results are not acceptable */ +/* { dg-final { scan-rtl-dump-not "Register 11 in insn *" "rnreg" { target powerpc*-*-linux* } } } */ +/* { dg-final { cleanup-rtl-dump "rnreg" } } */ +int +calc (int j) +{ + if (j<=1) return 1; + return calc(j-1)*(j+1); +} diff --git a/gcc/testsuite/gcc.target/powerpc/paired-1.c b/gcc/testsuite/gcc.target/powerpc/paired-1.c new file mode 100644 index 000000000..19a66a15b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-1.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32} } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> + +static float in1[2] __attribute__ ((aligned (8))) = +{6.0, 7.0}; +static float in2[2] __attribute__ ((aligned (8))) = +{4.0, 3.0}; + +static float out[2] __attribute__ ((aligned (8))); + +vector float a, b, c, d; +void +test_api () +{ + b = paired_lx (0, in1); + c = paired_lx (0, in2); + + a = paired_sub (b, c); + + paired_stx (a, 0, out); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-10.c b/gcc/testsuite/gcc.target/powerpc/paired-10.c new file mode 100644 index 000000000..1f904c258 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-10.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> + +static float out[2] __attribute__ ((aligned (8))); +void +test_api (float y, float x) +{ + vector float c = {x, y}; + vector float b = {0.0, 8.0}; + vector float a; + + a = paired_sub (b, c); + paired_stx (a, 0, out); +} + + +int main () +{ + test_api (6, 7); + return (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/paired-2.c b/gcc/testsuite/gcc.target/powerpc/paired-2.c new file mode 100644 index 000000000..181bbf1c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 3.0, 8.0 }; +vector float c = { 3.0, 5.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu0_eq (b, c)) + { + a = paired_sub (b, c); + paired_stx (a, 0, out); + } + + if ((out[1]) != 3.0) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-3.c b/gcc/testsuite/gcc.target/powerpc/paired-3.c new file mode 100644 index 000000000..2e4bbf4af --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 2.0, 8.0 }; +vector float c = { 3.0, 5.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu0_lt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 13.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-4.c b/gcc/testsuite/gcc.target/powerpc/paired-4.c new file mode 100644 index 000000000..2c7cb1b67 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-4.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 3.0, 8.0 }; +vector float c = { 2.0, 5.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu0_gt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 13.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-5.c b/gcc/testsuite/gcc.target/powerpc/paired-5.c new file mode 100644 index 000000000..3914c2a6f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-5.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 3.0, 5.0 }; +vector float c = { 2.0, 5.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu1_eq (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 10.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-6.c b/gcc/testsuite/gcc.target/powerpc/paired-6.c new file mode 100644 index 000000000..25dd42835 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-6.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 3.0, 5.0 }; +vector float c = { 2.0, 6.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu1_lt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 11.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-7.c b/gcc/testsuite/gcc.target/powerpc/paired-7.c new file mode 100644 index 000000000..6e4b80917 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-7.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> +#include <stdlib.h> + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 2.0, 8.0 }; +vector float c = { 3.0, 6.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu1_gt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 14.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/paired-8.c b/gcc/testsuite/gcc.target/powerpc/paired-8.c new file mode 100644 index 000000000..1dfaf5187 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-8.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> + +static float out[2] __attribute__ ((aligned (8))); +void +test_api (float x) +{ + vector float c = {x, x}; + vector float b = {60.0, 88.0}; + vector float a; + + a = paired_sub (b, c); + paired_stx (a, 0, out); +} + + +int main () +{ + test_api (6); + return (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/paired-9.c b/gcc/testsuite/gcc.target/powerpc/paired-9.c new file mode 100644 index 000000000..c72132fec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/paired-9.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> + +static float out[2] __attribute__ ((aligned (8))); +void +test_api (float y, float x) +{ + vector float c = {x, 7.0}; + vector float b = {0.0, 8.0}; + vector float a; + + a = paired_sub (b, c); + paired_stx (a, 0, out); +} + + +int main () +{ + test_api (6, 7); + return (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/parity-1.c b/gcc/testsuite/gcc.target/powerpc/parity-1.c new file mode 100644 index 000000000..c991d4caa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/parity-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5" } */ +/* { dg-final { scan-assembler "popcntb" } } */ +/* { dg-final { scan-assembler-not "mullw" } } */ + +int foo(int x) +{ + return __builtin_parity(x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-1.c b/gcc/testsuite/gcc.target/powerpc/popcount-1.c new file mode 100644 index 000000000..c94d155e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/popcount-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5" } */ +/* { dg-final { scan-assembler "popcntb" } } */ +/* { dg-final { scan-assembler-not "mullw" } } */ + +int foo(int x) +{ + return __builtin_popcount(x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-2.c b/gcc/testsuite/gcc.target/powerpc/popcount-2.c new file mode 100644 index 000000000..43b2ce7fa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/popcount-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "popcntw" } } */ + +int foo(int x) +{ + return __builtin_popcount(x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-3.c b/gcc/testsuite/gcc.target/powerpc/popcount-3.c new file mode 100644 index 000000000..341816f9f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/popcount-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "popcntd" } } */ + +long foo(int x) +{ + return __builtin_popcountl(x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/powerpc.exp b/gcc/testsuite/gcc.target/powerpc/powerpc.exp new file mode 100644 index 000000000..bb97e1e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/powerpc.exp @@ -0,0 +1,41 @@ +# Copyright (C) 2005, 2007 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the 'dg.exp' driver. + +# Exit immediately if this isn't a PowerPC target. +if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize 'dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c new file mode 100644 index 000000000..3d4237ce9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,0,30" } } */ +/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,29,30" } } */ +/* { dg-final { scan-assembler-not "rldicr" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16457 - use rlwinm insn. */ + +char *foo1 (char *p, unsigned int x) +{ + return p - (x & ~1); +} + +char *foo2 (char *p, unsigned int x) +{ + return p - (x & 6); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c b/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c new file mode 100644 index 000000000..34e5a28e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c @@ -0,0 +1,67 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31" } } */ +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 17104 many sign extends added. */ + +struct { + int f1 : 1; + int f2 : 1; + int f3 : 1; + int f4 : 1; + int f5 : 1; + int f6 : 1; + int f7 : 1; + int f8 : 1; + int f9 : 1; + int f10 : 1; + int f11 : 1; + int f12 : 1; + int f13 : 1; + int f14 : 1; + int f15 : 1; + int f16 : 1; + int f17 : 2; + int f18 : 2; + int f19 : 2; + int f20 : 2; + int f21 : 2; + int f22 : 2; + int f23 : 2; + int f24 : 2; + } s; + +void foo () +{ + + s.f1 = 0; + s.f2 = 0; + s.f3 = 0; + s.f4 = 0; + s.f5 = 0; + s.f6 = 0; + s.f7 = 0; + s.f8 = 0; + s.f9 = 0; + s.f10 = 0; + s.f11 = 0; + s.f12 = 0; + s.f13 = 0; + s.f14 = 0; + s.f15 = 0; + s.f16 = 0; + s.f17 = 0; + s.f18 = 0; + s.f19 = 0; + s.f20 = 0; + s.f21 = 0; + s.f22 = 0; + s.f23 = 0; + s.f24 = 0; + +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c new file mode 100644 index 000000000..2566423a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "cmpw" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16458: Extraneous compare. */ + +int foo (unsigned a, unsigned b) +{ + if (a == b) return 1; + if (a > b) return 2; + if (a < b) return 3; + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c b/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c new file mode 100644 index 000000000..47ba1a733 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c @@ -0,0 +1,4 @@ +/* PR target/16952 */ +/* { dg-do compile { target { powerpc*-*-linux* && ilp32 } } } */ +/* { dg-options "-meabi -mrelocatable" } */ +char *s = "boo"; diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c new file mode 100644 index 000000000..496a6e340 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c @@ -0,0 +1,10 @@ +/* PR rtl-optimization/10588 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x) +{ + return x == 0; +} + +/* { dg-final { scan-assembler "cntlzw|isel" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c new file mode 100644 index 000000000..674115a28 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c @@ -0,0 +1,183 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times "xvmadd" 4 } } */ +/* { dg-final { scan-assembler-times "xsmadd" 2 } } */ +/* { dg-final { scan-assembler-times "fmadds" 2 } } */ +/* { dg-final { scan-assembler-times "xvmsub" 2 } } */ +/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ +/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ +/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ +/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ + +/* All functions should generate an appropriate (a * b) + c instruction + since -mfused-madd is on by default. */ + +double +builtin_fma (double b, double c, double d) +{ + return __builtin_fma (b, c, d); /* xsmadd{a,m}dp */ +} + +double +builtin_fms (double b, double c, double d) +{ + return __builtin_fma (b, c, -d); /* xsmsub{a,b}dp */ +} + +double +builtin_fnma (double b, double c, double d) +{ + return - __builtin_fma (b, c, d); /* xsnmadd{a,b}dp */ +} + +double +builtin_fnms (double b, double c, double d) +{ + return - __builtin_fma (b, c, -d); /* xsnmsub{a,b}dp */ +} + +float +builtin_fmaf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, d); /* fmadds */ +} + +float +builtin_fmsf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, -d); /* fmsubs */ +} + +float +builtin_fnmaf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, d); /* fnmadds */ +} + +float +builtin_fnmsf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, -d); /* fnmsubs */ +} + +double +normal_fma (double b, double c, double d) +{ + return (b * c) + d; /* xsmadd{a,m}dp */ +} + +float +normal_fmaf (float b, float c, float d) +{ + return (b * c) + d; /* fmadds */ +} + +#ifndef SIZE +#define SIZE 1024 +#endif + +double vda[SIZE] __attribute__((__aligned__(32))); +double vdb[SIZE] __attribute__((__aligned__(32))); +double vdc[SIZE] __attribute__((__aligned__(32))); +double vdd[SIZE] __attribute__((__aligned__(32))); + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvmadd{a,m}dp */ +} + +void +vector_fms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvmsub{a,m}dp */ +} + +void +vector_fnma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvnmadd{a,m}dp */ +} + +void +vector_fnms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvnmsub{a,m}dp */ +} + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvmadd{a,m}sp */ +} + +void +vector_fmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvmsub{a,m}sp */ +} + +void +vector_fnmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvnmadd{a,m}sp */ +} + +void +vector_fnmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */ +} + +void +vnormal_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = (vdb[i] * vdc[i]) + vdd[i]; /* xvmadd{a,m}dp */ +} + +void +vnormal_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* xvmadd{a,m}sp */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c new file mode 100644 index 000000000..111b9cb09 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c @@ -0,0 +1,183 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -ffp-contract=off" } */ +/* { dg-final { scan-assembler-times "xvmadd" 2 } } */ +/* { dg-final { scan-assembler-times "xsmadd" 1 } } */ +/* { dg-final { scan-assembler-times "fmadds" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsub" 2 } } */ +/* { dg-final { scan-assembler-times "xsmsub" 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */ +/* { dg-final { scan-assembler-times "xsnmadd" 1 } } */ +/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */ +/* { dg-final { scan-assembler-times "xsnmsub" 1 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ + +/* Only the functions calling the bulitin should generate an appropriate (a * + b) + c instruction. */ + +double +builtin_fma (double b, double c, double d) +{ + return __builtin_fma (b, c, d); /* xsmadd{a,m}dp */ +} + +double +builtin_fms (double b, double c, double d) +{ + return __builtin_fma (b, c, -d); /* xsmsub{a,b}dp */ +} + +double +builtin_fnma (double b, double c, double d) +{ + return - __builtin_fma (b, c, d); /* xsnmadd{a,b}dp */ +} + +double +builtin_fnms (double b, double c, double d) +{ + return - __builtin_fma (b, c, -d); /* xsnmsub{a,b}dp */ +} + +float +builtin_fmaf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, d); /* fmadds */ +} + +float +builtin_fmsf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, -d); /* fmsubs */ +} + +float +builtin_fnmaf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, d); /* fnmadds */ +} + +float +builtin_fnmsf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, -d); /* fnmsubs */ +} + +double +normal_fma (double b, double c, double d) +{ + return (b * c) + d; /* fmul/fadd */ +} + +float +normal_fmaf (float b, float c, float d) +{ + return (b * c) + d; /* fmuls/fadds */ +} + +#ifndef SIZE +#define SIZE 1024 +#endif + +double vda[SIZE] __attribute__((__aligned__(32))); +double vdb[SIZE] __attribute__((__aligned__(32))); +double vdc[SIZE] __attribute__((__aligned__(32))); +double vdd[SIZE] __attribute__((__aligned__(32))); + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvmadd{a,m}dp */ +} + +void +vector_fms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvmsub{a,m}dp */ +} + +void +vector_fnma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]); /* xvnmadd{a,m}dp */ +} + +void +vector_fnms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]); /* xvnmsub{a,m}dp */ +} + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvmadd{a,m}sp */ +} + +void +vector_fmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvmsub{a,m}sp */ +} + +void +vector_fnmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* xvnmadd{a,m}sp */ +} + +void +vector_fnmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */ +} + +void +vnormal_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = (vdb[i] * vdc[i]) + vdd[i]; /* xvmadd{a,m}dp */ +} + +void +vnormal_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* xvmadd{a,m}sp */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c new file mode 100644 index 000000000..c83c58298 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c @@ -0,0 +1,103 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math" } */ +/* { dg-final { scan-assembler-times "vmaddfp" 2 } } */ +/* { dg-final { scan-assembler-times "fmadd " 2 } } */ +/* { dg-final { scan-assembler-times "fmadds" 2 } } */ +/* { dg-final { scan-assembler-times "fmsub " 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "fnmadd " 1 } } */ +/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ +/* { dg-final { scan-assembler-times "fnmsub " 1 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ + +/* All functions should generate an appropriate (a * b) + c instruction + since -mfused-madd is on by default. */ + +double +builtin_fma (double b, double c, double d) +{ + return __builtin_fma (b, c, d); /* fmadd */ +} + +double +builtin_fms (double b, double c, double d) +{ + return __builtin_fma (b, c, -d); /* fmsub */ +} + +double +builtin_fnma (double b, double c, double d) +{ + return - __builtin_fma (b, c, d); /* fnmadd */ +} + +double +builtin_fnms (double b, double c, double d) +{ + return - __builtin_fma (b, c, -d); /* fnmsub */ +} + +float +builtin_fmaf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, d); /* fmadds */ +} + +float +builtin_fmsf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, -d); /* fmsubs */ +} + +float +builtin_fnmaf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, d); /* fnmadds */ +} + +float +builtin_fnmsf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, -d); /* fnmsubs */ +} + +double +normal_fma (double b, double c, double d) +{ + return (b * c) + d; /* fmadd */ +} + +float +normal_fmaf (float b, float c, float d) +{ + return (b * c) + d; /* fmadds */ +} + +#ifndef SIZE +#define SIZE 1024 +#endif + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* vaddfp */ +} + +void +vnormal_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = (vfb[i] * vfc[i]) + vfd[i]; /* vaddfp */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c new file mode 100644 index 000000000..44da6e76b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c @@ -0,0 +1,94 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math -ffp-contract=off" } */ +/* { dg-final { scan-assembler-times "vmaddfp" 1 } } */ +/* { dg-final { scan-assembler-times "fmadd " 1 } } */ +/* { dg-final { scan-assembler-times "fmadds" 1 } } */ +/* { dg-final { scan-assembler-times "fmsub " 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "fnmadd " 1 } } */ +/* { dg-final { scan-assembler-times "fnmadds" 1 } } */ +/* { dg-final { scan-assembler-times "fnmsub " 1 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */ + +/* Only the functions calling the builtin should generate an appropriate + (a * b) + c instruction. */ + +double +builtin_fma (double b, double c, double d) +{ + return __builtin_fma (b, c, d); /* fmadd */ +} + +double +builtin_fms (double b, double c, double d) +{ + return __builtin_fma (b, c, -d); /* fmsub */ +} + +double +builtin_fnma (double b, double c, double d) +{ + return - __builtin_fma (b, c, d); /* fnmadd */ +} + +double +builtin_fnms (double b, double c, double d) +{ + return - __builtin_fma (b, c, -d); /* fnmsub */ +} + +float +builtin_fmaf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, d); /* fmadds */ +} + +float +builtin_fmsf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, -d); /* fmsubs */ +} + +float +builtin_fnmaf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, d); /* fnmadds */ +} + +float +builtin_fnmsf (float b, float c, float d) +{ + return - __builtin_fmaf (b, c, -d); /* fnmsubs */ +} + +double +normal_fma (double b, double c, double d) +{ + return (b * c) + d; /* fmul/fadd */ +} + +float +normal_fmaf (float b, float c, float d) +{ + return (b * c) + d; /* fmuls/fadds */ +} + +#ifndef SIZE +#define SIZE 1024 +#endif + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); /* vaddfp */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c new file mode 100644 index 000000000..97243afb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5 -std=c99" } */ + +#ifndef __FP_FAST_FMA +#error "__FP_FAST_FMA should be defined" +#endif + +#ifndef __FP_FAST_FMAF +#error "__FP_FAST_FMAF should be defined" +#endif + +double d_a = 2.0, d_b = 3.0, d_c = 4.0; +float f_a = 2.0f, f_b = 3.0f, f_c = 4.0f; + +int +main (void) +{ + if (__builtin_fma (d_a, d_b, d_c) != (2.0 * 3.0) + 4.0) + __builtin_abort (); + + if (__builtin_fmaf (f_a, f_b, f_c) != (2.0f * 3.0f) + 4.0f) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c new file mode 100644 index 000000000..c9132bbf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=power5 -std=c99 -msoft-float" } */ +/* { dg-final { scan-assembler-not "fmadd" } } */ +/* { dg-final { scan-assembler-not "xsfmadd" } } */ + +/* Test whether -msoft-float turns off the macros math.h uses for + FP_FAST_FMA{,F,L}. */ +#ifdef __FP_FAST_FMA +#error "__FP_FAST_FMA should not be defined" +#endif + +#ifdef __FP_FAST_FMAF +#error "__FP_FAST_FMAF should not be defined" +#endif + +double +builtin_fma (double b, double c, double d) +{ + return __builtin_fma (b, c, d); /* bl fma */ +} + +float +builtin_fmaf (float b, float c, float d) +{ + return __builtin_fmaf (b, c, -d); /* bl fmaf */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c new file mode 100644 index 000000000..ec0c3d740 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -ffast-math" } */ +/* { dg-final { scan-assembler-times "fmadd" 1 } } */ +/* { dg-final { scan-assembler-times "fmsub " 1 } } */ +/* { dg-final { scan-assembler-not "fmul" } } */ +/* { dg-final { scan-assembler-not "fadd " } } */ + +/* Check whether the common FFT idiom (a*b)+c and (a*b)-c generates two fma + instructions, instead of a multiply, add, and subtract. */ + +void +fft (double *result, double a, double b, double c) +{ + result[0] = (a*b) + c; + result[1] = (a*b) - c; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c new file mode 100644 index 000000000..ff959f2d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-ffast-math -O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[1] = b[1] - c[1] * d[1]; // fnmsub with fast-math + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[3] = -b[3] - c[3] * d[3]; // fnmadd with fast-math + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[5] = -( b[5] - c[5] * d[5]); // fmsub with fast-math + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[7] = -(-b[7] - c[7] * d[7]); // fmadd with fast-math + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[11] = b[11] + c[11] * -d[11]; // fnmsub with fast-math + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[13] = -b[13] + c[13] * -d[13]; // fnmadd with fast-math + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[15] = -( b[15] + c[15] * -d[15]); // fmsub with fast-math + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub + a[17] = -(-b[17] + c[17] * -d[17]); // fmadd with fast-math +} + +void foos(float *a, float *b, float *c, float *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[1] = b[1] - c[1] * d[1]; // fnmsub with fast-math + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[3] = -b[3] - c[3] * d[3]; // fnmadd with fast-math + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[5] = -( b[5] - c[5] * d[5]); // fmsub with fast-math + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[7] = -(-b[7] - c[7] * d[7]); // fmadd with fast-math + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[11] = b[11] + c[11] * -d[11]; // fnmsub with fast-math + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[13] = -b[13] + c[13] * -d[13]; // fnmadd with fast-math + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[15] = -( b[15] + c[15] * -d[15]); // fmsub with fast-math + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub + a[17] = -(-b[17] + c[17] * -d[17]); // fmadd with fast-math +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c new file mode 100644 index 000000000..02ed811da --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub +} + +void foos(float *a, float *b, float *c, float *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c new file mode 100644 index 000000000..d4205225c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ +#if 0 + a[1] = b[1] - c[1] * d[1]; // fneg, fmadd without fast-math +#endif + a[3] = -b[3] - c[3] * d[3]; // fneg, fmsub without fast-math +#if 0 + a[5] = -( b[5] - c[5] * d[5]); // fneg, fnmadd without fast-math +#endif + a[7] = -(-b[7] - c[7] * d[7]); // fneg, fnmsub without fast-math + a[11] = b[11] + c[11] * -d[11]; // fneg, fmadd without fast-math + a[13] = -b[13] + c[13] * -d[13]; // fneg, fmsub without fast-math + a[15] = -( b[15] + c[15] * -d[15]); // fneg, fnmadd without fast-math + a[17] = -(-b[17] + c[17] * -d[17]); // fneg, fnmsub without fast-math +} + +void foos(float *a, float *b, float *c, float *d) +{ +#if 0 + a[1] = b[1] - c[1] * d[1]; // fneg, fmadd without fast-math +#endif + a[3] = -b[3] - c[3] * d[3]; // fneg, fmsub without fast-math +#if 0 + a[5] = -( b[5] - c[5] * d[5]); // fneg, fnmadd without fast-math +#endif + a[7] = -(-b[7] - c[7] * d[7]); // fneg, fnmsub without fast-math + a[11] = b[11] + c[11] * -d[11]; // fneg, fmadd without fast-math + a[13] = -b[13] + c[13] * -d[13]; // fneg, fmsub without fast-math + a[15] = -( b[15] + c[15] * -d[15]); // fneg, fnmadd without fast-math + a[17] = -(-b[17] + c[17] * -d[17]); // fneg, fnmsub without fast-math +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c new file mode 100644 index 000000000..8a6cc08b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ +/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ +/* { dg-final { scan-assembler-times "fcfids" 3 } } */ +/* { dg-final { scan-assembler-times "fcfidus" 1 } } */ +/* { dg-final { scan-assembler-times "xscvsxddp" 3 } } */ +/* { dg-final { scan-assembler-times "xscvuxddp" 1 } } */ + +void int_to_float (float *dest, int *src) +{ + *dest = (float) *src; +} + +void int_to_double (double *dest, int *src) +{ + *dest = (double) *src; +} + +void uint_to_float (float *dest, unsigned int *src) +{ + *dest = (float) *src; +} + +void uint_to_double (double *dest, unsigned int *src) +{ + *dest = (double) *src; +} + +void llong_to_float (float *dest, long long *src) +{ + *dest = (float) *src; +} + +void llong_to_double (double *dest, long long *src) +{ + *dest = (double) *src; +} + +void ullong_to_float (float *dest, unsigned long long *src) +{ + *dest = (float) *src; +} + +void ullong_to_double (double *dest, unsigned long long *src) +{ + *dest = (double) *src; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c new file mode 100644 index 000000000..59ba5f91f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xsrdpiz" } } */ +/* { dg-final { scan-assembler-not "friz" } } */ + +double round_double_llong (double a) +{ + return (double)(long long)a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c new file mode 100644 index 000000000..2eebbb42c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */ +/* { dg-final { scan-assembler-not "xsrdpiz" } } */ +/* { dg-final { scan-assembler "friz" } } */ + +double round_double_llong (double a) +{ + return (double)(long long)a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c new file mode 100644 index 000000000..e0a834225 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power6 -ffast-math" } */ +/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ +/* { dg-final { scan-assembler-not "lfiwzx" } } */ +/* { dg-final { scan-assembler-times "fcfid " 10 } } */ +/* { dg-final { scan-assembler-not "fcfids" } } */ +/* { dg-final { scan-assembler-not "fcfidus" } } */ +/* { dg-final { scan-assembler-not "xscvsxddp" } } */ +/* { dg-final { scan-assembler-not "xscvuxddp" } } */ + +void int_to_float (float *dest, int *src) +{ + *dest = (float) *src; +} + +void int_to_double (double *dest, int *src) +{ + *dest = (double) *src; +} + +void uint_to_float (float *dest, unsigned int *src) +{ + *dest = (float) *src; +} + +void uint_to_double (double *dest, unsigned int *src) +{ + *dest = (double) *src; +} + +void llong_to_float (float *dest, long long *src) +{ + *dest = (float) *src; +} + +void llong_to_double (double *dest, long long *src) +{ + *dest = (double) *src; +} + +void ullong_to_float (float *dest, unsigned long long *src) +{ + *dest = (float) *src; +} + +void ullong_to_double (double *dest, unsigned long long *src) +{ + *dest = (double) *src; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c new file mode 100644 index 000000000..6196162a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=power5 -ffast-math" } */ +/* { dg-final { scan-assembler-not "lfiwax" } } */ +/* { dg-final { scan-assembler-not "lfiwzx" } } */ +/* { dg-final { scan-assembler-times "fcfid " 10 } } */ +/* { dg-final { scan-assembler-not "fcfids" } } */ +/* { dg-final { scan-assembler-not "fcfidus" } } */ +/* { dg-final { scan-assembler-not "xscvsxddp" } } */ +/* { dg-final { scan-assembler-not "xscvuxddp" } } */ + +void int_to_float (float *dest, int *src) +{ + *dest = (float) *src; +} + +void int_to_double (double *dest, int *src) +{ + *dest = (double) *src; +} + +void uint_to_float (float *dest, unsigned int *src) +{ + *dest = (float) *src; +} + +void uint_to_double (double *dest, unsigned int *src) +{ + *dest = (double) *src; +} + +void llong_to_float (float *dest, long long *src) +{ + *dest = (float) *src; +} + +void llong_to_double (double *dest, long long *src) +{ + *dest = (double) *src; +} + +void ullong_to_float (float *dest, unsigned long long *src) +{ + *dest = (float) *src; +} + +void ullong_to_double (double *dest, unsigned long long *src) +{ + *dest = (double) *src; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c new file mode 100644 index 000000000..c4b9ea69b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=750 -ffast-math" } */ +/* { dg-final { scan-assembler-not "lfiwax" } } */ +/* { dg-final { scan-assembler-not "lfiwzx" } } */ +/* { dg-final { scan-assembler-not "fcfid " } } */ +/* { dg-final { scan-assembler-not "fcfids" } } */ +/* { dg-final { scan-assembler-not "fcfidus" } } */ +/* { dg-final { scan-assembler-not "xscvsxddp" } } */ +/* { dg-final { scan-assembler-not "xscvuxddp" } } */ + +void int_to_float (float *dest, int *src) +{ + *dest = (float) *src; +} + +void int_to_double (double *dest, int *src) +{ + *dest = (double) *src; +} + +void uint_to_float (float *dest, unsigned int *src) +{ + *dest = (float) *src; +} + +void uint_to_double (double *dest, unsigned int *src) +{ + *dest = (double) *src; +} + +void llong_to_float (float *dest, long long *src) +{ + *dest = (float) *src; +} + +void llong_to_double (double *dest, long long *src) +{ + *dest = (double) *src; +} + +void ullong_to_float (float *dest, unsigned long long *src) +{ + *dest = (float) *src; +} + +void ullong_to_double (double *dest, unsigned long long *src) +{ + *dest = (double) *src; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c new file mode 100644 index 000000000..a071fc122 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ +/* { dg-final { scan-assembler-times "fctiwuz" 2 } } */ +/* { dg-final { scan-assembler-times "fctidz" 1 } } */ +/* { dg-final { scan-assembler-times "fctiduz" 1 } } */ +/* { dg-final { scan-assembler-times "xscvdpsxds" 1 } } */ +/* { dg-final { scan-assembler-times "xscvdpuxds" 1 } } */ + +void float_to_int (int *dest, float src) { *dest = (int) src; } +void double_to_int (int *dest, double src) { *dest = (int) src; } + +void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } +void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } + +void float_to_llong (long long *dest, float src) { *dest = (long long) src; } +void double_to_llong (long long *dest, double src) { *dest = (long long) src; } + +void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } +void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c new file mode 100644 index 000000000..09ee1885a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power6 -ffast-math" } */ +/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ +/* { dg-final { scan-assembler-not "fctiwuz" } } */ +/* { dg-final { scan-assembler-times "fctidz" 8 } } */ +/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ +/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ + +void float_to_int (int *dest, float src) { *dest = (int) src; } +void double_to_int (int *dest, double src) { *dest = (int) src; } + +void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } +void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } + +void float_to_llong (long long *dest, float src) { *dest = (long long) src; } +void double_to_llong (long long *dest, double src) { *dest = (long long) src; } + +void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } +void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c new file mode 100644 index 000000000..007c8644a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O3 -mcpu=power5 -ffast-math" } */ +/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ +/* { dg-final { scan-assembler-not "fctiwuz" } } */ +/* { dg-final { scan-assembler-times "fctidz" 8 } } */ +/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ +/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ + +void float_to_int (int *dest, float src) { *dest = (int) src; } +void double_to_int (int *dest, double src) { *dest = (int) src; } + +void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } +void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } + +void float_to_llong (long long *dest, float src) { *dest = (long long) src; } +void double_to_llong (long long *dest, double src) { *dest = (long long) src; } + +void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } +void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c new file mode 100644 index 000000000..b5410f60e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O3 -mcpu=750 -ffast-math" } */ +/* { dg-final { scan-assembler-times "fctiwz" 6 } } */ +/* { dg-final { scan-assembler-not "fctiwuz" } } */ +/* { dg-final { scan-assembler-not "fctidz" } } */ +/* { dg-final { scan-assembler-not "fctiduz" } } */ +/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ +/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ + +void float_to_int (int *dest, float src) { *dest = (int) src; } +void double_to_int (int *dest, double src) { *dest = (int) src; } + +void float_to_uint (int *dest, float src) { *dest = (unsigned int) src; } +void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; } + +void float_to_llong (long long *dest, float src) { *dest = (long long) src; } +void double_to_llong (long long *dest, double src) { *dest = (long long) src; } + +void float_to_ullong (unsigned long long *dest, float src) { *dest = (unsigned long long) src; } +void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c new file mode 100644 index 000000000..836c030ba --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-not "lwz" } } */ +/* { dg-final { scan-assembler-not "stw" } } */ +/* { dg-final { scan-assembler-not "ld " } } */ +/* { dg-final { scan-assembler-not "std" } } */ + +void float_to_llong (long long *dest, float src) { *dest = (long long) src; } +void double_to_llong (long long *dest, double src) { *dest = (long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c new file mode 100644 index 000000000..8d364352a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt -fno-trapping-math" } */ +/* { dg-final { scan-assembler "fsel" } } */ + +/* If the user doesn't care about signals, fsel can be used in many cases. */ + +double foo(double a, double b, double c, double d) +{ + return a < b ? c : d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c new file mode 100644 index 000000000..9768b165c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c @@ -0,0 +1,80 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt -g0 -ffinite-math-only" } */ +/* { dg-final { scan-assembler-not "^L" } } */ + +/* Every single one of these should be compiled into straight-line + code using fsel (or, in a few cases, hardwired to 'true' or + 'false'), no branches anywhere. */ + +double +test_isunordered(double x, double y, double a, double b) +{ + return __builtin_isunordered(x, y) ? a : b; +} + +double +test_not_isunordered(double x, double y, double a, double b) +{ + return !__builtin_isunordered(x, y) ? a : b; +} + +double +test_isless(double x, double y, double a, double b) +{ + return __builtin_isless(x, y) ? a : b; +} + +double +test_not_isless(double x, double y, double a, double b) +{ + return !__builtin_isless(x, y) ? a : b; +} + +double +test_islessequal(double x, double y, double a, double b) +{ + return __builtin_islessequal(x, y) ? a : b; +} + +double +test_not_islessequal(double x, double y, double a, double b) +{ + return !__builtin_islessequal(x, y) ? a : b; +} + +double +test_isgreater(double x, double y, double a, double b) +{ + return __builtin_isgreater(x, y) ? a : b; +} + +double +test_not_isgreater(double x, double y, double a, double b) +{ + return !__builtin_isgreater(x, y) ? a : b; +} + +double +test_isgreaterequal(double x, double y, double a, double b) +{ + return __builtin_isgreaterequal(x, y) ? a : b; +} + +double +test_not_isgreaterequal(double x, double y, double a, double b) +{ + return !__builtin_isgreaterequal(x, y) ? a : b; +} + +double +test_islessgreater(double x, double y, double a, double b) +{ + return __builtin_islessgreater(x, y) ? a : b; +} + +double +test_not_islessgreater(double x, double y, double a, double b) +{ + return !__builtin_islessgreater(x, y) ? a : b; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c new file mode 100644 index 000000000..1d07c528e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt" } */ +/* { dg-final { scan-assembler-not "fsub" } } */ + +/* Check that an fsub isn't generated when no arithmetic was requested; + such an fsub might incorrectly set floating-point exception flags. */ + +double foo(double a, double b, double c, double d) +{ + return a < b ? c : d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c b/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c new file mode 100644 index 000000000..da6001fcd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c @@ -0,0 +1,21 @@ +/* { dg-do run { target powerpc*-*-eabi* powerpc*-*-elf* powerpc*-*-linux* } } */ +/* { dg-options "-O -mlong-double-128" } */ + +#include <stdlib.h> + +/* SVR4 and EABI both specify that 'long double' is aligned to a 128-bit + boundary in structures. */ + +struct { + int x; + long double d; +} s; + +int main(void) +{ + if (sizeof (s) != 32) + abort (); + if ((char *)&s.d - (char *)&s != 16) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c new file mode 100644 index 000000000..750cf85f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c @@ -0,0 +1,52 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "fmr \[0-9\]+,\[0-9\]+" } } + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16796: Extraneous move. */ + +static const double huge = 1.0e300; +typedef int int64_t __attribute__ ((__mode__ (__DI__))); +typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__))); + +double __floor(double x) +{ + union { + double dbl_val; + long int long_val; + } temp; + + int64_t i0,j0; + u_int64_t i; + temp.dbl_val = x; + i0 = temp.long_val; + + j0 = ((i0>>52)&0x7ff)-0x3ff; + if(j0<52) { + if(j0<0) { + if(huge+x>0.0) { + if(i0>=0) {i0=0;} + else if((i0&0x7fffffffffffffff)!=0) + { i0=0xbff0000000000000;} + } + } else { + i = (0x000fffffffffffff)>>j0; + if((i0&i)==0) return x; + if(huge+x>0.0) { + if(i0<0) i0 += (0x0010000000000000)>>j0; + i0 &= (~i); + } + } + } else { + if (j0==0x400) + return x+x; + else + return x; + } + temp.long_val = i0; + x = temp.dbl_val; + return x; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c new file mode 100644 index 000000000..0386ecba7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long foo(long x) +{ + return -(x == 0); +} + +long bar(long x) +{ + long t = __builtin_clzl(x); + return -(t>>(sizeof(long) == 8 ? 6 : 5)); +} + +/* { dg-final { scan-assembler-not "cntlz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-paired.c b/gcc/testsuite/gcc.target/powerpc/ppc-paired.c new file mode 100644 index 000000000..be84e431c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-paired.c @@ -0,0 +1,45 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include <paired.h> + +vector float a, b, c, d; + +void +test_api () +{ + b = paired_msub (b, c, d); + b = paired_madd (b, c, d); + b = paired_nmadd (b, c, d); + b = paired_nmsub (b, c, d); + b = paired_sum0 (a, b, c); + b = paired_sum1 (a, b, c); + b = paired_div (b, c); + b = paired_add (a, c); + b = paired_sub (a, c); + b = paired_mul (a, c); + b = paired_neg (a); + b = paired_muls0 (a, c); + b = paired_muls1 (a, c); + b = paired_madds0 (a, c, d); + b = paired_madds1 (a, c, d); + b = paired_merge00 (a, c); + b = paired_merge01 (a, c); + b = paired_merge10 (a, c); + b = paired_merge11 (a, c); + b = paired_abs (a); + b = paired_nabs (a); + b = paired_sqrt (a); + b = paired_res (a); + b = paired_sel (a, b, c); +} + +int +main (void) +{ + test_api (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-pow.c b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c new file mode 100644 index 000000000..1255d5c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-options "-O2 -ffast-math -mcpu=power6" } */ +/* { dg-final { scan-assembler-times "fsqrt" 3 } } */ +/* { dg-final { scan-assembler-times "fmul" 1 } } */ +/* { dg-final { scan-assembler-times "bl pow" 1 } } */ +/* { dg-final { scan-assembler-times "bl sqrt" 1 } } */ + +double +do_pow_0_75_default (double a) +{ + return __builtin_pow (a, 0.75); /* should generate 2 fsqrts */ +} + +double +do_pow_0_5_default (double a) +{ + return __builtin_pow (a, 0.5); /* should generate fsqrt */ +} + +#pragma GCC target "no-powerpc-gpopt,no-powerpc-gfxopt" + +double +do_pow_0_75_nosqrt (double a) +{ + return __builtin_pow (a, 0.75); /* should call pow */ +} + +double +do_pow_0_5_nosqrt (double a) +{ + return __builtin_pow (a, 0.5); /* should call sqrt */ +} + +#pragma GCC reset_options diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c new file mode 100644 index 000000000..20262aa44 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-times "stfiwx" 4 } } */ +/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ +/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ +/* { dg-final { scan-assembler-times "fctiwz" 2 } } */ +/* { dg-final { scan-assembler-times "xscvsxddp" 2 } } */ +/* { dg-final { scan-assembler-times "fcfids" 2 } } */ +/* { dg-final { scan-assembler-not "lwz" } } */ +/* { dg-final { scan-assembler-not "stw" } } */ + +/* Make sure we don't have loads/stores to the GPR unit. */ +double +round_double_int (double a) +{ + return (double)(int)a; +} + +float +round_float_int (float a) +{ + return (float)(int)a; +} + +double +round_double_uint (double a) +{ + return (double)(unsigned int)a; +} + +float +round_float_uint (float a) +{ + return (float)(unsigned int)a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c new file mode 100644 index 000000000..5f39d8636 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */ +/* { dg-options "-O2 -fno-common -G 8 -meabi -msdata=eabi" } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata2," } } */ +/* { dg-final { scan-assembler "sdat@sda21\\((13|0)\\)" } } */ +/* { dg-final { scan-assembler "sdat2@sda21\\((2|0)\\)" } } */ + + +int sdat = 2; +const char sdat2[] = "1234"; + +const char * test (void) +{ + return sdat ? sdat2 : 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c new file mode 100644 index 000000000..f102b1d1f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */ +/* { dg-options "-O2 -fno-common -G 8 -msdata=sysv" } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */ +/* { dg-final { scan-assembler-not "\\.section\[ \t\]\\.sdata2," } } */ +/* { dg-final { scan-assembler "sdat@sdarel\\(13\\)" } } */ +/* { dg-final { scan-assembler "sdat2@sdarel\\(13\\)" } } */ + + +int sdat = 2; +const char sdat2[] = "1234"; + +const char * test (void) +{ + return sdat ? sdat2 : 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c new file mode 100644 index 000000000..b56439433 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c @@ -0,0 +1,663 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* (Test with -O0 so we don't optimize any of them away). */ + +#include <spe.h> + +/* Test PowerPC SPE extensions. */ + +#define vector __attribute__((vector_size(8))) + +vector int a, b, c, *ap; +vector float f, g, h; +unsigned int *uip; +unsigned short *usp; +int i, j, *ip; +uint64_t ull; +int64_t sll; +unsigned ui; +float fl; +uint16_t u16; +int16_t s16; + +/* These are the only documented/supported accesor functions for the + SPE builtins. */ +void +test_api () +{ + c = __ev_addw (a, b); + c = __ev_addiw (a, 8); + c = __ev_subfw (a, b); + c = __ev_subifw (8, a); + c = __ev_abs (a); + c = __ev_neg (a); + c = __ev_extsb (a); + c = __ev_extsh (a); + c = __ev_and (a, b); + c = __ev_or (a, b); + c = __ev_xor (a, b); + c = __ev_nand (a, b); + c = __ev_nor (a, b); + c = __ev_eqv (a, b); + c = __ev_andc (a, b); + c = __ev_orc (a, b); + c = __ev_rlw (a, b); + c = __ev_rlwi (a, 8); + c = __ev_slw (a, b); + c = __ev_slwi (a, 8); + c = __ev_srws (a, b); + c = __ev_srwu (a, b); + c = __ev_srwis (a, 8); + c = __ev_srwiu (a, 8); + c = __ev_cntlzw (a); + c = __ev_cntlsw (a); + c = __ev_rndw (a); + c = __ev_mergehi (a, b); + c = __ev_mergelo (a, b); + c = __ev_mergelohi (a, b); + c = __ev_mergehilo (a, b); + c = __ev_splati (5); + c = __ev_splatfi (6); + c = __ev_divws (a, b); + c = __ev_divwu (a, b); + c = __ev_mra (a); + i = __brinc (5, 6); + + /* Loads. */ + c = __ev_lddx (ap, i); + c = __ev_ldwx (ap, i); + c = __ev_ldhx (ap, i); + + c = __ev_lwhex (uip, i); + c = __ev_lwhoux (uip, i); + c = __ev_lwhosx (uip, i); + c = __ev_lwwsplatx (uip, i); + c = __ev_lwhsplatx (uip, i); + + c = __ev_lhhesplatx (usp, i); + c = __ev_lhhousplatx (usp, i); + c = __ev_lhhossplatx (usp, i); + + c = __ev_ldd (ap, 5); + c = __ev_ldw (ap, 6); + c = __ev_ldh (ap, 7); + c = __ev_lwhe (uip, 6); + c = __ev_lwhou (uip, 6); + c = __ev_lwhos (uip, 7); + c = __ev_lwwsplat (uip, 7); + c = __ev_lwhsplat (uip, 7); + c = __ev_lhhesplat (usp, 7); + c = __ev_lhhousplat (usp, 7); + c = __ev_lhhossplat (usp, 7); + + /* Stores. */ + __ev_stddx (a, ap, 9); + __ev_stdwx (a, ap, 9); + __ev_stdhx (a, ap, 9); + __ev_stwwex (a, uip, 9); + __ev_stwwox (a, uip, 9); + __ev_stwhex (a, uip, 9); + __ev_stwhox (a, uip, 9); + __ev_stdd (a, ap, 9); + __ev_stdw (a, ap, 9); + __ev_stdh (a, ap, 9); + __ev_stwwe (a, uip, 9); + __ev_stwwo (a, uip, 9); + __ev_stwhe (a, uip, 9); + __ev_stwho (a, uip, 9); + + /* Fixed point complex. */ + c = __ev_mhossf (a, b); + c = __ev_mhosmf (a, b); + c = __ev_mhosmi (a, b); + c = __ev_mhoumi (a, b); + c = __ev_mhessf (a, b); + c = __ev_mhesmf (a, b); + c = __ev_mhesmi (a, b); + c = __ev_mheumi (a, b); + c = __ev_mhossfa (a, b); + c = __ev_mhosmfa (a, b); + c = __ev_mhosmia (a, b); + c = __ev_mhoumia (a, b); + c = __ev_mhessfa (a, b); + c = __ev_mhesmfa (a, b); + c = __ev_mhesmia (a, b); + c = __ev_mheumia (a, b); + + c = __ev_mhoumf (a, b); + c = __ev_mheumf (a, b); + c = __ev_mhoumfa (a, b); + c = __ev_mheumfa (a, b); + + c = __ev_mhossfaaw (a, b); + c = __ev_mhossiaaw (a, b); + c = __ev_mhosmfaaw (a, b); + c = __ev_mhosmiaaw (a, b); + c = __ev_mhousiaaw (a, b); + c = __ev_mhoumiaaw (a, b); + c = __ev_mhessfaaw (a, b); + c = __ev_mhessiaaw (a, b); + c = __ev_mhesmfaaw (a, b); + c = __ev_mhesmiaaw (a, b); + c = __ev_mheusiaaw (a, b); + c = __ev_mheumiaaw (a, b); + + c = __ev_mhousfaaw (a, b); + c = __ev_mhoumfaaw (a, b); + c = __ev_mheusfaaw (a, b); + c = __ev_mheumfaaw (a, b); + + c = __ev_mhossfanw (a, b); + c = __ev_mhossianw (a, b); + c = __ev_mhosmfanw (a, b); + c = __ev_mhosmianw (a, b); + c = __ev_mhousianw (a, b); + c = __ev_mhoumianw (a, b); + c = __ev_mhessfanw (a, b); + c = __ev_mhessianw (a, b); + c = __ev_mhesmfanw (a, b); + c = __ev_mhesmianw (a, b); + c = __ev_mheusianw (a, b); + c = __ev_mheumianw (a, b); + + c = __ev_mhousfanw (a, b); + c = __ev_mhoumfanw (a, b); + c = __ev_mheusfanw (a, b); + c = __ev_mheumfanw (a, b); + + c = __ev_mhogsmfaa (a, b); + c = __ev_mhogsmiaa (a, b); + c = __ev_mhogumiaa (a, b); + c = __ev_mhegsmfaa (a, b); + c = __ev_mhegsmiaa (a, b); + c = __ev_mhegumiaa (a, b); + + c = __ev_mhogumfaa (a, b); + c = __ev_mhegumfaa (a, b); + + c = __ev_mhogsmfan (a, b); + c = __ev_mhogsmian (a, b); + c = __ev_mhogumian (a, b); + c = __ev_mhegsmfan (a, b); + c = __ev_mhegsmian (a, b); + c = __ev_mhegumian (a, b); + + c = __ev_mhogumfan (a, b); + c = __ev_mhegumfan (a, b); + + c = __ev_mwhssf (a, b); + c = __ev_mwhsmf (a, b); + c = __ev_mwhsmi (a, b); + c = __ev_mwhumi (a, b); + c = __ev_mwhssfa (a, b); + c = __ev_mwhsmfa (a, b); + c = __ev_mwhsmia (a, b); + c = __ev_mwhumia (a, b); + + c = __ev_mwhumf (a, b); + c = __ev_mwhumfa (a, b); + + c = __ev_mwlumi (a, b); + c = __ev_mwlumia (a, b); + c = __ev_mwlumiaaw (a, b); + + c = __ev_mwlssiaaw (a, b); + c = __ev_mwlsmiaaw (a, b); + c = __ev_mwlusiaaw (a, b); + c = __ev_mwlusiaaw (a, b); + + c = __ev_mwlssianw (a, b); + c = __ev_mwlsmianw (a, b); + c = __ev_mwlusianw (a, b); + c = __ev_mwlumianw (a, b); + + c = __ev_mwssf (a, b); + c = __ev_mwsmf (a, b); + c = __ev_mwsmi (a, b); + c = __ev_mwumi (a, b); + c = __ev_mwssfa (a, b); + c = __ev_mwsmfa (a, b); + c = __ev_mwsmia (a, b); + c = __ev_mwumia (a, b); + c = __ev_mwumf (a, b); + c = __ev_mwumfa (a, b); + c = __ev_mwssfaa (a, b); + c = __ev_mwsmfaa (a, b); + c = __ev_mwsmiaa (a, b); + c = __ev_mwumiaa (a, b); + c = __ev_mwumfaa (a, b); + c = __ev_mwssfan (a, b); + c = __ev_mwsmfan (a, b); + c = __ev_mwsmian (a, b); + c = __ev_mwumian (a, b); + c = __ev_mwumfan (a, b); + c = __ev_addssiaaw (a); + c = __ev_addsmiaaw (a); + c = __ev_addusiaaw (a); + c = __ev_addumiaaw (a); + c = __ev_addusfaaw (a); + c = __ev_addumfaaw (a); + c = __ev_addsmfaaw (a); + c = __ev_addssfaaw (a); + c = __ev_subfssiaaw (a); + c = __ev_subfsmiaaw (a); + c = __ev_subfusiaaw (a); + c = __ev_subfumiaaw (a); + c = __ev_subfusfaaw (a); + c = __ev_subfumfaaw (a); + c = __ev_subfsmfaaw (a); + c = __ev_subfssfaaw (a); + + /* Floating point SIMD instructions. */ + c = __ev_fsabs (a); + c = __ev_fsnabs (a); + c = __ev_fsneg (a); + c = __ev_fsadd (a, b); + c = __ev_fssub (a, b); + c = __ev_fsmul (a, b); + c = __ev_fsdiv (a, b); + c = __ev_fscfui (a); + c = __ev_fscfsi (a); + c = __ev_fscfuf (a); + c = __ev_fscfsf (a); + c = __ev_fsctui (a); + c = __ev_fsctsi (a); + c = __ev_fsctuf (a); + c = __ev_fsctsf (a); + c = __ev_fsctuiz (a); + c = __ev_fsctsiz (a); + + /* Non supported sythetic instructions made from two instructions. */ + + c = __ev_mwhssfaaw (a, b); + c = __ev_mwhssiaaw (a, b); + c = __ev_mwhsmfaaw (a, b); + c = __ev_mwhsmiaaw (a, b); + c = __ev_mwhusiaaw (a, b); + c = __ev_mwhumiaaw (a, b); + c = __ev_mwhusfaaw (a, b); + c = __ev_mwhumfaaw (a, b); + c = __ev_mwhssfanw (a, b); + c = __ev_mwhssianw (a, b); + c = __ev_mwhsmfanw (a, b); + c = __ev_mwhsmianw (a, b); + c = __ev_mwhusianw (a, b); + c = __ev_mwhumianw (a, b); + c = __ev_mwhusfanw (a, b); + c = __ev_mwhumfanw (a, b); + + c = __ev_mwhgssfaa (a, b); + c = __ev_mwhgsmfaa (a, b); + c = __ev_mwhgsmiaa (a, b); + c = __ev_mwhgumiaa (a, b); + c = __ev_mwhgssfan (a, b); + c = __ev_mwhgsmfan (a, b); + c = __ev_mwhgsmian (a, b); + c = __ev_mwhgumian (a, b); + + /* Creating, insertion, and extraction. */ + + a = __ev_create_u64 ((uint64_t) 55); + a = __ev_create_s64 ((int64_t) 66); + a = __ev_create_fs (3.14F, 2.18F); + a = __ev_create_u32 ((uint32_t) 5, (uint32_t) i); + a = __ev_create_s32 ((int32_t) 5, (int32_t) 6); + a = __ev_create_u16 ((uint16_t) 6, (uint16_t) 6, (uint16_t) 7, (uint16_t) 1); + a = __ev_create_s16 ((int16_t) 6, (int16_t) 6, (int16_t) 7, (int16_t) 9); + a = __ev_create_sfix32_fs (3.0F, 2.0F); + a = __ev_create_ufix32_fs (3.0F, 2.0F); + a = __ev_create_ufix32_u32 (3U, 5U); + a = __ev_create_sfix32_s32 (6, 9); + ull = __ev_convert_u64 (a); + sll = __ev_convert_s64 (a); + i = __ev_get_upper_u32 (a); + ui = __ev_get_lower_u32 (a); + i = __ev_get_upper_s32 (a); + i = __ev_get_lower_s32 (a); + fl = __ev_get_upper_fs (a); + fl = __ev_get_lower_fs (a); + u16 = __ev_get_u16 (a, 5U); + s16 = __ev_get_s16 (a, 5U); + ui = __ev_get_upper_ufix32_u32 (a); + ui = __ev_get_lower_ufix32_u32 (a); + i = __ev_get_upper_sfix32_s32 (a); + i = __ev_get_lower_sfix32_s32 (a); + fl = __ev_get_upper_sfix32_fs (a); + fl = __ev_get_lower_sfix32_fs (a); + fl = __ev_get_upper_ufix32_fs (a); + fl = __ev_get_lower_ufix32_fs (a); + a = __ev_set_upper_u32 (a, 5U); + a = __ev_set_lower_u32 (a, 5U); + a = __ev_set_upper_s32 (a, 5U); + a = __ev_set_lower_s32 (a, 6U); + a = __ev_set_upper_fs (a, 6U); + a = __ev_set_lower_fs (a, fl); + a = __ev_set_upper_ufix32_u32 (a, 5U); + a = __ev_set_lower_ufix32_u32 (a, 5U); + a = __ev_set_upper_sfix32_s32 (a, 5); + a = __ev_set_lower_sfix32_s32 (a, 5); + a = __ev_set_upper_sfix32_fs (a, fl); + a = __ev_set_lower_sfix32_fs (a, fl); + a = __ev_set_upper_ufix32_fs (a, fl); + a = __ev_set_lower_ufix32_fs (a, fl); + a = __ev_set_acc_u64 ((uint64_t) 640); + a = __ev_set_acc_s64 ((int64_t) 460); + a = __ev_set_acc_vec64 (b); + a = __ev_set_u32 (a, 5, 6); + a = __ev_set_s32 (a, 5, 6); + a = __ev_set_fs (a, fl, 5); + a = __ev_set_u16 (a, 5U, 3); + a = __ev_set_s16 (a, 5, 6); + a = __ev_set_ufix32_u32 (a, 5U, 6U); + a = __ev_set_sfix32_s32 (a, 3, 6); + a = __ev_set_ufix32_fs (a, fl, 5); + a = __ev_set_sfix32_fs (a, fl, 5); + ui = __ev_get_u32 (a, 1); + i = __ev_get_s32 (a, 0); + fl = __ev_get_fs (a, 1); + u16 = __ev_get_u16 (a, 2); + s16 = __ev_get_s16 (a, 2); + ui = __ev_get_ufix32_u32 (a, 1); + i = __ev_get_sfix32_s32 (a, 0); + fl = __ev_get_ufix32_fs (a, 1); + fl = __ev_get_sfix32_fs (a, 0); + + /* Predicates. */ + i = __ev_any_gts (a, b); + i = __ev_all_gts (a, b); + i = __ev_upper_gts (a, b); + i = __ev_lower_gts (a, b); + a = __ev_select_gts (a, b, c, c); + + i = __ev_any_gtu (a, b); + i = __ev_all_gtu (a, b); + i = __ev_upper_gtu (a, b); + i = __ev_lower_gtu (a, b); + a = __ev_select_gtu (a, b, c, c); + + i = __ev_any_lts (a, b); + i = __ev_all_lts (a, b); + i = __ev_upper_lts (a, b); + i = __ev_lower_lts (a, b); + a = __ev_select_lts (a, b, c, c); + + i = __ev_any_ltu (a, b); + i = __ev_all_ltu (a, b); + i = __ev_upper_ltu (a, b); + i = __ev_lower_ltu (a, b); + a = __ev_select_ltu (a, b, c, c); + + i = __ev_any_eq (a, b); + i = __ev_all_eq (a, b); + i = __ev_upper_eq (a, b); + i = __ev_lower_eq (a, b); + a = __ev_select_eq (a, b, c, c); + + i = __ev_any_fs_gt (a, b); + i = __ev_all_fs_gt (a, b); + i = __ev_upper_fs_gt (a, b); + i = __ev_lower_fs_gt (a, b); + a = __ev_select_fs_gt (a, b, c, c); + + i = __ev_any_fs_lt (a, b); + i = __ev_all_fs_lt (a, b); + i = __ev_upper_fs_lt (a, b); + i = __ev_lower_fs_lt (a, b); + a = __ev_select_fs_lt (a, b, c, b); + + i = __ev_any_fs_eq (a, b); + i = __ev_all_fs_eq (a, b); + i = __ev_upper_fs_eq (a, b); + i = __ev_lower_fs_eq (a, b); + a = __ev_select_fs_eq (a, b, c, c); + + i = __ev_any_fs_tst_gt (a, b); + i = __ev_all_fs_tst_gt (a, b); + i = __ev_upper_fs_tst_gt (a, b); + i = __ev_lower_fs_tst_gt (a, b); + a = __ev_select_fs_tst_gt (a, b, c, c); + + i = __ev_any_fs_tst_lt (a, b); + i = __ev_all_fs_tst_lt (a, b); + i = __ev_upper_fs_tst_lt (a, b); + i = __ev_lower_fs_tst_lt (a, b); + a = __ev_select_fs_tst_lt (a, b, c, c); + + i = __ev_any_fs_tst_eq (a, b); + i = __ev_all_fs_tst_eq (a, b); + i = __ev_upper_fs_tst_eq (a, b); + i = __ev_lower_fs_tst_eq (a, b); + a = __ev_select_fs_tst_eq (a, b, c, c); +} + +int +main (void) +{ + /* Generic binary operations. */ + c = __builtin_spe_evaddw (a, b); + c = __builtin_spe_evand (a, b); + c = __builtin_spe_evandc (a, b); + c = __builtin_spe_evdivws (a, b); + c = __builtin_spe_evdivwu (a, b); + c = __builtin_spe_eveqv (a, b); + h = __builtin_spe_evfsadd (f, g); + h = __builtin_spe_evfsdiv (f, g); + h = __builtin_spe_evfsmul (f, g); + h = __builtin_spe_evfssub (f, g); + c = __builtin_spe_evlddx (ap, j); + c = __builtin_spe_evldhx (ap, j); + c = __builtin_spe_evldwx (ap, j); + c = __builtin_spe_evlhhesplatx (usp, j); + c = __builtin_spe_evlhhossplatx (usp, j); + c = __builtin_spe_evlhhousplatx (usp, j); + c = __builtin_spe_evlwhex (uip, j); + c = __builtin_spe_evlwhosx (uip, j); + c = __builtin_spe_evlwhoux (uip, j); + c = __builtin_spe_evlwhsplatx (uip, j); + c = __builtin_spe_evlwwsplatx (uip, j); + c = __builtin_spe_evmergehi (a, b); + c = __builtin_spe_evmergehilo (a, b); + c = __builtin_spe_evmergelo (a, b); + c = __builtin_spe_evmergelohi (a, b); + c = __builtin_spe_evmhegsmfaa (a, b); + c = __builtin_spe_evmhegsmfan (a, b); + c = __builtin_spe_evmhegsmiaa (a, b); + c = __builtin_spe_evmhegsmian (a, b); + c = __builtin_spe_evmhegumiaa (a, b); + c = __builtin_spe_evmhegumian (a, b); + c = __builtin_spe_evmhesmf (a, b); + c = __builtin_spe_evmhesmfa (a, b); + c = __builtin_spe_evmhesmfaaw (a, b); + c = __builtin_spe_evmhesmfanw (a, b); + c = __builtin_spe_evmhesmi (a, b); + c = __builtin_spe_evmhesmia (a, b); + c = __builtin_spe_evmhesmiaaw (a, b); + c = __builtin_spe_evmhesmianw (a, b); + c = __builtin_spe_evmhessf (a, b); + c = __builtin_spe_evmhessfa (a, b); + c = __builtin_spe_evmhessfaaw (a, b); + c = __builtin_spe_evmhessfanw (a, b); + c = __builtin_spe_evmhessiaaw (a, b); + c = __builtin_spe_evmhessianw (a, b); + c = __builtin_spe_evmheumi (a, b); + c = __builtin_spe_evmheumia (a, b); + c = __builtin_spe_evmheumiaaw (a, b); + c = __builtin_spe_evmheumianw (a, b); + c = __builtin_spe_evmheusiaaw (a, b); + c = __builtin_spe_evmheusianw (a, b); + c = __builtin_spe_evmhogsmfaa (a, b); + c = __builtin_spe_evmhogsmfan (a, b); + c = __builtin_spe_evmhogsmiaa (a, b); + c = __builtin_spe_evmhogsmian (a, b); + c = __builtin_spe_evmhogumiaa (a, b); + c = __builtin_spe_evmhogumian (a, b); + c = __builtin_spe_evmhosmf (a, b); + c = __builtin_spe_evmhosmfa (a, b); + c = __builtin_spe_evmhosmfaaw (a, b); + c = __builtin_spe_evmhosmfanw (a, b); + c = __builtin_spe_evmhosmi (a, b); + c = __builtin_spe_evmhosmia (a, b); + c = __builtin_spe_evmhosmiaaw (a, b); + c = __builtin_spe_evmhosmianw (a, b); + c = __builtin_spe_evmhossf (a, b); + c = __builtin_spe_evmhossfa (a, b); + c = __builtin_spe_evmhossfaaw (a, b); + c = __builtin_spe_evmhossfanw (a, b); + c = __builtin_spe_evmhossiaaw (a, b); + c = __builtin_spe_evmhossianw (a, b); + c = __builtin_spe_evmhoumi (a, b); + c = __builtin_spe_evmhoumia (a, b); + c = __builtin_spe_evmhoumiaaw (a, b); + c = __builtin_spe_evmhoumianw (a, b); + c = __builtin_spe_evmhousiaaw (a, b); + c = __builtin_spe_evmhousianw (a, b); + c = __builtin_spe_evmwhsmf (a, b); + c = __builtin_spe_evmwhsmfa (a, b); + c = __builtin_spe_evmwhsmi (a, b); + c = __builtin_spe_evmwhsmia (a, b); + c = __builtin_spe_evmwhssf (a, b); + c = __builtin_spe_evmwhssfa (a, b); + c = __builtin_spe_evmwhumi (a, b); + c = __builtin_spe_evmwhumia (a, b); + c = __builtin_spe_evmwlsmiaaw (a, b); + c = __builtin_spe_evmwlsmianw (a, b); + c = __builtin_spe_evmwlssiaaw (a, b); + c = __builtin_spe_evmwlssianw (a, b); + c = __builtin_spe_evmwlumi (a, b); + c = __builtin_spe_evmwlumia (a, b); + c = __builtin_spe_evmwlumiaaw (a, b); + c = __builtin_spe_evmwlumianw (a, b); + c = __builtin_spe_evmwlusiaaw (a, b); + c = __builtin_spe_evmwlusianw (a, b); + c = __builtin_spe_evmwsmf (a, b); + c = __builtin_spe_evmwsmfa (a, b); + c = __builtin_spe_evmwsmfaa (a, b); + c = __builtin_spe_evmwsmfan (a, b); + c = __builtin_spe_evmwsmi (a, b); + c = __builtin_spe_evmwsmia (a, b); + c = __builtin_spe_evmwsmiaa (a, b); + c = __builtin_spe_evmwsmian (a, b); + c = __builtin_spe_evmwssf (a, b); + c = __builtin_spe_evmwssfa (a, b); + c = __builtin_spe_evmwssfaa (a, b); + c = __builtin_spe_evmwssfan (a, b); + c = __builtin_spe_evmwumi (a, b); + c = __builtin_spe_evmwumia (a, b); + c = __builtin_spe_evmwumiaa (a, b); + c = __builtin_spe_evmwumian (a, b); + c = __builtin_spe_evnand (a, b); + c = __builtin_spe_evnor (a, b); + c = __builtin_spe_evor (a, b); + c = __builtin_spe_evorc (a, b); + c = __builtin_spe_evrlw (a, b); + c = __builtin_spe_evslw (a, b); + c = __builtin_spe_evsrws (a, b); + c = __builtin_spe_evsrwu (a, b); + c = __builtin_spe_evsubfw (a, b); + c = __builtin_spe_evxor (a, b); + + c = __builtin_spe_evmwhssfaa (a, b); + c = __builtin_spe_evmwhssmaa (a, b); + c = __builtin_spe_evmwhsmfaa (a, b); + c = __builtin_spe_evmwhsmiaa (a, b); + c = __builtin_spe_evmwhusiaa (a, b); + c = __builtin_spe_evmwhumiaa (a, b); + c = __builtin_spe_evmwhssfan (a, b); + c = __builtin_spe_evmwhssian (a, b); + c = __builtin_spe_evmwhsmfan (a, b); + c = __builtin_spe_evmwhsmian (a, b); + c = __builtin_spe_evmwhusian (a, b); + c = __builtin_spe_evmwhumian (a, b); + c = __builtin_spe_evmwhgssfaa (a, b); + c = __builtin_spe_evmwhgsmfaa (a, b); + c = __builtin_spe_evmwhgsmiaa (a, b); + c = __builtin_spe_evmwhgumiaa (a, b); + c = __builtin_spe_evmwhgssfan (a, b); + c = __builtin_spe_evmwhgsmfan (a, b); + c = __builtin_spe_evmwhgsmian (a, b); + c = __builtin_spe_evmwhgumian (a, b); + i = __builtin_spe_brinc (i, j); + + /* Generic unary operations. */ + a = __builtin_spe_evabs (b); + a = __builtin_spe_evaddsmiaaw (b); + a = __builtin_spe_evaddssiaaw (b); + a = __builtin_spe_evaddumiaaw (b); + a = __builtin_spe_evaddusiaaw (b); + a = __builtin_spe_evcntlsw (b); + a = __builtin_spe_evcntlzw (b); + a = __builtin_spe_evextsb (b); + a = __builtin_spe_evextsh (b); + f = __builtin_spe_evfsabs (g); + f = __builtin_spe_evfscfsf (g); + a = __builtin_spe_evfscfsi (g); + f = __builtin_spe_evfscfuf (g); + f = __builtin_spe_evfscfui (a); + f = __builtin_spe_evfsctsf (g); + a = __builtin_spe_evfsctsi (g); + a = __builtin_spe_evfsctsiz (g); + f = __builtin_spe_evfsctuf (g); + a = __builtin_spe_evfsctui (g); + a = __builtin_spe_evfsctuiz (g); + f = __builtin_spe_evfsnabs (g); + f = __builtin_spe_evfsneg (g); + a = __builtin_spe_evmra (b); + a = __builtin_spe_evneg (b); + a = __builtin_spe_evrndw (b); + a = __builtin_spe_evsubfsmiaaw (b); + a = __builtin_spe_evsubfssiaaw (b); + a = __builtin_spe_evsubfumiaaw (b); + a = __builtin_spe_evsubfusiaaw (b); + + /* Unary operations of the form: X = foo (5_bit_signed_immediate). */ + a = __builtin_spe_evsplatfi (5); + a = __builtin_spe_evsplati (5); + + /* Binary operations of the form: X = foo(Y, 5_bit_immediate). */ + a = __builtin_spe_evaddiw (b, 13); + a = __builtin_spe_evldd (ap, 13); + a = __builtin_spe_evldh (ap, 13); + a = __builtin_spe_evldw (ap, 13); + a = __builtin_spe_evlhhesplat (usp, 13); + a = __builtin_spe_evlhhossplat (usp, 13); + a = __builtin_spe_evlhhousplat (usp, 13); + a = __builtin_spe_evlwhe (uip, 13); + a = __builtin_spe_evlwhos (uip, 13); + a = __builtin_spe_evlwhou (uip, 13); + a = __builtin_spe_evlwhsplat (uip, 13); + a = __builtin_spe_evlwwsplat (uip, 13); + + a = __builtin_spe_evrlwi (b, 13); + a = __builtin_spe_evslwi (b, 13); + a = __builtin_spe_evsrwis (b, 13); + a = __builtin_spe_evsrwiu (b, 13); + a = __builtin_spe_evsubifw (b, 13); + + /* Store indexed builtins. */ + __builtin_spe_evstddx (b, ap, j); + __builtin_spe_evstdhx (b, ap, j); + __builtin_spe_evstdwx (b, ap, j); + __builtin_spe_evstwhex (b, uip, j); + __builtin_spe_evstwhox (b, uip, j); + __builtin_spe_evstwwex (b, uip, j); + __builtin_spe_evstwwox (b, uip, j); + + /* Store indexed immediate builtins. */ + __builtin_spe_evstdd (b, ap, 5); + __builtin_spe_evstdh (b, ap, 5); + __builtin_spe_evstdw (b, ap, 5); + __builtin_spe_evstwhe (b, uip, 5); + __builtin_spe_evstwho (b, uip, 5); + __builtin_spe_evstwwe (b, uip, 5); + __builtin_spe_evstwwo (b, uip, 5); + + /* SPEFSCR builtins. */ + i = __builtin_spe_mfspefscr (); + __builtin_spe_mtspefscr (j); + + test_api (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c new file mode 100644 index 000000000..f07e818fa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c @@ -0,0 +1,7 @@ +/* Test that SPE targets do not permit -m64. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile { target powerpc-*-*spe } } */ +/* { dg-options "-m64" } */ + +/* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */ +/* { dg-error "64-bit E500 not supported" "64-bit E500" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c new file mode 100644 index 000000000..465fc41e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target powerpc*-*-linux* powerpc*-*-eabi* } } */ +/* { dg-options {} } */ + +/* Test stack pointer alignment against variable alloca. */ +/* Inspired by PR libgcj/10610. */ +/* Origin: Franz Sirl <Franz.Sirl-kernel@lauterbach.com>. */ + +extern void abort (void); +extern void exit (int); + +register unsigned long sp __asm__ ("r1"); + +void g (int * val __attribute__ ((unused))) +{ + if (sp & 0xf) + abort (); +} + +void f (int val) +{ + int *val1 = __builtin_alloca (val); + + g (val1); + return; +} + +int main (void) +{ + int i; + + for (i = 1; i < 32; i++) + f (i); + + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c b/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c new file mode 100644 index 000000000..47a29ed3f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-mpowerpc-gfxopt" } */ +/* { dg-final { scan-assembler "stfiwx" } } */ + +int foo (double x) +{ + return x; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c new file mode 100644 index 000000000..c98666c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */ +/* { dg-final { scan-assembler-times "fabs" 3 } } */ +/* { dg-final { scan-assembler-times "fnabs" 3 } } */ +/* { dg-final { scan-assembler-times "fsel" 3 } } */ +/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */ +/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */ + +double normal1 (double, double); +double power5 (double, double) __attribute__((__target__("cpu=power5"))); +double power6 (double, double) __attribute__((__target__("cpu=power6"))); +double power6x (double, double) __attribute__((__target__("cpu=power6x"))); +double power7 (double, double) __attribute__((__target__("cpu=power7"))); +double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx"))); +double normal2 (double, double); + +/* fabs/fnabs/fsel */ +double normal1 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fabs/fnabs/fsel */ +double power5 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power6 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power6x (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* xscpsgndp */ +double power7 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power7n (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fabs/fnabs/fsel */ +double normal2 (double a, double b) +{ + return __builtin_copysign (a, b); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c new file mode 100644 index 000000000..8ef95b7a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */ +/* { dg-final { scan-assembler-times "fabs" 3 } } */ +/* { dg-final { scan-assembler-times "fnabs" 3 } } */ +/* { dg-final { scan-assembler-times "fsel" 3 } } */ +/* { dg-final { scan-assembler-times "fcpsgn" 3 } } */ +/* { dg-final { scan-assembler-times "xscpsgndp" 1 } } */ + +/* fabs/fnabs/fsel */ +double normal1 (double a, double b) { return __builtin_copysign (a, b); } + +#pragma GCC push_options +#pragma GCC target ("cpu=power5") +/* fabs/fnabs/fsel */ +double power5 (double a, double b) { return __builtin_copysign (a, b); } +#pragma GCC pop_options + +#pragma GCC target ("cpu=power6") +/* fcpsgn */ +double power6 (double a, double b) { return __builtin_copysign (a, b); } +#pragma GCC reset_options + +#pragma GCC target ("cpu=power6x") +/* fcpsgn */ +double power6x (double a, double b) { return __builtin_copysign (a, b); } +#pragma GCC reset_options + +#pragma GCC target ("cpu=power7") +/* xscpsgndp */ +double power7 (double a, double b) { return __builtin_copysign (a, b); } +#pragma GCC reset_options + +#pragma GCC target ("cpu=power7,no-vsx") +/* fcpsgn */ +double power7n (double a, double b) { return __builtin_copysign (a, b); } +#pragma GCC reset_options + +/* fabs/fnabs/fsel */ +double normal2 (double a, double b) { return __builtin_copysign (a, b); } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c new file mode 100644 index 000000000..286f31f63 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c @@ -0,0 +1,62 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=no-altivec" } */ +/* { dg-final { scan-assembler-times "fabs" 3 } } */ +/* { dg-final { scan-assembler-times "fnabs" 3 } } */ +/* { dg-final { scan-assembler-times "fsel" 3 } } */ +/* { dg-final { scan-assembler-times "fcpsgn" 4 } } */ +/* { dg-final { scan-assembler-not "xscpsgndp" } } */ + +/* Like ppc-target-1.c, but do not enable the altivec abi on 32-bit, so the + power7 code should generate fcpsgn and not xscpsgndp. */ + +double normal1 (double, double); +double power5 (double, double) __attribute__((__target__("cpu=power5"))); +double power6 (double, double) __attribute__((__target__("cpu=power6"))); +double power6x (double, double) __attribute__((__target__("cpu=power6x"))); +double power7 (double, double) __attribute__((__target__("cpu=power7"))); +double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx"))); +double normal2 (double, double); + +/* fabs/fnabs/fsel */ +double normal1 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fabs/fnabs/fsel */ +double power5 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power6 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power6x (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* xscpsgndp */ +double power7 (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fcpsgn */ +double power7n (double a, double b) +{ + return __builtin_copysign (a, b); +} + +/* fabs/fnabs/fsel */ +double normal2 (double a, double b) +{ + return __builtin_copysign (a, b); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c new file mode 100644 index 000000000..797c4074d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ +/* { dg-final { scan-assembler "lvx" } } */ + +void foo(void) +{ + int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c new file mode 100644 index 000000000..ad7aadea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ +/* { dg-final { scan-assembler "stvx" } } */ + +#include <string.h> + +void foo(void) +{ + int x[8] __attribute__((aligned(128))); + memset (x, 0, sizeof (x)); + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c new file mode 100644 index 000000000..14908dba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c @@ -0,0 +1,253 @@ +/* { dg-do run { target { powerpc_fprs && { ilp32 && dfprt } } } } */ +/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC ELF ABI for decimal float values. */ + +extern void abort (void); +int failcnt = 0; + +/* Support compiling the test to report individual failures; default is + to abort as soon as a check fails. */ +#ifdef DBG +#include <stdio.h> +#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; } +#else +#define FAILURE abort (); +#endif + +typedef struct +{ + int pad; + _Decimal32 d; +} d32parm_t; + +typedef struct +{ + unsigned int gprs[8]; + double fprs[8]; +} reg_parms_t; + +reg_parms_t gparms; + +typedef struct sf +{ + struct sf *backchain; + int a1; + unsigned int slot[200]; +} stack_frame_t; + +/* Wrapper to save the GPRs and FPRs and then jump to the real function. */ +#define WRAPPER(NAME) \ +__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ + ".text\n\t" \ + ".type " #NAME "_asm, @function\n" \ + #NAME "_asm:\n\t" \ + "lis 11,gparms@ha\n\t" \ + "la 11,gparms@l(11)\n\t" \ + "st 3,0(11)\n\t" \ + "st 4,4(11)\n\t" \ + "st 5,8(11)\n\t" \ + "st 6,12(11)\n\t" \ + "st 7,16(11)\n\t" \ + "st 8,20(11)\n\t" \ + "st 9,24(11)\n\t" \ + "st 10,28(11)\n\t" \ + "stfd 1,32(11)\n\t" \ + "stfd 2,40(11)\n\t" \ + "stfd 3,48(11)\n\t" \ + "stfd 4,56(11)\n\t" \ + "stfd 5,64(11)\n\t" \ + "stfd 6,72(11)\n\t" \ + "stfd 7,80(11)\n\t" \ + "stfd 8,88(11)\n\t" \ + "b " #NAME "\n\t" \ + ".size " #NAME ",.-" #NAME "\n") + +/* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ +extern void func0_asm (double, double, double, double, double, + double, double, double, _Decimal64, _Decimal128); + +WRAPPER(func0); + +void __attribute__ ((noinline)) +func0 (double a1, double a2, double a3, double a4, double a5, + double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != gparms.fprs[0]) FAILURE + if (a2 != gparms.fprs[1]) FAILURE + if (a3 != gparms.fprs[2]) FAILURE + if (a4 != gparms.fprs[3]) FAILURE + if (a5 != gparms.fprs[4]) FAILURE + if (a6 != gparms.fprs[5]) FAILURE + if (a7 != gparms.fprs[6]) FAILURE + if (a8 != gparms.fprs[7]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE +} + +/* Alternate 64-bit and 128-bit decimal float arguments, checking that + _Decimal128 is always passed in even/odd register pairs. */ +extern void func1_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, + _Decimal64, _Decimal128, _Decimal64, _Decimal128); + +WRAPPER(func1); + +void __attribute__ ((noinline)) +func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE +} + +extern void func2_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64, + _Decimal128, _Decimal64, _Decimal128, _Decimal64); + +WRAPPER(func2); + +void __attribute__ ((noinline)) +func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ + if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE +} + +extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, + _Decimal64); + +WRAPPER(func3); + +void __attribute__ ((noinline)) +func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE +} + +extern void func4_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32); + +WRAPPER(func4); + +void __attribute__ ((noinline)) +func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot. */ + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */ + if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */ + if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */ + if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */ + if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ + if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */ + if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */ + if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE + if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE + if (a12 != *(_Decimal32 *)&sp->slot[3]) FAILURE + if (a13 != *(_Decimal32 *)&sp->slot[4]) FAILURE + if (a14 != *(_Decimal32 *)&sp->slot[5]) FAILURE + if (a15 != *(_Decimal32 *)&sp->slot[6]) FAILURE + if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE +} + +extern void func5_asm (_Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128); + +WRAPPER(func5); + +void __attribute__ ((noinline)) +func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */ + if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */ + if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ + if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */ + + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[6]) FAILURE + if (a9 != *(_Decimal128 *)&sp->slot[8]) FAILURE + if (a10 != *(_Decimal32 *)&sp->slot[12]) FAILURE + if (a11 != *(_Decimal64 *)&sp->slot[14]) FAILURE + if (a12 != *(_Decimal128 *)&sp->slot[16]) FAILURE +} + +int +main () +{ + func0_asm (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl); + func1_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl); + func2_asm (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd); + func3_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dl); + func4_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, + 515.2df, 516.2df); + func5_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); + + if (failcnt != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c new file mode 100644 index 000000000..8fcb7fd7f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c @@ -0,0 +1,364 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2" } */ +#include <stdarg.h> +#include <signal.h> +#include <stdio.h> + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. + Parameter passing of integral and floating point is tested. */ + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Testcase could break on future gcc's, if parameter regs + are changed before this asm. */ + +#ifndef __MACH__ +#define save_parms(lparms) \ + asm volatile ("ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ + "std 5,16(11)\n\t" \ + "std 6,24(11)\n\t" \ + "std 7,32(11)\n\t" \ + "std 8,40(11)\n\t" \ + "std 9,48(11)\n\t" \ + "std 10,56(11)\n\t" \ + "stfd 1,64(11)\n\t" \ + "stfd 2,72(11)\n\t" \ + "stfd 3,80(11)\n\t" \ + "stfd 4,88(11)\n\t" \ + "stfd 5,96(11)\n\t" \ + "stfd 6,104(11)\n\t" \ + "stfd 7,112(11)\n\t" \ + "stfd 8,120(11)\n\t" \ + "stfd 9,128(11)\n\t" \ + "stfd 10,136(11)\n\t" \ + "stfd 11,144(11)\n\t" \ + "stfd 12,152(11)\n\t" \ + "stfd 13,160(11)\n\t":::"11", "memory"); \ + lparms = gparms; +#else +#define save_parms(lparms) \ + asm volatile ("ld r11,gparms@got(r2)\n\t" \ + "std r3,0(r11)\n\t" \ + "std r4,8(r11)\n\t" \ + "std r5,16(r11)\n\t" \ + "std r6,24(r11)\n\t" \ + "std r7,32(r11)\n\t" \ + "std r8,40(r11)\n\t" \ + "std r9,48(r11)\n\t" \ + "std r10,56(r11)\n\t" \ + "stfd f1,64(r11)\n\t" \ + "stfd f2,72(r11)\n\t" \ + "stfd f3,80(r11)\n\t" \ + "stfd f4,88(r11)\n\t" \ + "stfd f5,96(r11)\n\t" \ + "stfd f6,104(r11)\n\t" \ + "stfd f7,112(r11)\n\t" \ + "stfd f8,120(r11)\n\t" \ + "stfd f9,128(r11)\n\t" \ + "stfd f10,136(r11)\n\t" \ + "stfd f11,144(r11)\n\t" \ + "stfd f12,152(r11)\n\t" \ + "stfd f13,160(r11)\n\t":::"r11", "memory"); \ + lparms = gparms; +#endif + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 1 +*/ +void __attribute__ ((noinline)) fcld (char *s, long l, double d) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldi (char *s, long l, double d, signed int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); + + if ((signed long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldu (char *s, long l, float d, unsigned int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if ((double) d != lparms.fprs[0]) + abort (); + + if ((unsigned long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : slot 1 + d : slot 2 +*/ + +void __attribute__ ((noinline)) fceld (char *s, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort (); + + l = va_arg (arg, long); + d = va_arg (arg, double); + + /* Go back one frame. */ + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[1].l != l) + abort (); + + if (sp->slot[2].d != d) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + d : slot 3 + l : slot 4 +*/ +void __attribute__ ((noinline)) fciiedl (char *s, int i, int j, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if ((long) i != lparms.gprs[1]) + abort (); + + if ((long) j != lparms.gprs[2]) + abort (); + + d = va_arg (arg, double); + l = va_arg (arg, long); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[3].d != d) + abort (); + + if (sp->slot[4].l != l) + abort (); +} + +/* +Parameter Register Offset in parameter save area +c r3 0-7 (not stored in parameter save area) +ff f1 8-15 (not stored) +d r5 16-23 (not stored) +ld f2 24-31 (not stored) +f r7 32-39 (not stored) +s r8,r9 40-55 (not stored) +gg f3 56-63 (not stored) +t (none) 64-79 (stored in parameter save area) +e (none) 80-87 (stored) +hh f4 88-95 (stored) + +*/ + +typedef struct +{ + int a; + double dd; +} sparm; + +typedef union +{ + int i[2]; + long l; + double d; +} double_t; + +/* Example from ABI documentation with slight changes. + Paramter passing. + c : gpr 3 + ff : fpr 1 + d : gpr 5 + ld : fpr 2 + f : gpr 7 + s : gpr 8 - 9 + gg : fpr 3 + t : save area offset 64 - 79 + e : save area offset 80 - 88 + hh : fpr 4 +*/ + +void __attribute__ ((noinline)) +fididisdsid (int c, double ff, int d, double ld, int f, + sparm s, double gg, sparm t, int e, double hh) +{ + stack_frame_t *sp; + reg_parms_t lparms; + double_t dx, dy; + + save_parms (lparms); + + /* Parm 0: int. */ + if ((long) c != lparms.gprs[0]) + abort (); + + /* Parm 1: double. */ + if (ff != lparms.fprs[0]) + abort (); + + /* Parm 2: int. */ + if ((long) d != lparms.gprs[2]) + abort (); + + /* Parm 3: double. */ + if (ld != lparms.fprs[1]) + abort (); + + /* Parm 4: int. */ + if ((long) f != lparms.gprs[4]) + abort (); + + /* Parm 5: struct sparm. */ + dx.l = lparms.gprs[5]; + dy.l = lparms.gprs[6]; + + if (s.a != dx.i[0]) + abort (); + if (s.dd != dy.d) + abort (); + + /* Parm 6: double. */ + if (gg != lparms.fprs[2]) + abort (); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* Parm 7: struct sparm. */ + dx.l = sp->slot[8].l; + dy.l = sp->slot[9].l; + if (t.a != dx.i[0]) + abort (); + if (t.dd != dy.d) + abort (); + + /* Parm 8: int. */ + if (e != sp->slot[10].l) + abort (); + + /* Parm 9: double. */ + + if (hh != lparms.fprs[3]) + abort (); +} + +int +main () +{ + char *s = "ii"; + + fcld (s, 1, 1.0); + fcldi (s, 1, 1.0, -2); + fcldu (s, 1, 1.0, 2); + fceld (s, 1, 1.0); + fciiedl (s, 1, 2, 1.0, 3); + fididisdsid (1, 1.0, 2, 2.0, -1, (sparm) + { + 3, 3.0}, 4.0, (sparm) + { + 5, 5.0}, 6, 7.0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c new file mode 100644 index 000000000..a9883d9e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c @@ -0,0 +1,403 @@ +/* { dg-do run { target { { powerpc*-*-linux* && lp64 } && powerpc_altivec_ok } } } */ +/* { dg-options "-O2 -fprofile -mprofile-kernel -maltivec -mabi=altivec" } */ +#include <stdarg.h> +#include <signal.h> +#include <altivec.h> +#include <stdlib.h> + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +void __attribute__((no_instrument_function)) +sig_ill_handler (int sig) +{ + exit(0); +} + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; + long pad; + vector int vrs[12]; +} reg_parms_t; + +reg_parms_t gparms; + +/* _mcount call is done on Linux ppc64 early in the prologue. + my_mcount will provide a entry point _mcount, + which will save all register to gparms. + Note that _mcount need to restore lr to original value, + therefor use ctr to return. +*/ + +void __attribute__((no_instrument_function)) +my_mcount() +{ + asm volatile (".type _mcount,@function\n\t" + ".globl _mcount\n\t" + "_mcount:\n\t" + "mflr 0\n\t" + "mtctr 0\n\t" + "ld 0,16(1)\n\t" + "mtlr 0\n\t" + "ld 11,gparms@got(2)\n\t" + "std 3,0(11)\n\t" + "std 4,8(11)\n\t" + "std 5,16(11)\n\t" + "std 6,24(11)\n\t" + "std 7,32(11)\n\t" + "std 8,40(11)\n\t" + "std 9,48(11)\n\t" + "std 10,56(11)\n\t" + "stfd 1,64(11)\n\t" + "stfd 2,72(11)\n\t" + "stfd 3,80(11)\n\t" + "stfd 4,88(11)\n\t" + "stfd 5,96(11)\n\t" + "stfd 6,104(11)\n\t" + "stfd 7,112(11)\n\t" + "stfd 8,120(11)\n\t" + "stfd 9,128(11)\n\t" + "stfd 10,136(11)\n\t" + "stfd 11,144(11)\n\t" + "stfd 12,152(11)\n\t" + "stfd 13,160(11)\n\t" + "li 3,176\n\t" + "stvx 2,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 3,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 4,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 5,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 6,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 7,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 8,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 9,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 10,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 11,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 12,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 13,3,11\n\t" + "ld 3,0(11)\n\t" + "bctr"); +} + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + +typedef union +{ + unsigned int i[4]; + unsigned long l[2]; + vector int v; +} vector_int_t; + +/* Paramter passing. + s : gpr 3 + v : vpr 2 + i : gpr 7 +*/ +void __attribute__ ((noinline)) +fcvi (char *s, vector int v, int i) +{ + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if ((long) i != lparms.gprs[4]) + abort(); +} +/* Paramter passing. + s : gpr 3 + v : vpr 2 + w : vpr 3 +*/ + +void __attribute__ ((noinline)) +fcvv (char *s, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + v : vpr 2 + w : vpr 3 +*/ +void __attribute__ ((noinline)) +fcivv (char *s, int i, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + v : slot 2-3 + w : slot 4-5 +*/ + +void __attribute__ ((noinline)) +fcevv (char *s, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + /* Go back one frame. */ + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[2].l != 0x100000002ULL + || sp->slot[4].l != 0x500000006ULL) + abort(); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + v : slot 4-5 + w : slot 6-7 +*/ +void __attribute__ ((noinline)) +fciievv (char *s, int i, int j, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if ((long) j != lparms.gprs[2]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +void __attribute__ ((noinline)) +fcvevv (char *s, vector int x, ...) +{ + vector int a, c = {7, 10, 13, 16}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, x); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + + a = vec_add (v,w); + a = vec_add (a, x); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +int __attribute__((no_instrument_function, noinline)) +main1() +{ + char *s = "vv"; + vector int v = {1, 2, 3, 4}; + vector int w = {5, 6, 7, 8}; + + fcvi (s, v, 2); + fcvv (s, v, w); + fcivv (s, 1, v, w); + fcevv (s, v, w); + fciievv (s, 1, 2, v, w); + fcvevv (s, v, v, w); + return 0; +} + +int __attribute__((no_instrument_function)) +main() +{ + /* Exit on systems without altivec. */ + signal (SIGILL, sig_ill_handler); + /* Altivec instruction, 'vor %v0,%v0,%v0'. */ + asm volatile (".long 0x10000484"); + signal (SIGILL, SIG_DFL); + + return main1 (); +} + +/* Paramter passing. + Function called with no prototype. + s : gpr 3 + v : vpr 2 gpr 5-6 + w : vpr 3 gpr 7-8 + x : vpr 4 gpr 9-10 + y : vpr 5 slot 8-9 +*/ +void +fnp_cvvvv (char *s, vector int v, vector int w, + vector int x, vector int y) +{ + vector int a, c = {12, 16, 20, 24}; + reg_parms_t lparms = gparms; + stack_frame_t *sp; + vector_int_t v0, v1, v2, v3; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + if (!vec_all_eq (x, lparms.vrs[2])) + abort (); + + if (!vec_all_eq (y, lparms.vrs[3])) + abort (); + + a = vec_add (v,w); + a = vec_add (a,x); + a = vec_add (a,y); + + if (!vec_all_eq (a, c)) + abort (); + + v0.v = lparms.vrs[0]; + v1.v = lparms.vrs[1]; + v2.v = lparms.vrs[2]; + v3.v = lparms.vrs[3]; + + if (v0.l[0] != lparms.gprs[2]) + abort (); + + if (v0.l[1] != lparms.gprs[3]) + abort (); + + if (v1.l[0] != lparms.gprs[4]) + abort (); + + if (v1.l[1] != lparms.gprs[5]) + abort (); + + if (v2.l[0] != lparms.gprs[6]) + abort (); + + if (v2.l[1] != lparms.gprs[7]) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[8].l != v3.l[0]) + abort (); + + if (sp->slot[9].l != v3.l[1]) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c new file mode 100644 index 000000000..8c78c9e2b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-options "-Wall" } */ +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +typedef int __attribute__((vector_size(16))) v4si; +typedef int __attribute__((vector_size(8))) v2si; + +v4si +f(v4si v) +{ /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + return v; +} + +v2si +g(v2si v) +{ + return v; +} + +int +main() +{ + v4si v = { 1, 2, 3, 4 }; + v2si w = { 5, 6 }; + v = f (v); /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + w = g (w); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c new file mode 100644 index 000000000..eb54a653b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c @@ -0,0 +1,331 @@ +/* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ELF ABI for decimal float values. */ + +extern void abort (void); +int failcnt = 0; + +/* Support compiling the test to report individual failures; default is + to abort as soon as a check fails. */ +#ifdef DBG +#include <stdio.h> +#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; } +#else +#define FAILURE abort (); +#endif + +typedef struct +{ + int pad; + _Decimal32 d; +} d32parm_t; + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Wrapper to save the GPRs and FPRs and then jump to the real function. */ +#define WRAPPER(NAME) \ +__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ + ".section \".opd\",\"aw\"\n\t" \ + ".align 3\n" \ + #NAME "_asm:\n\t" \ + ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \ + ".text\n\t" \ + ".type " #NAME "_asm, @function\n" \ + ".L." #NAME "_asm:\n\t" \ + "ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ + "std 5,16(11)\n\t" \ + "std 6,24(11)\n\t" \ + "std 7,32(11)\n\t" \ + "std 8,40(11)\n\t" \ + "std 9,48(11)\n\t" \ + "std 10,56(11)\n\t" \ + "stfd 1,64(11)\n\t" \ + "stfd 2,72(11)\n\t" \ + "stfd 3,80(11)\n\t" \ + "stfd 4,88(11)\n\t" \ + "stfd 5,96(11)\n\t" \ + "stfd 6,104(11)\n\t" \ + "stfd 7,112(11)\n\t" \ + "stfd 8,120(11)\n\t" \ + "stfd 9,128(11)\n\t" \ + "stfd 10,136(11)\n\t" \ + "stfd 11,144(11)\n\t" \ + "stfd 12,152(11)\n\t" \ + "stfd 13,160(11)\n\t" \ + "b " #NAME "\n\t" \ + ".long 0\n\t" \ + ".byte 0,0,0,0,0,0,0,0\n\t" \ + ".size " #NAME ",.-" #NAME "\n") + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + unsigned long slot[100]; +} stack_frame_t; + +extern void func0_asm (double, double, double, double, double, double, + double, double, double, double, double, double, + double, double, + _Decimal64, _Decimal128, _Decimal64); + +WRAPPER(func0); + +/* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ +void __attribute__ ((noinline)) +func0 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + double a13, double a14, + _Decimal64 a15, _Decimal128 a16, _Decimal64 a17) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != gparms.fprs[0]) FAILURE + if (a2 != gparms.fprs[1]) FAILURE + if (a3 != gparms.fprs[2]) FAILURE + if (a4 != gparms.fprs[3]) FAILURE + if (a5 != gparms.fprs[4]) FAILURE + if (a6 != gparms.fprs[5]) FAILURE + if (a7 != gparms.fprs[6]) FAILURE + if (a8 != gparms.fprs[7]) FAILURE + if (a9 != gparms.fprs[8]) FAILURE + if (a10 != gparms.fprs[9]) FAILURE + if (a11 != gparms.fprs[10]) FAILURE + if (a12 != gparms.fprs[11]) FAILURE + if (a13 != gparms.fprs[12]) FAILURE + if (a14 != *(double *)&sp->slot[13]) FAILURE + if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE + if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE + if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE +} + +extern void func1_asm (double, double, double, double, double, double, + double, double, double, double, double, double, + double, _Decimal128 ); + +WRAPPER(func1); + +void __attribute__ ((noinline)) +func1 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + double a13, _Decimal128 a14) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != gparms.fprs[0]) FAILURE + if (a2 != gparms.fprs[1]) FAILURE + if (a3 != gparms.fprs[2]) FAILURE + if (a4 != gparms.fprs[3]) FAILURE + if (a5 != gparms.fprs[4]) FAILURE + if (a6 != gparms.fprs[5]) FAILURE + if (a7 != gparms.fprs[6]) FAILURE + if (a8 != gparms.fprs[7]) FAILURE + if (a9 != gparms.fprs[8]) FAILURE + if (a10 != gparms.fprs[9]) FAILURE + if (a11 != gparms.fprs[10]) FAILURE + if (a12 != gparms.fprs[11]) FAILURE + if (a13 != gparms.fprs[12]) FAILURE + if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE +} + +extern void func2_asm (double, double, double, double, double, double, + double, double, double, double, double, double, + _Decimal128); + +WRAPPER(func2); + +void __attribute__ ((noinline)) +func2 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + _Decimal128 a13) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != gparms.fprs[0]) FAILURE + if (a2 != gparms.fprs[1]) FAILURE + if (a3 != gparms.fprs[2]) FAILURE + if (a4 != gparms.fprs[3]) FAILURE + if (a5 != gparms.fprs[4]) FAILURE + if (a6 != gparms.fprs[5]) FAILURE + if (a7 != gparms.fprs[6]) FAILURE + if (a8 != gparms.fprs[7]) FAILURE + if (a9 != gparms.fprs[8]) FAILURE + if (a10 != gparms.fprs[9]) FAILURE + if (a11 != gparms.fprs[10]) FAILURE + if (a12 != gparms.fprs[11]) FAILURE + if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE +} + +extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128, + _Decimal64, _Decimal128, _Decimal64, _Decimal128, + _Decimal64, _Decimal128); + +WRAPPER(func3); + +void __attribute__ ((noinline)) +func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8, + _Decimal64 a9, _Decimal128 a10) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a6 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */ + if (a7 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */ + if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE +} + +extern void func4_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64, + _Decimal128, _Decimal64, _Decimal128, _Decimal64); + +WRAPPER(func4); + +void __attribute__ ((noinline)) +func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */ + if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */ + if (a5 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */ + if (a6 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */ + if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE +} + +extern void func5_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32, + _Decimal32, _Decimal32, _Decimal32, _Decimal32); + +WRAPPER(func5); + +void __attribute__ ((noinline)) +func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR or parameter slot. */ + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */ + if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */ + if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */ + if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */ + if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ + if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */ + if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */ + if (a9 != ((d32parm_t *)&gparms.fprs[8])->d) FAILURE /* f9 */ + if (a10 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */ + if (a11 != ((d32parm_t *)&gparms.fprs[10])->d) FAILURE /* f11 */ + if (a12 != ((d32parm_t *)&gparms.fprs[11])->d) FAILURE /* f12 */ + if (a13 != ((d32parm_t *)&gparms.fprs[12])->d) FAILURE /* f13 */ + if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE + if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE + if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE +} + +extern void func6_asm (_Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128, + _Decimal32, _Decimal64, _Decimal128); + +WRAPPER(func6); + +void __attribute__ ((noinline)) +func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) +{ + stack_frame_t *sp; + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */ + if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */ + if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */ + if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */ + if (a6 != *(_Decimal128 *)&gparms.fprs[7]) FAILURE /* f8 & f9 */ + if (a7 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */ + if (a8 != *(_Decimal64 *)&gparms.fprs[10]) FAILURE /* f11 */ + if (a9 != *(_Decimal128 *)&gparms.fprs[11]) FAILURE /* f12 & f13 */ + if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE + if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE +} + +int +main (void) +{ + func0_asm (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5, + 14.5, 15.2dd, 16.2dl, 17.2dd); + func1_asm (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5, + 110.5, 111.5, 112.5, 113.5, 114.2dd); + func2_asm (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5, + 210.5, 211.5, 212.5, 213.2dd); + func3_asm (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd, + 308.2dl, 309.2dd, 310.2dl); + func4_asm (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl, + 408.2dd); +#if 0 + /* _Decimal32 doesn't yet follow the ABI; enable this when it does. */ + func5_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, + 515.2df, 516.2df); + func6_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); +#endif + + if (failcnt != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c new file mode 100644 index 000000000..f9d4dda9c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c @@ -0,0 +1,12 @@ +// { dg-do compile } +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +// { dg-options "-O2 -mpowerpc64" } +// { dg-final { scan-assembler-not "stfd" } } + +// The register allocator should have allocated the temporary long long value in a floating point register. + +double +d2ll2d (double d) +{ + return (double)(long long)d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c b/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c new file mode 100644 index 000000000..21090af23 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c @@ -0,0 +1,22 @@ +/* { dg-do link } */ +/* { dg-options "-mminimal-toc" { target { powerpc*-*-* && lp64 } } } */ + +char *strchr (const char *, int); + +int +foo (int a) +{ + int b; + + b = 0; + if ("/"[1] != '\0') + if (strchr ("/", a)) + b = 1; + return b; +} + +int +main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c b/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c new file mode 100644 index 000000000..8efaeaba3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c @@ -0,0 +1,43 @@ +/* { dg-do link { target { *-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-W -Wall -Wno-uninitialized -Wno-unused-but-set-variable -mcpu=cell" } */ +/* Test some PPU intrinsics from <ppu_intrinsics.h>. */ + +#include <ppu_intrinsics.h> + +int main () +{ + double d, d1, d2; + float f, f1, f2; + unsigned long long ull, a, b; + long long ll; + int i; + +#ifdef __powerpc64__ + ull = __rldcl (a, b, 3); + ull = __rldcr (a, b, 3); + ull = __rldic (a, 3, 4); + ull = __rldicl (a, 4, 5); + ull = __rldicr (a, 2, 3); + ull = __rldimi (a, b, 4, 6); +#endif + ull = __rlwimi (a, b, 6, 9, 12); + ull = __rlwnm (a, b, 3, 5); + d = __fmul (d1, d2); + f = __fmuls (f1, f2); + f = __frsp (f); + d = __fcfid (ll); + d = __frsqrte (d1); + ll = __fctid (d); + ll = __fctidz (d); + i = __fctiw (d); + i = __fctiwz (d); + + __protected_stream_count (1, 2); + __protected_stream_go (); + __protected_stream_set (1, 0x1000, 3); + __protected_stream_stop (3); + __protected_stream_stop_all (); + __protected_unlimited_stream_set (3, 0x1000, 1); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr16155.c b/gcc/testsuite/gcc.target/powerpc/pr16155.c new file mode 100644 index 000000000..fffe957dc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr16155.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -ansi" } */ + +/* PR 16155 + * Compilation of a simple altivec test program fails if the -ansi flag is + * given to gcc, when compiling with -maltivec. + */ + +#include <altivec.h> + +void foo(void) +{ + vector unsigned short a, b; + a = vec_splat(b, 0); +} + +/* { dg-bogus "parse error before \"typeof\"" "-maltivec -mansi" { target powerpc*-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr16286.c b/gcc/testsuite/gcc.target/powerpc/pr16286.c new file mode 100644 index 000000000..790b6409f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr16286.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* PR 16286 + Compilation of a simple Altivec test program fails if vector, pixel + and/or bool are #undefined when compiling with -maltivec. This may be + done for building C++ programs that use the STL <vector>. */ + +#include <altivec.h> +#undef vector +#undef pixel +#undef bool + +void test(void) +{ + __vector unsigned int a, b; + __vector __pixel v0; + __vector __bool v1; + + a = vec_and(a, b); + vec_step (b); +} + +/* { dg-bogus "(syntax|parse) error before \"vector\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"pixel\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"bool\"" "-maltivec" { target powerpc*-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr18096-1.c b/gcc/testsuite/gcc.target/powerpc/pr18096-1.c new file mode 100644 index 000000000..74612f393 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr18096-1.c @@ -0,0 +1,12 @@ +/* PR middle-end/18096 */ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-options "-O2" } */ + +void f(char*); + +void mkcatdefs(char *fname) /* { dg-error "too large" "stack frame too large" } */ +{ + char line [2147483647]; + f(line); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr25960.c b/gcc/testsuite/gcc.target/powerpc/pr25960.c new file mode 100644 index 000000000..9ab9a10a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr25960.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */ +/* { dg-options "-O2 -mlong-double-128" } */ + +extern void abort (void); + +volatile long double l, m, n; + +int +main (void) +{ + l = __builtin_copysignl (0.0L, -1.0L); + m = __builtin_copysignl (0.0L, -1.0L); + n = l + m; + if (__builtin_copysignl (1.0L, n) >= 0.0L) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr26350.c b/gcc/testsuite/gcc.target/powerpc/pr26350.c new file mode 100644 index 000000000..6b4b20627 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr26350.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */ +/* { dg-options "-O2 -mlong-double-128 -fpic" } */ + +typedef int int32_t __attribute__ ((__mode__ (__SI__))); +typedef unsigned char uint8_t; +typedef unsigned int uint32_t; +typedef struct REGS REGS; +typedef union { uint32_t F; } FW; +typedef union { struct { FW L; } F; } DW; +typedef struct _PSW { + DW ia; +} PSW; +struct REGS { + PSW psw; + DW cr[16]; +}; +struct ebfp { + long double v; +}; + +void s390_convert_fix32_to_bfp_ext_reg (REGS *regs) +{ + struct ebfp op1; + int32_t op2; + ((regs))->psw.ia.F.L.F += (4); + if(!((regs)->cr[(0)].F.L.F & 0x00040000)) + op1.v = (long double)op2; + put_ebfp(&op1); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr27158.c b/gcc/testsuite/gcc.target/powerpc/pr27158.c new file mode 100644 index 000000000..5476577a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr27158.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ +#define REGLIST \ + "77", "78", "79", "80", "81", "82", "83", "84", "85", "86",\ + "87", "88", "89", "90", "91", "92", "93", "94", "95", "96",\ + "97", "98", "99", "100", "101", "102", "103", "104", "105", "106",\ + "107", "108" + +typedef __attribute__ ((vector_size (16))) float v4sf; + +void +foo (int H) +{ + volatile v4sf tmp; + while (H-- > 0) + { + asm ("" : : : REGLIST); + tmp = (v4sf) __builtin_altivec_vspltisw (1); + } +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr35907.c b/gcc/testsuite/gcc.target/powerpc/pr35907.c new file mode 100644 index 000000000..7d5465ea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr35907.c @@ -0,0 +1,57 @@ +/* PR target/35907 */ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +#define vector __attribute__((vector_size (16))) +union +{ + vector int k; + int c[16]; +} u, v, w; +vector int m; + +void __attribute__((noinline)) +bar (void *i, vector int j) +{ + asm volatile ("" : : "r" (i), "r" (&j) : "memory"); +} + +int __attribute__((noinline)) +foo (int i, vector int j) +{ + char *p = __builtin_alloca (64 + i); + m += u.k; + v.k = m; + w.k = j; + if (__builtin_memcmp (&v.c, &w.c, 16) != 0) + __builtin_abort (); + j += u.k; + bar (p, j); + j += u.k; + bar (p, j); + return 0; +} + +void +test (void) +{ + vector int l; + int i; + for (i = 0; i < 4; i++) + u.c[i] = i; + l = u.k; + if (foo (64, l)) + __builtin_abort (); + l += u.k; + if (foo (64, l)) + __builtin_abort (); +} + +int +main () +{ + test (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr37168.c b/gcc/testsuite/gcc.target/powerpc/pr37168.c new file mode 100644 index 000000000..8d35157d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr37168.c @@ -0,0 +1,14 @@ +/* PR target/37168 */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +#define C 3.68249351546114573519399405666776E-44f +#define vector __attribute__ ((altivec (vector__))) + +vector float +foo (vector float a) +{ + vector float b = __builtin_vec_madd (b, a, (vector float) { C, C, C, C }); + return b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr39457.c b/gcc/testsuite/gcc.target/powerpc/pr39457.c new file mode 100644 index 000000000..c4828bbb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr39457.c @@ -0,0 +1,56 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2 -mminimal-toc" } */ + +/* PR 39457 -- fix breakage because the compiler ran out of registers and + wanted to stash a floating point value to the LR/CTR register. */ + +/* -O2 -m64 -mminimal-toc */ +typedef struct { void *s; } S; +typedef void (*T1) (void); +typedef void (*T2) (void *, void *, int, void *); +char *fn1 (const char *, ...); +void *fn2 (void); +int fn3 (char *, int); +int fn4 (const void *); +int fn5 (const void *); +long fn6 (void) __attribute__ ((__const__)); +int fn7 (void *, void *, void *); +void *fn8 (void *, long); +void *fn9 (void *, long, const char *, ...); +void *fn10 (void *); +long fn11 (void) __attribute__ ((__const__)); +long fn12 (void *, const char *, T1, T2, void *); +void *fn13 (void *); +long fn14 (void) __attribute__ ((__const__)); +extern void *v1; +extern char *v2; +extern int v3; + +void +foo (void *x, char *z) +{ + void *i1, *i2; + int y; + if (v1) + return; + v1 = fn9 (fn10 (fn2 ()), fn6 (), "x", 0., "y", 0., 0); + y = 520 - (520 - fn4 (x)) / 2; + fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", fn8 (v1, fn14 ()), "x", 18.0, + "y", 16.0, "wid", 80.0, "hi", 500.0, 0); + fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 80.0, "y2", + 500.0, "f", fn3 ("fff", 0x0D0DFA00), 0); + fn13 (((S *) fn8 (v1, fn6 ()))->s); + fn12 (fn8 (v1, fn11 ()), "ev", (T1) fn7, 0, fn8 (v1, fn6 ())); + fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", + fn8 (v1, fn14 ()), "x", 111.0, "y", 14.0, "wid", 774.0, "hi", + 500.0, 0); + v1 = fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 774.0, "y2", + 500.0, "f", fn3 ("gc", 0x0D0DFA00), 0); + fn1 (z, 0); + i1 = fn9 (fn8 (v1, fn6 ()), fn6 (), "pixbuf", x, "x", + 800 - fn5 (x) / 2, "y", y - fn4 (x), 0); + fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, "/ok/"); + fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, 0); + i2 = fn9 (fn8 (v1, fn6 ()), fn6 (), "txt", "OK", "fnt", v2, "x", + 800, "y", y - fn4 (x) + 15, "ar", 0, "f", v3, 0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr39902-2.c b/gcc/testsuite/gcc.target/powerpc/pr39902-2.c new file mode 100644 index 000000000..463a36c1b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr39902-2.c @@ -0,0 +1,28 @@ +/* Check that simplification "x*(-1)" -> "-x" is not performed for decimal + float types. */ + +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -O -mcpu=power6" } */ +/* { dg-final { scan-assembler-not "fneg" } } */ + +extern _Decimal32 a32, b32; +extern _Decimal64 a64, b64; +extern _Decimal128 a128, b128; + +void +foo32 (void) +{ + b32 = a32 * -1.0DF; +} + +void +foo64 (void) +{ + b64 = a64 * -1.0DD; +} + +void +foo128 (void) +{ + b128 = a128 * -1.0DL; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr41175.c b/gcc/testsuite/gcc.target/powerpc/pr41175.c new file mode 100644 index 000000000..2f0137962 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr41175.c @@ -0,0 +1,461 @@ +/* PR target/41175 */ +/* { dg-do run } */ +/* { dg-options "-Os" } */ + +#define X2(n) X1(n##0) X1(n##1) +#define X4(n) X2(n##0) X2(n##1) +#define X8(n) X4(n##0) X4(n##1) + +#ifndef __SPE__ +#define FLOAT_REG_CONSTRAINT "f" +#else +#define FLOAT_REG_CONSTRAINT "r" +#endif + +volatile int ll; + +__attribute__((noinline)) void +foo (void) +{ + asm volatile ("" : : : "memory"); +} + +__attribute__((noinline)) void +bar (char *p) +{ + asm volatile ("" : : "r" (p) : "memory"); +} + +__attribute__((noinline)) void +f1 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f2 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f3 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +#ifndef __NO_FPRS__ +__attribute__((noinline)) void +f4 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f5 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f6 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f7 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f8 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f9 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f10 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f11 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f12 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f13 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f14 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f15 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} +#endif + +int +main () +{ + ll = 60; + f1 (); + f2 (); + f3 (); +#ifndef __NO_FPRS__ + f4 (); + f5 (); + f6 (); + f7 (); + f8 (); + f9 (); + f10 (); + f11 (); + f12 (); + f13 (); + f14 (); + f15 (); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr42747.c b/gcc/testsuite/gcc.target/powerpc/pr42747.c new file mode 100644 index 000000000..9e7310e17 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr42747.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ + +double foo (double x) { return __builtin_sqrt (x); } + +/* { dg-final { scan-assembler "xssqrtdp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr43154.c b/gcc/testsuite/gcc.target/powerpc/pr43154.c new file mode 100644 index 000000000..d083e977b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr43154.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* Make sure that vec_mergel and vec_mergeh are supported for V2DF/V2DI types. */ +/* { dg-final { scan-assembler-times "xxpermdi" 4 } } */ + +#include <altivec.h> + +void vec_high_v2df (vector double *a, vector double *b, vector double *c) +{ + *a = vec_mergeh (*b, *c); +} + +void vec_low_v2df (vector double *a, vector double *b, vector double *c) +{ + *a = vec_mergel (*b, *c); +} + +void vec_high_v2di (vector long long *a, vector long long *b, vector long long *c) +{ + *a = vec_mergeh (*b, *c); +} + +void vec_low_v2di (vector long long *a, vector long long *b, vector long long *c) +{ + *a = vec_mergel (*b, *c); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr47251.c b/gcc/testsuite/gcc.target/powerpc/pr47251.c new file mode 100644 index 000000000..6cb9f492e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr47251.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -msoft-float -mcpu=power7" } */ + +/* PR 47151: libgcc fails to build when using --with-cpu=power7 due to a missed + TARGET_HARD_FLOAT test. */ +unsigned long long +func (float a) +{ + const float dfa = a; + const unsigned int hi = dfa / 0x1p32f; + const unsigned int lo = dfa - (float) hi * 0x1p32f; + return ((unsigned long long) hi << (4 * 8)) | lo; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755-2.c b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c new file mode 100644 index 000000000..2180efdbe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c @@ -0,0 +1,134 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7" } */ + +/* PR 47755: Make sure compiler generates correct code for various + V2DI constants. */ + +#ifdef DEBUG +#include <stdio.h> + +static int num_errors; +#define FAIL_LL(A, B) \ + (num_errors++, printf ("Fail (%i, %i)\n", (int)(A), (int)(B))) +#define FAIL_I(A, B, C, D) \ + (num_errors++, \ + printf ("Fail (%i, %i, %i, %i)\n", (int)(A), (int)(B), (int)(C), (int)(D))) + +#else +extern void abort (void) __attribute__((__noreturn__)); +#define FAIL_LL(A, B) abort () +#define FAIL_I(A, B, C, D) abort () +#endif + +static test_ll (vector long long, long long, long long) __attribute__((__noinline__)); + +static +test_ll (vector long long v, long long a, long long b) +{ + union { + vector long long v; + long long ll[2]; + } u; + + u.v = v; + if (u.ll[0] != a && u.ll[1] != b) + FAIL_LL (a, b); +} + +#define TEST_LL(A,B) test_ll ((vector long long){ (A), (B) }, (A), (B)) + +static test_i (vector int, int, int, int, int) __attribute__((__noinline__)); + +static +test_i (vector int v, int a, int b, int c, int d) +{ + union { + vector int v; + int i[4]; + } u; + + u.v = v; + if (u.i[0] != a && u.i[1] != b && u.i[2] != c && u.i[3] != d) + FAIL_I (a, b, c, d); +} + +#define TEST_I(A,B,C,D) \ + test_i ((vector int){ (A), (B), (C), (D) }, (A), (B), (C), (D)) + +int +main (void) +{ + TEST_LL (-2LL, -2LL); + TEST_LL (-2LL, -1LL); + TEST_LL (-2LL, 0LL); + TEST_LL (-2LL, 1LL); + TEST_LL (-2LL, 2LL); + + TEST_LL (-1LL, -2LL); + TEST_LL (-1LL, -1LL); + TEST_LL (-1LL, 0LL); + TEST_LL (-1LL, 1LL); + TEST_LL (-1LL, 2LL); + + TEST_LL (0LL, -2LL); + TEST_LL (0LL, -1LL); + TEST_LL (0LL, 0LL); + TEST_LL (0LL, 1LL); + TEST_LL (0LL, 2LL); + + TEST_LL (1LL, -2LL); + TEST_LL (1LL, -1LL); + TEST_LL (1LL, 0LL); + TEST_LL (1LL, 1LL); + TEST_LL (1LL, 2LL); + + TEST_LL (2LL, -2LL); + TEST_LL (2LL, -1LL); + TEST_LL (2LL, 0LL); + TEST_LL (2LL, 1LL); + TEST_LL (2LL, 2LL); + + /* We could use VSPLTI instructions for these tests. */ + TEST_LL (0x0101010101010101LL, 0x0101010101010101LL); + TEST_LL (0x0001000100010001LL, 0x0001000100010001LL); + TEST_LL (0x0000000100000001LL, 0x0000000100000001LL); + + TEST_LL (0x0404040404040404LL, 0x0404040404040404LL); + TEST_LL (0x0004000400040004LL, 0x0004000400040004LL); + TEST_LL (0x0000000400000004LL, 0x0000000400000004LL); + + TEST_LL (0xf8f8f8f8f8f8f8f8LL, 0xf8f8f8f8f8f8f8f8LL); + TEST_LL (0xfff8fff8fff8fff8LL, 0xfff8fff8fff8fff8LL); + TEST_LL (0xfffffff8fffffff8LL, 0xfffffff8fffffff8LL); + + /* We could use VSPLTI instructions for these tests. */ + TEST_I (-2, -2, -2, -2); + TEST_I (-1, -1, -1, -1); + TEST_I ( 0, 0, 0, 0); + TEST_I ( 1, 1, 1, 1); + TEST_I ( 2, 2, 2, 2); + + TEST_I (0x01010101, 0x01010101, 0x01010101, 0x01010101); + TEST_I (0x00010001, 0x00010001, 0x00010001, 0x00010001); + + TEST_I (0x02020202, 0x02020202, 0x02020202, 0x02020202); + TEST_I (0x00020002, 0x00020002, 0x00020002, 0x00020002); + + TEST_I (0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8); + TEST_I (0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8); + + /* non-easy constants. */ + TEST_I (-2, -1, 0, 1); + TEST_I ( 1, 0, -1, -2); + + TEST_I (-1, -1, 0, 0); + TEST_I ( 0, 0, -1, -1); + +#ifdef DEBUG + printf ("%d error%s\n", num_errors, (num_errors == 1) ? "" : "s"); +#endif + + return 0; +}; diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755.c b/gcc/testsuite/gcc.target/powerpc/pr47755.c new file mode 100644 index 000000000..6dbd1fe02 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr47755.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxlxor" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ + +/* PR 47755: Compiler loads vector constant of 0 from TOC instead of using + xxlxor. */ +void +func (vector long long *p) +{ + *p = (vector long long) { 0LL, 0LL }; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr47862.c b/gcc/testsuite/gcc.target/powerpc/pr47862.c new file mode 100644 index 000000000..528cace38 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr47862.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-not "stfd" } } */ + +/* PR 47862: Verify caller-save spill of vectors in FP regs do not use + legacy FP insns, which spill only half the vector. */ +extern vector double dd[15]; + +vector double foo() { + vector double a,b,c,d,e,f,g,h,i,j,k,l,m,n; + + a=dd[1]; b=dd[2]; c=dd[3]; d=dd[4]; e=dd[5]; f=dd[6]; g=dd[7]; h=dd[8]; i=dd[9]; + j=dd[10]; k=dd[11]; l=dd[12]; m=dd[13]; n=dd[14]; + bar(); + return (a+b+c+d+e+f+g+h+i+j+k+l+m+n); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr48053-1.c b/gcc/testsuite/gcc.target/powerpc/pr48053-1.c new file mode 100644 index 000000000..fd7cd3d9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48053-1.c @@ -0,0 +1,30 @@ +/* Test for ICE arising from VSX code generation. */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mcpu=power7 -funroll-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +int sourcenode; +int ARCHelems; +int *source_elms; +void +foo (int argc, char **argv) +{ + int i, j; + int cor[4]; + double Ke[12][12], Me[12], Ce[12], Mexv[12], Cexv[12], v[12]; + for (i = 0; i < ARCHelems; i++) + { + for (j = 0; j < 12; j++) + Me[j] = 0.0; + if (cor[j] == sourcenode) + vv12x12 (Me, v, Mexv); + vv12x12 (Ce, v, Cexv); + if (source_elms[i] == 3) + for (j = 0; j < 12; j++) + { + v[j] = -v[j]; + Mexv[j] = -Mexv[j]; + Cexv[j] = -Cexv[j]; + } + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr48053-2.c b/gcc/testsuite/gcc.target/powerpc/pr48053-2.c new file mode 100644 index 000000000..2cdec6a68 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48053-2.c @@ -0,0 +1,38 @@ +/* Test for ICE arising from VSX code generation. */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mcpu=power7" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +struct timeval +{ + long tv_sec; + long tv_usec; +}; + +extern char *bar (struct timeval *); +int *error; + +void +foo (void *ptr) +{ + struct timeval tm; + long n1, n2; + + if (!ptr) + { + *error = 1; + n1 = -1; + n2 = -1; + } + else + { + n1 = 0; + n2 = *error; + } + + tm.tv_sec = n1; + tm.tv_usec = n2; + + if (*error) + bar (&tm); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr48192.c b/gcc/testsuite/gcc.target/powerpc/pr48192.c new file mode 100644 index 000000000..515926085 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48192.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -std=gnu89" } */ + +/* Make sure that the conditional macros vector, bool, and pixel are not + considered as being defined. */ + +#ifdef bool +#error "bool is considered defined" +#endif + +#ifdef vector +#error "vector is considered defined" +#endif + +#ifdef pixel +#error "pixel is condsidered defined" +#endif + +#if defined(bool) +#error "bool is considered defined" +#endif + +#if defined(vector) +#error "vector is considered defined" +#endif + +#if defined(pixel) +#error "pixel is condsidered defined" +#endif + +#ifndef bool +#else +#error "bool is considered defined" +#endif + +#ifndef vector +#else +#error "vector is considered defined" +#endif + +#ifndef pixel +#else +#error "pixel is condsidered defined" +#endif + +#define bool long double +bool pixel = 0; diff --git a/gcc/testsuite/gcc.target/powerpc/pr48857.c b/gcc/testsuite/gcc.target/powerpc/pr48857.c new file mode 100644 index 000000000..e8201c037 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr48857.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -mabi=altivec" } */ +/* { dg-final { scan-assembler-times "lxvd2x" 1 } } */ +/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */ +/* { dg-final { scan-assembler-not "ld" } } */ +/* { dg-final { scan-assembler-not "lwz" } } */ +/* { dg-final { scan-assembler-not "stw" } } */ +/* { dg-final { scan-assembler-not "addi" } } */ + +typedef vector long long v2di_type; + +v2di_type +return_v2di (v2di_type *ptr) +{ + return *ptr; /* should generate lxvd2x 34,0,3. */ +} + +void +pass_v2di (v2di_type arg, v2di_type *ptr) +{ + *ptr = arg; /* should generate stxvd2x 34,0,{3,5}. */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr51623.c b/gcc/testsuite/gcc.target/powerpc/pr51623.c new file mode 100644 index 000000000..37b7d6557 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr51623.c @@ -0,0 +1,123 @@ +/* PR target/51623 */ +/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */ +/* { dg-options "-mrelocatable -ffreestanding" } */ + +/* This generated an error, since the compiler was calling + unlikely_text_section_p in a context where it wasn't valid. */ + +typedef long long loff_t; +typedef unsigned size_t; + + +struct mtd_info { + unsigned writesize; + unsigned oobsize; + const char *name; +}; + +extern int strcmp(const char *,const char *); +extern char * strchr(const char *,int); + +struct cmd_tbl_s { + char *name; +}; + + +int printf(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2))); +void* malloc(size_t); +void free(void*); + + +extern int nand_curr_device; +extern struct mtd_info nand_info[]; + +static int nand_dump(struct mtd_info *nand, unsigned long off, int only_oob) +{ + int i; + unsigned char *datbuf, *oobbuf, *p; + + datbuf = malloc(nand->writesize + nand->oobsize); + oobbuf = malloc(nand->oobsize); + off &= ~(nand->writesize - 1); + + printf("Page %08lx dump:\n", off); + i = nand->writesize >> 4; + p = datbuf; + + while (i--) { + if (!only_oob) + printf("\t%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], + p[8], p[9], p[10], p[11], p[12], p[13], p[14], + p[15]); + p += 16; + } + + i = nand->oobsize >> 3; + free(datbuf); + free(oobbuf); + + return 0; +} + +int do_nand(struct cmd_tbl_s * cmdtp, int flag, int argc, char *argv[]) +{ + int dev; + unsigned long off; + char *cmd, *s; + struct mtd_info *nand; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "info") == 0) { + putc('\n'); + return 0; + } + + if (strcmp(cmd, "device") == 0) { + if (argc < 3) { + putc('\n'); + } + dev = (int)simple_strtoul(argv[2], ((void *)0), 10); + nand_curr_device = dev; + return 0; + } + + if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 ) + goto usage; + + if (nand_curr_device < 0 ) { + return 1; + } + nand = &nand_info[nand_curr_device]; + + if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) { + int clean = argc > 2 && !strcmp("clean", argv[2]); + int scrub = !strcmp(cmd, "scrub"); + return 0; + } + + if (strncmp(cmd, "dump", 4) == 0) { + if (argc < 3) + goto usage; + + s = strchr(cmd, '.'); + off = (int)simple_strtoul(argv[2], ((void *)0), 16); + + if (s != ((void *)0) && strcmp(s, ".oob") == 0) + nand_dump(nand, off, 1); + else + nand_dump(nand, off, 0); + + return 0; + } +usage: + cmd_usage(cmdtp); + return 1; +} + +void *ptr = do_nand; diff --git a/gcc/testsuite/gcc.target/powerpc/pr52199.c b/gcc/testsuite/gcc.target/powerpc/pr52199.c new file mode 100644 index 000000000..e22319388 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52199.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7 -fmerge-all-constants" } */ + +struct locale_time_t +{ + const char *abday[7]; + const unsigned int *wabday[7]; +}; + +static const unsigned int empty_wstr[1] = { 0 }; + +void +time_read (struct locale_time_t *time) +{ + int cnt; + + for (cnt=0; cnt < 7; cnt++) + { + time->abday[cnt] = ""; + time->wabday[cnt] = empty_wstr; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr52457.c b/gcc/testsuite/gcc.target/powerpc/pr52457.c new file mode 100644 index 000000000..4470e5502 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52457.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target vsx_hw } */ +/* { dg-options "-O1 -mcpu=power7" } */ + +extern void abort (void); + +typedef long long T; +typedef T vl_t __attribute__((vector_size(2 * sizeof (T)))); + +vl_t +buggy_func (T x) +{ + vl_t w; + T *p = (T *)&w; + p[0] = p[1] = x; + return w; +} + +int +main(void) +{ + vl_t rval; + T *pl; + + pl = (T *) &rval; + rval = buggy_func (2); + + if (pl[0] != 2 || pl[1] != 2) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr52775.c b/gcc/testsuite/gcc.target/powerpc/pr52775.c new file mode 100644 index 000000000..4027819ee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52775.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O1 -mcpu=power4" } */ +/* { dg-final { scan-assembler-times "fcfid" 2 } } */ + +double +int_to_double (int *p) +{ + return (double)*p; +} + +double +long_long_to_double (long long *p) +{ + return (double)*p; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr53199.c b/gcc/testsuite/gcc.target/powerpc/pr53199.c new file mode 100644 index 000000000..89a0cad06 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr53199.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power6 -mavoid-indexed-addresses" } */ +/* { dg-final { scan-assembler-times "lwbrx" 6 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 6 } } */ + +/* PR 51399: bswap gets an error if -mavoid-indexed-addresses was used in + creating the two lwbrx instructions. */ + +long long +load64_reverse_1 (long long *p) +{ + return __builtin_bswap64 (*p); +} + +long long +load64_reverse_2 (long long *p) +{ + return __builtin_bswap64 (p[1]); +} + +long long +load64_reverse_3 (long long *p, int i) +{ + return __builtin_bswap64 (p[i]); +} + +void +store64_reverse_1 (long long *p, long long x) +{ + *p = __builtin_bswap64 (x); +} + +void +store64_reverse_2 (long long *p, long long x) +{ + p[1] = __builtin_bswap64 (x); +} + +void +store64_reverse_3 (long long *p, long long x, int i) +{ + p[i] = __builtin_bswap64 (x); +} + +long long +reg_reverse (long long x) +{ + return __builtin_bswap64 (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-1.c b/gcc/testsuite/gcc.target/powerpc/recip-1.c new file mode 100644 index 000000000..590881bb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */ +/* { dg-final { scan-assembler-times "frsqrte" 2 } } */ +/* { dg-final { scan-assembler-times "fmsub" 2 } } */ +/* { dg-final { scan-assembler-times "fmul" 8 } } */ +/* { dg-final { scan-assembler-times "fnmsub" 4 } } */ + +double +rsqrt_d (double a) +{ + return 1.0 / __builtin_sqrt (a); +} + +float +rsqrt_f (float a) +{ + return 1.0f / __builtin_sqrtf (a); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-2.c b/gcc/testsuite/gcc.target/powerpc/recip-2.c new file mode 100644 index 000000000..3e64c0757 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power5" } */ +/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "fmuls" 6 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 3 } } */ +/* { dg-final { scan-assembler-times "fsqrt" 1 } } */ + +/* power5 resqrte is not accurate enough, and should not be generated by + default for -mrecip. */ +double +rsqrt_d (double a) +{ + return 1.0 / __builtin_sqrt (a); +} + +float +rsqrt_f (float a) +{ + return 1.0f / __builtin_sqrtf (a); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-3.c b/gcc/testsuite/gcc.target/powerpc/recip-3.c new file mode 100644 index 000000000..c5ce539bb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */ +/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */ +/* { dg-final { scan-assembler-times "xsrsqrtedp" 1 } } */ +/* { dg-final { scan-assembler-times "xsmsub.dp" 1 } } */ +/* { dg-final { scan-assembler-times "xsmuldp" 4 } } */ +/* { dg-final { scan-assembler-times "xsnmsub.dp" 2 } } */ +/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */ +/* { dg-final { scan-assembler-times "fmsubs" 1 } } */ +/* { dg-final { scan-assembler-times "fmuls" 4 } } */ +/* { dg-final { scan-assembler-times "fnmsubs" 2 } } */ + +double +rsqrt_d (double a) +{ + return 1.0 / __builtin_sqrt (a); +} + +float +rsqrt_f (float a) +{ + return 1.0f / __builtin_sqrtf (a); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-4.c b/gcc/testsuite/gcc.target/powerpc/recip-4.c new file mode 100644 index 000000000..bd496d70e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-4.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O3 -ftree-vectorize -mrecip -ffast-math -mcpu=power7 -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "xvrsqrtedp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsub.dp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 4 } } */ +/* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */ +/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmulsp" 4 } } */ +/* { dg-final { scan-assembler-times "xvnmsub.sp" 2 } } */ + +#define SIZE 1024 + +extern double a_d[SIZE] __attribute__((__aligned__(32))); +extern double b_d[SIZE] __attribute__((__aligned__(32))); + +void +vectorize_rsqrt_d (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a_d[i] = 1.0 / __builtin_sqrt (b_d[i]); +} + +extern float a_f[SIZE] __attribute__((__aligned__(32))); +extern float b_f[SIZE] __attribute__((__aligned__(32))); + +void +vectorize_rsqrt_f (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a_f[i] = 1.0f / __builtin_sqrtf (b_f[i]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-5.c b/gcc/testsuite/gcc.target/powerpc/recip-5.c new file mode 100644 index 000000000..4a9c49620 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-5.c @@ -0,0 +1,94 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "xvredp" 4 } } */ +/* { dg-final { scan-assembler-times "xvresp" 5 } } */ +/* { dg-final { scan-assembler-times "xsredp" 2 } } */ +/* { dg-final { scan-assembler-times "fres" 2 } } */ + +#include <altivec.h> + +float f_recip (float a, float b) { return __builtin_recipdivf (a, b); } +double d_recip (double a, double b) { return __builtin_recipdiv (a, b); } + +float f_div (float a, float b) { return a / b; } +double d_div (double a, double b) { return a / b; } + +#define SIZE 1024 + +double d_a[SIZE] __attribute__((__aligned__(32))); +double d_b[SIZE] __attribute__((__aligned__(32))); +double d_c[SIZE] __attribute__((__aligned__(32))); + +float f_a[SIZE] __attribute__((__aligned__(32))); +float f_b[SIZE] __attribute__((__aligned__(32))); +float f_c[SIZE] __attribute__((__aligned__(32))); + +void vec_f_recip (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f_a[i] = __builtin_recipdivf (f_b[i], f_c[i]); +} + +void vec_d_recip (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d_a[i] = __builtin_recipdiv (d_b[i], d_c[i]); +} + +void vec_f_div (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f_a[i] = f_b[i] / f_c[i]; +} + +void vec_f_div2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f_a[i] = f_b[i] / 2.0f; +} + +void vec_f_div53 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f_a[i] = f_b[i] / 53.0f; +} + +void vec_d_div (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d_a[i] = d_b[i] / d_c[i]; +} + +void vec_d_div2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d_a[i] = d_b[i] / 2.0; +} + +void vec_d_div53 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d_a[i] = d_b[i] / 53.0; +} + +vector float v4sf_recip1 (vector float a, vector float b) { return vec_recipdiv (a, b); } +vector float v4sf_recip2 (vector float a, vector float b) { return __builtin_altivec_vrecipdivfp (a, b); } +vector double v2df_recip1 (vector double a, vector double b) { return vec_recipdiv (a, b); } +vector float v4sf_recip3 (vector float a, vector float b) { return __builtin_vsx_xvrecipdivsp (a, b); } +vector double v2df_recip2 (vector double a, vector double b) { return __builtin_vsx_xvrecipdivdp (a, b); } diff --git a/gcc/testsuite/gcc.target/powerpc/recip-6.c b/gcc/testsuite/gcc.target/powerpc/recip-6.c new file mode 100644 index 000000000..7d71df670 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-6.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target vsx_hw } */ +/* { dg-options "-mcpu=power7 -O3 -ftree-vectorize -ffast-math -mrecip=all -mrecip-precision" } */ + +/* Check reciprocal estimate functions for accuracy. */ + +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <math.h> +#include <float.h> +#include <string.h> + +#include "recip-test.h" diff --git a/gcc/testsuite/gcc.target/powerpc/recip-7.c b/gcc/testsuite/gcc.target/powerpc/recip-7.c new file mode 100644 index 000000000..7b32ba076 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-7.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target ppc_recip_hw } */ +/* { dg-options "-O3 -ftree-vectorize -ffast-math -mrecip -mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb" } */ + +/* Check reciprocal estimate functions for accuracy. */ + +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <math.h> +#include <float.h> +#include <string.h> + +#include "recip-test.h" diff --git a/gcc/testsuite/gcc.target/powerpc/recip-test.h b/gcc/testsuite/gcc.target/powerpc/recip-test.h new file mode 100644 index 000000000..7a42df575 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-test.h @@ -0,0 +1,149 @@ +/* Check reciprocal estimate functions for accuracy. */ + +#ifdef _ARCH_PPC64 +typedef unsigned long uns64_t; +#define UNUM64(x) x ## L + +#else +typedef unsigned long long uns64_t; +#define UNUM64(x) x ## LL +#endif + +typedef unsigned int uns32_t; + +#define TNAME2(x) #x +#define TNAME(x) TNAME2(x) + +/* + * Float functions. + */ + +#define TYPE float +#define NAME(PREFIX) PREFIX ## _float +#define UNS_TYPE uns32_t +#define UNS_ABS __builtin_abs +#define EXP_SIZE 8 +#define MAN_SIZE 23 +#define FABS __builtin_fabsf +#define FMAX __builtin_fmaxf +#define FMIN __builtin_fminf +#define SQRT __builtin_sqrtf +#define RMIN 1.0e-10 +#define RMAX 1.0e+10 +#define BDIV 1 +#define BRSQRT 2 +#define ASMDIV "fdivs" +#define ASMSQRT "fsqrts" + +#define INIT_DIV \ +{ \ + { 0x4fffffff }, /* 8589934080 */ \ + { 0x4effffff }, /* 2147483520 */ \ + { 0x40ffffff }, /* 7.99999952316284 */ \ + { 0x3fffffff }, /* 1.99999988079071 */ \ + { 0x417fffff }, /* 15.9999990463257 */ \ + { 0x42ffffff }, /* 127.999992370605 */ \ + { 0x3dffffff }, /* 0.124999992549419 */ \ + { 0x3effffff }, /* 0.499999970197678 */ \ +} + +#define INIT_RSQRT \ +{ \ + { 0x457ffffe }, /* 4096 - small amount */ \ + { 0x4c7fffff }, /* 6.71089e+07 */ \ + { 0x3d7fffff }, /* 0.0625 - small amount */ \ + { 0x307ffffe }, /* 9.31322e-10 */ \ + { 0x4c7ffffe }, /* 6.71089e+07 */ \ + { 0x397ffffe }, /* 0.000244141 */ \ + { 0x2e7fffff }, /* 5.82077e-11 */ \ + { 0x2f7fffff }, /* 2.32831e-10 */ \ +} + + +#include "recip-test2.h" + +/* + * Double functions. + */ + +#undef TYPE +#undef NAME +#undef UNS_TYPE +#undef UNS_ABS +#undef EXP_SIZE +#undef MAN_SIZE +#undef FABS +#undef FMAX +#undef FMIN +#undef SQRT +#undef RMIN +#undef RMAX +#undef BDIV +#undef BRSQRT +#undef ASMDIV +#undef ASMSQRT +#undef INIT_DIV +#undef INIT_RSQRT + +#define TYPE double +#define NAME(PREFIX) PREFIX ## _double +#define UNS_TYPE uns64_t +#define UNS_ABS __builtin_imaxabs +#define EXP_SIZE 11 +#define MAN_SIZE 52 +#define FABS __builtin_fabs +#define FMAX __builtin_fmax +#define FMIN __builtin_fmin +#define SQRT __builtin_sqrt +#define RMIN 1.0e-100 +#define RMAX 1.0e+100 +#define BDIV 1 +#define BRSQRT 2 +#define ASMDIV "fdiv" +#define ASMSQRT "fsqrt" + +#define INIT_DIV \ +{ \ + { UNUM64 (0x2b57be53f2a2f3a0) }, /* 6.78462e-100 */ \ + { UNUM64 (0x2b35f8e8ea553e52) }, /* 1.56963e-100 */ \ + { UNUM64 (0x2b5b9d861d2fe4fb) }, /* 7.89099e-100 */ \ + { UNUM64 (0x2b45dc44a084e682) }, /* 3.12327e-100 */ \ + { UNUM64 (0x2b424ce16945d777) }, /* 2.61463e-100 */ \ + { UNUM64 (0x2b20b5023d496b50) }, /* 5.96749e-101 */ \ + { UNUM64 (0x2b61170547f57caa) }, /* 9.76678e-100 */ \ + { UNUM64 (0x2b543b9d498aac37) }, /* 5.78148e-100 */ \ +} + +#define INIT_RSQRT \ +{ \ + { UNUM64 (0x2b616f2d8cbbc646) }, /* 9.96359e-100 */ \ + { UNUM64 (0x2b5c4db2da0a011d) }, /* 8.08764e-100 */ \ + { UNUM64 (0x2b55a82d5735b262) }, /* 6.1884e-100 */ \ + { UNUM64 (0x2b50b52908258cb8) }, /* 4.77416e-100 */ \ + { UNUM64 (0x2b363989a4fb29af) }, /* 1.58766e-100 */ \ + { UNUM64 (0x2b508b9f6f4180a9) }, /* 4.7278e-100 */ \ + { UNUM64 (0x2b4f7a1d48accb40) }, /* 4.49723e-100 */ \ + { UNUM64 (0x2b1146a37372a81f) }, /* 3.08534e-101 */ \ + { UNUM64 (0x2b33f876a8c48050) }, /* 1.42663e-100 */ \ +} + +#include "recip-test2.h" + +int +main (int argc __attribute__((__unused__)), + char *argv[] __attribute__((__unused__))) +{ + srand48 (1); + run_float (); + +#ifdef VERBOSE + printf ("\n"); +#endif + + run_double (); + + if (error_count_float != 0 || error_count_double != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/recip-test2.h b/gcc/testsuite/gcc.target/powerpc/recip-test2.h new file mode 100644 index 000000000..3ec356cdf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/recip-test2.h @@ -0,0 +1,432 @@ +/* + * Included file to common source float/double checking + * The following macros should be defined: + * TYPE -- floating point type + * NAME -- convert a name to include the type + * UNS_TYPE -- type to hold TYPE as an unsigned number + * EXP_SIZE -- size in bits of the exponent + * MAN_SIZE -- size in bits of the mantissa + * UNS_ABS -- absolute value for UNS_TYPE + * FABS -- absolute value function for TYPE + * FMAX -- maximum function for TYPE + * FMIN -- minimum function for TYPE + * SQRT -- square root function for TYPE + * RMIN -- minimum random number to generate + * RMAX -- maximum random number to generate + * ASMDIV -- assembler instruction to do divide + * ASMSQRT -- assembler instruction to do square root + * BDIV -- # of bits of inaccuracy to allow for division + * BRSQRT -- # of bits of inaccuracy to allow for 1/sqrt + * INIT_DIV -- Initial values to test 1/x against + * INIT_RSQRT -- Initial values to test 1/sqrt(x) against + */ + +typedef union +{ + UNS_TYPE i; + TYPE x; +} NAME (union); + +/* + * Input/output arrays. + */ + +static NAME (union) NAME (div_input) [] __attribute__((__aligned__(32))) = INIT_DIV; +static NAME (union) NAME (rsqrt_input)[] __attribute__((__aligned__(32))) = INIT_RSQRT; + +#define DIV_SIZE (sizeof (NAME (div_input)) / sizeof (TYPE)) +#define RSQRT_SIZE (sizeof (NAME (rsqrt_input)) / sizeof (TYPE)) + +static TYPE NAME (div_expected)[DIV_SIZE] __attribute__((__aligned__(32))); +static TYPE NAME (div_output) [DIV_SIZE] __attribute__((__aligned__(32))); + +static TYPE NAME (rsqrt_expected)[RSQRT_SIZE] __attribute__((__aligned__(32))); +static TYPE NAME (rsqrt_output) [RSQRT_SIZE] __attribute__((__aligned__(32))); + + +/* + * Crack a floating point number into sign bit, exponent, and mantissa. + */ + +static void +NAME (crack) (TYPE number, unsigned int *p_sign, unsigned *p_exponent, UNS_TYPE *p_mantissa) +{ + NAME (union) u; + UNS_TYPE bits; + + u.x = number; + bits = u.i; + + *p_sign = (unsigned int)((bits >> (EXP_SIZE + MAN_SIZE)) & 0x1); + *p_exponent = (unsigned int)((bits >> MAN_SIZE) & ((((UNS_TYPE)1) << EXP_SIZE) - 1)); + *p_mantissa = bits & ((((UNS_TYPE)1) << MAN_SIZE) - 1); + return; +} + + +/* + * Prevent optimizer from eliminating + 0.0 to remove -0.0. + */ + +volatile TYPE NAME (math_diff_0) = ((TYPE) 0.0); + +/* + * Return negative if two numbers are significanly different or return the + * number of bits that are different in the mantissa. + */ + +static int +NAME (math_diff) (TYPE a, TYPE b, int bits) +{ + TYPE zero = NAME (math_diff_0); + unsigned int sign_a, sign_b; + unsigned int exponent_a, exponent_b; + UNS_TYPE mantissa_a, mantissa_b, diff; + int i; + + /* eliminate signed zero. */ + a += zero; + b += zero; + + /* special case Nan. */ + if (__builtin_isnan (a)) + return (__builtin_isnan (b) ? 0 : -1); + + if (a == b) + return 0; + + /* special case infinity. */ + if (__builtin_isinf (a)) + return (__builtin_isinf (b) ? 0 : -1); + + /* punt on denormal numbers. */ + if (!__builtin_isnormal (a) || !__builtin_isnormal (b)) + return -1; + + NAME (crack) (a, &sign_a, &exponent_a, &mantissa_a); + NAME (crack) (b, &sign_b, &exponent_b, &mantissa_b); + + /* If the sign is different, there is no hope. */ + if (sign_a != sign_b) + return -1; + + /* If the exponent is off by 1, see if the values straddle the power of two, + and adjust things to do the mantassa check if we can. */ + if ((exponent_a == (exponent_b+1)) || (exponent_a == (exponent_b-1))) + { + TYPE big = FMAX (a, b); + TYPE small = FMIN (a, b); + TYPE diff = FABS (a - b); + unsigned int sign_big, sign_small, sign_test; + unsigned int exponent_big, exponent_small, exponent_test; + UNS_TYPE mantissa_big, mantissa_small, mantissa_test; + + NAME (crack) (big, &sign_big, &exponent_big, &mantissa_big); + NAME (crack) (small, &sign_small, &exponent_small, &mantissa_small); + + NAME (crack) (small - diff, &sign_test, &exponent_test, &mantissa_test); + if ((sign_test == sign_small) && (exponent_test == exponent_small)) + { + mantissa_a = mantissa_small; + mantissa_b = mantissa_test; + } + + else + { + NAME (crack) (big + diff, &sign_test, &exponent_test, &mantissa_test); + if ((sign_test == sign_big) && (exponent_test == exponent_big)) + { + mantissa_a = mantissa_big; + mantissa_b = mantissa_test; + } + + else + return -1; + } + } + + else if (exponent_a != exponent_b) + return -1; + + diff = UNS_ABS (mantissa_a - mantissa_b); + for (i = MAN_SIZE; i > 0; i--) + { + if ((diff & ((UNS_TYPE)1) << (i-1)) != 0) + return i; + } + + return -1; +} + + +/* + * Turn off inlining to make code inspection easier. + */ + +static void NAME (asm_div) (void) __attribute__((__noinline__)); +static void NAME (vector_div) (void) __attribute__((__noinline__)); +static void NAME (scalar_div) (void) __attribute__((__noinline__)); +static void NAME (asm_rsqrt) (void) __attribute__((__noinline__)); +static void NAME (vector_rsqrt) (void) __attribute__((__noinline__)); +static void NAME (scalar_rsqrt) (void) __attribute__((__noinline__)); +static void NAME (check_div) (const char *) __attribute__((__noinline__)); +static void NAME (check_rsqrt) (const char *) __attribute__((__noinline__)); +static void NAME (run) (void) __attribute__((__noinline__)); + + +/* + * Division function that might be vectorized. + */ + +static void +NAME (vector_div) (void) +{ + size_t i; + + for (i = 0; i < DIV_SIZE; i++) + NAME (div_output)[i] = ((TYPE) 1.0) / NAME (div_input)[i].x; +} + +/* + * Division function that is not vectorized. + */ + +static void +NAME (scalar_div) (void) +{ + size_t i; + + for (i = 0; i < DIV_SIZE; i++) + { + TYPE x = ((TYPE) 1.0) / NAME (div_input)[i].x; + TYPE y; + __asm__ ("" : "=d" (y) : "0" (x)); + NAME (div_output)[i] = y; + } +} + +/* + * Generate the division instruction via asm. + */ + +static void +NAME (asm_div) (void) +{ + size_t i; + + for (i = 0; i < DIV_SIZE; i++) + { + TYPE x; + __asm__ (ASMDIV " %0,%1,%2" + : "=d" (x) + : "d" ((TYPE) 1.0), "d" (NAME (div_input)[i].x)); + NAME (div_expected)[i] = x; + } +} + +/* + * Reciprocal square root function that might be vectorized. + */ + +static void +NAME (vector_rsqrt) (void) +{ + size_t i; + + for (i = 0; i < RSQRT_SIZE; i++) + NAME (rsqrt_output)[i] = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x); +} + +/* + * Reciprocal square root function that is not vectorized. + */ + +static void +NAME (scalar_rsqrt) (void) +{ + size_t i; + + for (i = 0; i < RSQRT_SIZE; i++) + { + TYPE x = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x); + TYPE y; + __asm__ ("" : "=d" (y) : "0" (x)); + NAME (rsqrt_output)[i] = y; + } +} + +/* + * Generate the 1/sqrt instructions via asm. + */ + +static void +NAME (asm_rsqrt) (void) +{ + size_t i; + + for (i = 0; i < RSQRT_SIZE; i++) + { + TYPE x; + TYPE y; + __asm__ (ASMSQRT " %0,%1" : "=d" (x) : "d" (NAME (rsqrt_input)[i].x)); + __asm__ (ASMDIV " %0,%1,%2" : "=d" (y) : "d" ((TYPE) 1.0), "d" (x)); + NAME (rsqrt_expected)[i] = y; + } +} + + +/* + * Functions to abort or report errors. + */ + +static int NAME (error_count) = 0; + +#ifdef VERBOSE +static int NAME (max_bits_div) = 0; +static int NAME (max_bits_rsqrt) = 0; +#endif + + +/* + * Compare the expected value with the value we got. + */ + +static void +NAME (check_div) (const char *test) +{ + size_t i; + int b; + + for (i = 0; i < DIV_SIZE; i++) + { + TYPE exp = NAME (div_expected)[i]; + TYPE out = NAME (div_output)[i]; + b = NAME (math_diff) (exp, out, BDIV); + +#ifdef VERBOSE + if (b != 0) + { + NAME (union) u_in = NAME (div_input)[i]; + NAME (union) u_exp; + NAME (union) u_out; + char explanation[64]; + const char *p_exp; + + if (b < 0) + p_exp = "failed"; + else + { + p_exp = explanation; + sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : ""); + } + + u_exp.x = exp; + u_out.x = out; + printf ("%s %s %s for 1.0 / %g [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n", + TNAME (TYPE), test, p_exp, + (double) u_in.x, (unsigned long long) u_in.i, + (double) exp, (unsigned long long) u_exp.i, + (double) out, (unsigned long long) u_out.i); + } +#endif + + if (b < 0 || b > BDIV) + NAME (error_count)++; + +#ifdef VERBOSE + if (b > NAME (max_bits_div)) + NAME (max_bits_div) = b; +#endif + } +} + +static void +NAME (check_rsqrt) (const char *test) +{ + size_t i; + int b; + + for (i = 0; i < RSQRT_SIZE; i++) + { + TYPE exp = NAME (rsqrt_expected)[i]; + TYPE out = NAME (rsqrt_output)[i]; + b = NAME (math_diff) (exp, out, BRSQRT); + +#ifdef VERBOSE + if (b != 0) + { + NAME (union) u_in = NAME (rsqrt_input)[i]; + NAME (union) u_exp; + NAME (union) u_out; + char explanation[64]; + const char *p_exp; + + if (b < 0) + p_exp = "failed"; + else + { + p_exp = explanation; + sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : ""); + } + + u_exp.x = exp; + u_out.x = out; + printf ("%s %s %s for 1 / sqrt (%g) [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n", + TNAME (TYPE), test, p_exp, + (double) u_in.x, (unsigned long long) u_in.i, + (double) exp, (unsigned long long) u_exp.i, + (double) out, (unsigned long long) u_out.i); + } +#endif + + if (b < 0 || b > BRSQRT) + NAME (error_count)++; + +#ifdef VERBOSE + if (b > NAME (max_bits_rsqrt)) + NAME (max_bits_rsqrt) = b; +#endif + } +} + + +/* + * Now do everything. + */ + +static void +NAME (run) (void) +{ +#ifdef VERBOSE + printf ("start run_%s, divide size = %ld, rsqrt size = %ld, %d bit%s for a/b, %d bit%s for 1/sqrt(a)\n", + TNAME (TYPE), + (long)DIV_SIZE, + (long)RSQRT_SIZE, + BDIV, (BDIV == 1) ? "" : "s", + BRSQRT, (BRSQRT == 1) ? "" : "s"); +#endif + + NAME (asm_div) (); + + NAME (scalar_div) (); + NAME (check_div) ("scalar"); + + NAME (vector_div) (); + NAME (check_div) ("vector"); + + NAME (asm_rsqrt) (); + + NAME (scalar_rsqrt) (); + NAME (check_rsqrt) ("scalar"); + + NAME (vector_rsqrt) (); + NAME (check_rsqrt) ("vector"); + +#ifdef VERBOSE + printf ("end run_%s, errors = %d, max div bits = %d, max rsqrt bits = %d\n", + TNAME (TYPE), + NAME (error_count), + NAME (max_bits_div), + NAME (max_bits_rsqrt)); +#endif +} diff --git a/gcc/testsuite/gcc.target/powerpc/regnames-1.c b/gcc/testsuite/gcc.target/powerpc/regnames-1.c new file mode 100644 index 000000000..e34e6241d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/regnames-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-mregnames" } */ + +register double f17 asm ("f17"); +double foo (void) +{ + return f17; +} diff --git a/gcc/testsuite/gcc.target/powerpc/rotate.c b/gcc/testsuite/gcc.target/powerpc/rotate.c new file mode 100644 index 000000000..5d47215d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rotate.c @@ -0,0 +1,6 @@ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "slwi" } } */ +unsigned int foo (unsigned int x) +{ + return ((x >> 16) & 0xffff) | ((x & 0xffff) << 16); +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c new file mode 100644 index 000000000..66bb61d25 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-darwin* powerpc*-*-linux* } } */ +/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */ +extern void bar (void *); +extern double x; +void +foo (void) +{ + char buf2 [32][1024]; + bar (buf2 [(int) x]); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c new file mode 100644 index 000000000..410f780de --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */ +/* { dg-options "-mno-powerpc-gfxopt" } */ +/* { dg-final { scan-assembler-not "stfiwx" } } */ + +/* A basic test of the old-style (not stfiwx) fp -> int conversion. */ +int f(double a, double b) +{ + int a1 = a; + int b1 = b; + return a1+b1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c new file mode 100644 index 000000000..8d474f076 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */ +/* { dg-options "-mlong-double-128" } */ + +/* Check that long double values are rounded correctly when being converted + to 32-bit integers. All these values are of the form +/- 2 +/- 2^-60. */ + +extern void abort(void); +extern void exit(int); + +int main(void) +{ + long double l1 = 1.9999999999999999991326382620115964527941L; + long double l2 = 2.0000000000000000008673617379884035472059L; + long double l3 = -2.0000000000000000008673617379884035472059L; + long double l4 = -1.9999999999999999991326382620115964527941L; + + if ((int) l1 != 1) + abort (); + if ((int) l2 != 2) + abort (); + if ((int) l3 != -2) + abort (); + if ((int) l4 != -1) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c new file mode 100644 index 000000000..5dc74cd2d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */ +/* { dg-options "-mlong-double-128" } */ + +/* Check that LDBL_EPSILON is right for 'long double'. */ + +#include <float.h> + +extern void abort (void); + +int main(void) +{ + volatile long double ee = 1.0; + long double eps = ee; + while (ee + 1.0 != 1.0) + { + eps = ee; + ee = eps / 2; + } + if (eps != LDBL_EPSILON) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c new file mode 100644 index 000000000..375241ec6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ +/* This used to ICE as the peephole was not checking to see + if the register is a floating point one (I think this cannot + happen in real life except in this example). */ + +register volatile double t1 __asm__("r14"); +register volatile double t2 __asm__("r15"); +register volatile double t3 __asm__("r16"), t4 __asm__("r17"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c new file mode 100644 index 000000000..567ad8c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc_fprs && ilp32 } } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w" } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "sfd" } } */ +/* { dg-final { scan-assembler "lfq" } } */ +/* { dg-final { scan-assembler "stfq" } } */ + +register volatile double t1 __asm__("fr0"); +register volatile double t2 __asm__("fr1"); +register volatile double t3 __asm__("fr2"), t4 __asm__("fr3"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c b/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c new file mode 100644 index 000000000..8bdb154e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c @@ -0,0 +1,14 @@ +/* Verify that we don't ICE trying to put SPE data in .sdata2. */ +/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */ +/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */ + +#include <spe.h> + +__ev64_fs__ x; + +int main(void) +{ + x = __ev_fsabs (x); + return(0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c b/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c new file mode 100644 index 000000000..2a466e344 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c @@ -0,0 +1,12 @@ +/* Verify that we don't ICE trying to put float data in .sdata2. */ +/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */ +/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */ + +double x; + +int main(void) +{ + x = x * 2; + return(0); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c b/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c new file mode 100644 index 000000000..84d4bf288 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c @@ -0,0 +1,116 @@ +/* Verify that unwinding can find SPE registers in signal frames. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */ +/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */ + +#include <unwind.h> +#include <stdlib.h> +#include <signal.h> +#include <string.h> + +int count; +char *null; +int found_reg; + +typedef int v2si __attribute__((__vector_size__(8))); + +v2si v1 = { 123, 234 }; +v2si v2 = { 345, 456 }; + +static _Unwind_Reason_Code +force_unwind_stop (int version, _Unwind_Action actions, + _Unwind_Exception_Class exc_class, + struct _Unwind_Exception *exc_obj, + struct _Unwind_Context *context, + void *stop_parameter) +{ + unsigned int reg; + if (actions & _UA_END_OF_STACK) + abort (); + if (_Unwind_GetGR (context, 1215) == 123) + found_reg = 1; + return _URC_NO_REASON; +} + +static void force_unwind () +{ + struct _Unwind_Exception *exc = malloc (sizeof (*exc)); + memset (&exc->exception_class, 0, sizeof (exc->exception_class)); + exc->exception_cleanup = 0; + +#ifndef __USING_SJLJ_EXCEPTIONS__ + _Unwind_ForcedUnwind (exc, force_unwind_stop, 0); +#else + _Unwind_SjLj_ForcedUnwind (exc, force_unwind_stop, 0); +#endif + + abort (); +} + +static void counter (void *p __attribute__((unused))) +{ + ++count; +} + +static void handler (void *p __attribute__((unused))) +{ + if (count != 2) + abort (); + if (!found_reg) + abort (); + exit (0); +} + +static int __attribute__((noinline)) fn5 () +{ + char dummy __attribute__((cleanup (counter))); + force_unwind (); + return 0; +} + +static void fn4 (int sig) +{ + char dummy __attribute__((cleanup (counter))); + /* Clobber high part without compiler's knowledge so the only saved + copy is from the signal frame. */ + asm volatile ("evmergelo 15,15,15"); + fn5 (); + null = NULL; +} + +static void fn3 () +{ + abort (); +} + +static int __attribute__((noinline)) fn2 () +{ + register v2si r15 asm("r15"); + r15 = v1; + asm volatile ("" : "+r" (r15)); + *null = 0; + fn3 (); + return 0; +} + +static int __attribute__((noinline)) fn1 () +{ + signal (SIGSEGV, fn4); + signal (SIGBUS, fn4); + fn2 (); + return 0; +} + +static int __attribute__((noinline)) fn0 () +{ + char dummy __attribute__((cleanup (handler))); + fn1 (); + null = 0; + return 0; +} + +int main() +{ + fn0 (); + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c new file mode 100644 index 000000000..09f813482 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-final { scan-assembler "evstdd" } } */ + +void foo(void) +{ + int x[8] __attribute__((aligned(64))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c b/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c new file mode 100644 index 000000000..7ecaf1037 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_spe } */ +/* { dg-options "-O -mspe=yes" } */ +/* { dg-final { scan-assembler "evstdd" } } */ + +#include <string.h> + +void foo(void) +{ + int x[8] __attribute__((aligned(64))); + memset (x, 0, sizeof (x)); + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc/testsuite/gcc.target/powerpc/spe1.c new file mode 100644 index 000000000..ddbb5a6e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* (Test with -O0 so we don't optimize any of them away). */ + + +typedef float __attribute__((vector_size(8))) __ev64_fs__; + +__ev64_opaque__ Foo (void); + +void Bar () +{ + __ev64_fs__ fs = Foo (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c b/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c new file mode 100644 index 000000000..3c52287b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c @@ -0,0 +1,11 @@ +/* Test Attribute Vector associated with vector type stabs. */ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types -faltivec" } */ + +int main () +{ + vector int vi = { 6,7,8,9 }; + return 0; +} + +/* { dg-final { scan-assembler ".stabs.*vi\:\\(0,\[0-9\]+\\)=\@V" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c new file mode 100644 index 000000000..42d5b6056 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvadddp" } } */ +/* { dg-final { scan-assembler "xvsubdp" } } */ +/* { dg-final { scan-assembler "xvmuldp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvnmadd" } } */ +/* { dg-final { scan-assembler "xvnmsub" } } */ +/* { dg-final { scan-assembler "xvdivdp" } } */ +/* { dg-final { scan-assembler "xvmaxdp" } } */ +/* { dg-final { scan-assembler "xvmindp" } } */ +/* { dg-final { scan-assembler "xvsqrtdp" } } */ +/* { dg-final { scan-assembler "xvrsqrtedp" } } */ +/* { dg-final { scan-assembler "xvabsdp" } } */ +/* { dg-final { scan-assembler "xvnabsdp" } } */ +/* { dg-final { scan-assembler "xvredp" } } */ + +void use_builtins (__vector double *p, __vector double *q, __vector double *r, __vector double *s) +{ + p[0] = __builtin_vsx_xvadddp (q[0], r[0]); + p[1] = __builtin_vsx_xvsubdp (q[1], r[1]); + p[2] = __builtin_vsx_xvmuldp (q[2], r[2]); + p[3] = __builtin_vsx_xvdivdp (q[3], r[3]); + p[4] = __builtin_vsx_xvmaxdp (q[4], r[4]); + p[5] = __builtin_vsx_xvmindp (q[5], r[5]); + p[6] = __builtin_vsx_xvabsdp (q[6]); + p[7] = __builtin_vsx_xvnabsdp (q[7]); + p[8] = __builtin_vsx_xvsqrtdp (q[8]); + p[9] = __builtin_vsx_xvmadddp (q[9], r[9], s[9]); + p[10] = __builtin_vsx_xvmsubdp (q[10], r[10], s[10]); + p[11] = __builtin_vsx_xvnmadddp (q[11], r[11], s[11]); + p[12] = __builtin_vsx_xvnmsubdp (q[12], r[12], s[12]); + p[13] = __builtin_vsx_xvredp (q[13]); + p[14] = __builtin_vsx_xvrsqrtedp (q[14]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c new file mode 100644 index 000000000..6d883dc90 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvnmadd" } } */ +/* { dg-final { scan-assembler "xvnmsub" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmaxsp" } } */ +/* { dg-final { scan-assembler "xvminsp" } } */ +/* { dg-final { scan-assembler "xvsqrtsp" } } */ +/* { dg-final { scan-assembler "xvabssp" } } */ +/* { dg-final { scan-assembler "xvnabssp" } } */ +/* { dg-final { scan-assembler "xvresp" } } */ +/* { dg-final { scan-assembler "xvrsqrtesp" } } */ + +void use_builtins (__vector float *p, __vector float *q, __vector float *r, __vector float *s) +{ + p[0] = __builtin_vsx_xvaddsp (q[0], r[0]); + p[1] = __builtin_vsx_xvsubsp (q[1], r[1]); + p[2] = __builtin_vsx_xvmulsp (q[2], r[2]); + p[3] = __builtin_vsx_xvdivsp (q[3], r[3]); + p[4] = __builtin_vsx_xvmaxsp (q[4], r[4]); + p[5] = __builtin_vsx_xvminsp (q[5], r[5]); + p[6] = __builtin_vsx_xvabssp (q[6]); + p[7] = __builtin_vsx_xvnabssp (q[7]); + p[8] = __builtin_vsx_xvsqrtsp (q[8]); + p[9] = __builtin_vsx_xvmaddsp (q[9], r[9], s[9]); + p[10] = __builtin_vsx_xvmsubsp (q[10], r[10], s[10]); + p[11] = __builtin_vsx_xvnmaddsp (q[11], r[11], s[11]); + p[12] = __builtin_vsx_xvnmsubsp (q[12], r[12], s[12]); + p[13] = __builtin_vsx_xvresp (q[13]); + p[14] = __builtin_vsx_xvrsqrtesp (q[14]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c new file mode 100644 index 000000000..8450920ec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c @@ -0,0 +1,212 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxsel" } } */ +/* { dg-final { scan-assembler "vperm" } } */ +/* { dg-final { scan-assembler "xvrdpi" } } */ +/* { dg-final { scan-assembler "xvrdpic" } } */ +/* { dg-final { scan-assembler "xvrdpim" } } */ +/* { dg-final { scan-assembler "xvrdpip" } } */ +/* { dg-final { scan-assembler "xvrdpiz" } } */ +/* { dg-final { scan-assembler "xvrspi" } } */ +/* { dg-final { scan-assembler "xvrspic" } } */ +/* { dg-final { scan-assembler "xvrspim" } } */ +/* { dg-final { scan-assembler "xvrspip" } } */ +/* { dg-final { scan-assembler "xvrspiz" } } */ +/* { dg-final { scan-assembler "xsrdpi" } } */ +/* { dg-final { scan-assembler "xsrdpic" } } */ +/* { dg-final { scan-assembler "xsrdpim" } } */ +/* { dg-final { scan-assembler "xsrdpip" } } */ +/* { dg-final { scan-assembler "xsrdpiz" } } */ +/* { dg-final { scan-assembler "xsmaxdp" } } */ +/* { dg-final { scan-assembler "xsmindp" } } */ +/* { dg-final { scan-assembler "xxland" } } */ +/* { dg-final { scan-assembler "xxlandc" } } */ +/* { dg-final { scan-assembler "xxlnor" } } */ +/* { dg-final { scan-assembler "xxlor" } } */ +/* { dg-final { scan-assembler "xxlxor" } } */ +/* { dg-final { scan-assembler "xvcmpeqdp" } } */ +/* { dg-final { scan-assembler "xvcmpgtdp" } } */ +/* { dg-final { scan-assembler "xvcmpgedp" } } */ +/* { dg-final { scan-assembler "xvcmpeqsp" } } */ +/* { dg-final { scan-assembler "xvcmpgtsp" } } */ +/* { dg-final { scan-assembler "xvcmpgesp" } } */ +/* { dg-final { scan-assembler "xxsldwi" } } */ +/* { dg-final { scan-assembler-not "call" } } */ + +extern __vector int si[][4]; +extern __vector short ss[][4]; +extern __vector signed char sc[][4]; +extern __vector float f[][4]; +extern __vector unsigned int ui[][4]; +extern __vector unsigned short us[][4]; +extern __vector unsigned char uc[][4]; +extern __vector __bool int bi[][4]; +extern __vector __bool short bs[][4]; +extern __vector __bool char bc[][4]; +extern __vector __pixel p[][4]; +#ifdef __VSX__ +extern __vector double d[][4]; +extern __vector long sl[][4]; +extern __vector unsigned long ul[][4]; +extern __vector __bool long bl[][4]; +#endif + +int do_sel(void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++; + + si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], bi[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], bl[i][3]); i++; + + si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], ui[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], us[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], ui[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], ul[i][3]); i++; + + return i; +} + +int do_perm(void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], uc[i][3]); i++; + ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], uc[i][3]); i++; + sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], uc[i][3]); i++; + d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], uc[i][3]); i++; + + si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++; + ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++; + sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++; + d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++; + + return i; +} + +int do_xxperm (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xxpermdi_2df (d[i][1], d[i][2], 0); i++; + d[i][0] = __builtin_vsx_xxpermdi (d[i][1], d[i][2], 1); i++; + return i; +} + +double x, y; +void do_concat (void) +{ + d[0][0] = __builtin_vsx_concat_2df (x, y); +} + +void do_set (void) +{ + d[0][0] = __builtin_vsx_set_2df (d[0][1], x, 0); + d[1][0] = __builtin_vsx_set_2df (d[1][1], y, 1); +} + +extern double z[][4]; + +int do_math (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xvrdpi (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpic (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpim (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpip (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpiz (d[i][1]); i++; + + f[i][0] = __builtin_vsx_xvrspi (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspic (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspim (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspip (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspiz (f[i][1]); i++; + + z[i][0] = __builtin_vsx_xsrdpi (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpic (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpim (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpiz (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsmaxdp (z[i][1], z[i][0]); i++; + z[i][0] = __builtin_vsx_xsmindp (z[i][1], z[i][0]); i++; + return i; +} + +int do_cmp (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++; + + f[i][0] = __builtin_vsx_xvcmpeqsp (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xvcmpgtsp (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xvcmpgesp (f[i][1], f[i][2]); i++; + return i; +} + +int do_logical (void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxland (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlandc (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlnor (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlor (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlxor (si[i][1], si[i][2]); i++; + + ss[i][0] = __builtin_vsx_xxland (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlandc (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlnor (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlor (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlxor (ss[i][1], ss[i][2]); i++; + + sc[i][0] = __builtin_vsx_xxland (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlandc (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlnor (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlor (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlxor (sc[i][1], sc[i][2]); i++; + + d[i][0] = __builtin_vsx_xxland (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlandc (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlnor (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlor (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlxor (d[i][1], d[i][2]); i++; + + f[i][0] = __builtin_vsx_xxland (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlandc (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlnor (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlor (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlxor (f[i][1], f[i][2]); i++; + return i; +} + +int do_xxsldwi (void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxsldwi (si[i][1], si[i][2], 0); i++; + ss[i][0] = __builtin_vsx_xxsldwi (ss[i][1], ss[i][2], 1); i++; + sc[i][0] = __builtin_vsx_xxsldwi (sc[i][1], sc[i][2], 2); i++; + ui[i][0] = __builtin_vsx_xxsldwi (ui[i][1], ui[i][2], 3); i++; + us[i][0] = __builtin_vsx_xxsldwi (us[i][1], us[i][2], 0); i++; + uc[i][0] = __builtin_vsx_xxsldwi (uc[i][1], uc[i][2], 1); i++; + f[i][0] = __builtin_vsx_xxsldwi (f[i][1], f[i][2], 2); i++; + d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++; + return i; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c new file mode 100644 index 000000000..bcf486377 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c @@ -0,0 +1,142 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvcmpeqdp." } } */ +/* { dg-final { scan-assembler "xvcmpgtdp." } } */ +/* { dg-final { scan-assembler "xvcmpgedp." } } */ +/* { dg-final { scan-assembler "xvcmpeqsp." } } */ +/* { dg-final { scan-assembler "xvcmpgtsp." } } */ +/* { dg-final { scan-assembler "xvcmpgesp." } } */ +/* { dg-final { scan-assembler "vcmpbfp." } } */ +/* { dg-final { scan-assembler "vcmpequb." } } */ +/* { dg-final { scan-assembler "vcmpequh." } } */ +/* { dg-final { scan-assembler "vcmpequw." } } */ +/* { dg-final { scan-assembler "vcmpgtub." } } */ +/* { dg-final { scan-assembler "vcmpgtuh." } } */ +/* { dg-final { scan-assembler "vcmpgtuw." } } */ +/* { dg-final { scan-assembler "vcmpgtsb." } } */ +/* { dg-final { scan-assembler "vcmpgtsh." } } */ +/* { dg-final { scan-assembler "vcmpgtsw." } } */ +/* { dg-final { scan-assembler-not "vcmpeqfp" } } */ +/* { dg-final { scan-assembler-not "vcmpgtfp" } } */ +/* { dg-final { scan-assembler-not "vcmpgefp" } } */ + +/* check that Altivec builtins generate VSX if -mvsx. */ + +#include <altivec.h> + +int *v16qi_s (vector signed char *a, vector signed char *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v16qi_u (vector unsigned char *a, vector unsigned char *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v8hi_s (vector short *a, vector short *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v8hi_u (vector unsigned short *a, vector unsigned short *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4si_s (vector int *a, vector int *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4si_u (vector unsigned int *a, vector unsigned int *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4sf (vector float *a, vector float *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 3; + + if (vec_all_in (*a, *b)) /* veccmpbfp. */ + *p++ = 4; + + return p; +} + +int *v2df (vector double *a, vector double *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 3; + + return p; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c new file mode 100644 index 000000000..5c24dc618 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxpermdi" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ + +/* Make sure double extract doesn't use a store instruction. */ + +double d0(__vector double v){ return __builtin_vec_extract (v, 0); } +double d1(__vector double v){ return __builtin_vec_extract (v, 1); } + +double e0(vector double v){ return __builtin_vec_ext_v2df (v, 0); } +double e1(vector double v){ return __builtin_vec_ext_v2df (v, 1); } diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c new file mode 100644 index 000000000..a722b83b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c @@ -0,0 +1,146 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* Check whether tdiv and tsqrt instructions generate the correct code. */ +/* Each of the *tdiv* and *tsqrt* instructions should be generated exactly 3 + times (the two calls in the _1 function should be combined). */ +/* { dg-final { scan-assembler-times "xstdivdp" 3 } } */ +/* { dg-final { scan-assembler-times "xvtdivdp" 3 } } */ +/* { dg-final { scan-assembler-times "xvtdivsp" 3 } } */ +/* { dg-final { scan-assembler-times "xstsqrtdp" 3 } } */ +/* { dg-final { scan-assembler-times "xvtsqrtdp" 3 } } */ +/* { dg-final { scan-assembler-times "xvtsqrtsp" 3 } } */ + +void test_div_df_1 (double a, double b, int *p) +{ + p[0] = __builtin_vsx_xstdivdp_fe (a, b); + p[1] = __builtin_vsx_xstdivdp_fg (a, b); +} + +int *test_div_df_2 (double a, double b, int *p) +{ + if (__builtin_vsx_xstdivdp_fe (a, b)) + *p++ = 1; + + return p; +} + +int *test_div_df_3 (double a, double b, int *p) +{ + if (__builtin_vsx_xstdivdp_fg (a, b)) + *p++ = 1; + + return p; +} + +void test_sqrt_df_1 (double a, int *p) +{ + p[0] = __builtin_vsx_xstsqrtdp_fe (a); + p[1] = __builtin_vsx_xstsqrtdp_fg (a); +} + +int *test_sqrt_df_2 (double a, int *p) +{ + if (__builtin_vsx_xstsqrtdp_fe (a)) + *p++ = 1; + + return p; +} + +int *test_sqrt_df_3 (double a, int *p) +{ + if (__builtin_vsx_xstsqrtdp_fg (a)) + *p++ = 1; + + return p; +} + +void test_div_v2df_1 (__vector double *a, __vector double *b, int *p) +{ + p[0] = __builtin_vsx_xvtdivdp_fe (*a, *b); + p[1] = __builtin_vsx_xvtdivdp_fg (*a, *b); +} + +int *test_div_v2df_2 (__vector double *a, __vector double *b, int *p) +{ + if (__builtin_vsx_xvtdivdp_fe (*a, *b)) + *p++ = 1; + + return p; +} + +int *test_div_v2df_3 (__vector double *a, __vector double *b, int *p) +{ + if (__builtin_vsx_xvtdivdp_fg (*a, *b)) + *p++ = 1; + + return p; +} + +void test_sqrt_v2df_1 (__vector double *a, int *p) +{ + p[0] = __builtin_vsx_xvtsqrtdp_fe (*a); + p[1] = __builtin_vsx_xvtsqrtdp_fg (*a); +} + +int *test_sqrt_v2df_2 (__vector double *a, int *p) +{ + if (__builtin_vsx_xvtsqrtdp_fe (*a)) + *p++ = 1; + + return p; +} + +int *test_sqrt_v2df_3 (__vector double *a, int *p) +{ + if (__builtin_vsx_xvtsqrtdp_fg (*a)) + *p++ = 1; + + return p; +} + +void test_div_v4sf_1 (__vector float *a, __vector float *b, int *p) +{ + p[0] = __builtin_vsx_xvtdivsp_fe (*a, *b); + p[1] = __builtin_vsx_xvtdivsp_fg (*a, *b); +} + +int *test_div_v4sf_2 (__vector float *a, __vector float *b, int *p) +{ + if (__builtin_vsx_xvtdivsp_fe (*a, *b)) + *p++ = 1; + + return p; +} + +int *test_div_v4sf_3 (__vector float *a, __vector float *b, int *p) +{ + if (__builtin_vsx_xvtdivsp_fg (*a, *b)) + *p++ = 1; + + return p; +} + +void test_sqrt_v4sf_1 (__vector float *a, int *p) +{ + p[0] = __builtin_vsx_xvtsqrtsp_fe (*a); + p[1] = __builtin_vsx_xvtsqrtsp_fg (*a); +} + +int *test_sqrt_v4sf_2 (__vector float *a, int *p) +{ + if (__builtin_vsx_xvtsqrtsp_fe (*a)) + *p++ = 1; + + return p; +} + +int *test_sqrt_v4sf_3 (__vector float *a, int *p) +{ + if (__builtin_vsx_xvtsqrtsp_fg (*a)) + *p++ = 1; + + return p; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c new file mode 100644 index 000000000..55e999d38 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c @@ -0,0 +1,150 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* Test simple extract/insert/slat operations. Make sure all types are + supported with various options. */ + +#include <altivec.h> + +double extract_df_0_reg (vector double p) { return vec_extract (p, 0); } +double extract_df_1_reg (vector double p) { return vec_extract (p, 1); } +double extract_df_n_reg (vector double p, int n) { return vec_extract (p, n); } + +double extract_df_0_mem (vector double *p) { return vec_extract (*p, 0); } +double extract_df_1_mem (vector double *p) { return vec_extract (*p, 1); } +double extract_df_n_mem (vector double *p, int n) { return vec_extract (*p, n); } + +vector double insert_df_0 (vector double p, double x) { return vec_insert (x, p, 0); } +vector double insert_df_1 (vector double p, double x) { return vec_insert (x, p, 1); } +vector double insert_df_n (vector double p, double x, int n) { return vec_insert (x, p, n); } + +vector double splat_df_reg (double x) { return vec_splats (x); } +vector double splat_df_mem (double *x) { return vec_splats (*x); } + +#ifdef _ARCH_PPC64 +#define ll long +#else +#define ll long long +#endif + +ll extract_di_0_reg (vector ll p) { return vec_extract (p, 0); } +ll extract_di_1_reg (vector ll p) { return vec_extract (p, 1); } +ll extract_di_n_reg (vector ll p, int n) { return vec_extract (p, n); } + +ll extract_di_0_mem (vector ll *p) { return vec_extract (*p, 0); } +ll extract_di_1_mem (vector ll *p) { return vec_extract (*p, 1); } +ll extract_di_n_mem (vector ll *p, int n) { return vec_extract (*p, n); } + +vector ll insert_di_0 (vector ll p, ll x) { return vec_insert (x, p, 0); } +vector ll insert_di_1 (vector ll p, ll x) { return vec_insert (x, p, 1); } +vector ll insert_di_n (vector ll p, ll x, int n) { return vec_insert (x, p, n); } + +vector ll splat_di_reg (ll x) { return vec_splats (x); } +vector ll splat_di_mem (ll *x) { return vec_splats (*x); } + +float extract_sf_0_reg (vector float p) { return vec_extract (p, 0); } +float extract_sf_3_reg (vector float p) { return vec_extract (p, 3); } +float extract_sf_n_reg (vector float p, int n) { return vec_extract (p, n); } + +float extract_sf_0_mem (vector float *p) { return vec_extract (*p, 0); } +float extract_sf_3_mem (vector float *p) { return vec_extract (*p, 3); } +float extract_sf_n_mem (vector float *p, int n) { return vec_extract (*p, n); } + +vector float insert_sf_0 (vector float p, float x) { return vec_insert (x, p, 0); } +vector float insert_sf_3 (vector float p, float x) { return vec_insert (x, p, 3); } +vector float insert_sf_n (vector float p, float x, int n) { return vec_insert (x, p, n); } + +vector float splat_sf_reg (float x) { return vec_splats (x); } +vector float splat_sf_mem (float *x) { return vec_splats (*x); } + +int extract_si_0_reg (vector int p) { return vec_extract (p, 0); } +int extract_si_3_reg (vector int p) { return vec_extract (p, 3); } +int extract_si_n_reg (vector int p, int n) { return vec_extract (p, n); } + +int extract_si_0_mem (vector int *p) { return vec_extract (*p, 0); } +int extract_si_3_mem (vector int *p) { return vec_extract (*p, 3); } +int extract_si_n_mem (vector int *p, int n) { return vec_extract (*p, n); } + +vector int insert_si_0 (vector int p, int x) { return vec_insert (x, p, 0); } +vector int insert_si_3 (vector int p, int x) { return vec_insert (x, p, 3); } +vector int insert_si_n (vector int p, int x, int n) { return vec_insert (x, p, n); } + +vector int splat_si_reg (int x) { return vec_splats (x); } +vector int splat_si_mem (int *x) { return vec_splats (*x); } + +unsigned int extract_usi_0_reg (vector unsigned int p) { return vec_extract (p, 0); } +unsigned int extract_usi_3_reg (vector unsigned int p) { return vec_extract (p, 3); } +unsigned int extract_usi_n_reg (vector unsigned int p, int n) { return vec_extract (p, n); } + +unsigned int extract_usi_0_mem (vector unsigned int *p) { return vec_extract (*p, 0); } +unsigned int extract_usi_3_mem (vector unsigned int *p) { return vec_extract (*p, 3); } +unsigned int extract_usi_n_mem (vector unsigned int *p, int n) { return vec_extract (*p, n); } + +vector unsigned int insert_usi_0 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 0); } +vector unsigned int insert_usi_3 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 3); } +vector unsigned int insert_usi_n (vector unsigned int p, unsigned int x, int n) { return vec_insert (x, p, n); } + +vector unsigned int splat_usi_reg (unsigned int x) { return vec_splats (x); } +vector unsigned int splat_usi_mem (unsigned int *x) { return vec_splats (*x); } + +short extract_hi_0_reg (vector short p) { return vec_extract (p, 0); } +short extract_hi_7_reg (vector short p) { return vec_extract (p, 7); } +short extract_hi_n_reg (vector short p, int n) { return vec_extract (p, n); } + +short extract_hi_0_mem (vector short *p) { return vec_extract (*p, 0); } +short extract_hi_7_mem (vector short *p) { return vec_extract (*p, 7); } +short extract_hi_n_mem (vector short *p, int n) { return vec_extract (*p, n); } + +vector short insert_hi_0 (vector short p, short x) { return vec_insert (x, p, 0); } +vector short insert_hi_7 (vector short p, short x) { return vec_insert (x, p, 7); } +vector short insert_hi_n (vector short p, short x, int n) { return vec_insert (x, p, n); } + +vector short splat_hi_reg (short x) { return vec_splats (x); } +vector short splat_hi_mem (short *x) { return vec_splats (*x); } + +unsigned short extract_uhi_0_reg (vector unsigned short p) { return vec_extract (p, 0); } +unsigned short extract_uhi_7_reg (vector unsigned short p) { return vec_extract (p, 7); } +unsigned short extract_uhi_n_reg (vector unsigned short p, int n) { return vec_extract (p, n); } + +unsigned short extract_uhi_0_mem (vector unsigned short *p) { return vec_extract (*p, 0); } +unsigned short extract_uhi_7_mem (vector unsigned short *p) { return vec_extract (*p, 7); } +unsigned short extract_uhi_n_mem (vector unsigned short *p, int n) { return vec_extract (*p, n); } + +vector unsigned short insert_uhi_0 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 0); } +vector unsigned short insert_uhi_7 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 7); } +vector unsigned short insert_uhi_n (vector unsigned short p, unsigned short x, int n) { return vec_insert (x, p, n); } + +vector unsigned short splat_uhi_reg (unsigned short x) { return vec_splats (x); } +vector unsigned short splat_uhi_mem (unsigned short *x) { return vec_splats (*x); } + +signed char extract_qi_0_reg (vector signed char p) { return vec_extract (p, 0); } +signed char extract_qi_1_reg5 (vector signed char p) { return vec_extract (p, 15); } +signed char extract_qi_n_reg (vector signed char p, int n) { return vec_extract (p, n); } + +signed char extract_qi_0_mem (vector signed char *p) { return vec_extract (*p, 0); } +signed char extract_qi_1_mem5 (vector signed char *p) { return vec_extract (*p, 15); } +signed char extract_qi_n_mem (vector signed char *p, int n) { return vec_extract (*p, n); } + +vector signed char insert_qi_0 (vector signed char p, signed char x) { return vec_insert (x, p, 0); } +vector signed char insert_qi_15 (vector signed char p, signed char x) { return vec_insert (x, p, 15); } +vector signed char insert_qi_n (vector signed char p, signed char x, int n) { return vec_insert (x, p, n); } + +vector signed char splat_qi_reg (signed char x) { return vec_splats (x); } +vector signed char splat_qi_mem (signed char *x) { return vec_splats (*x); } + +unsigned char extract_uqi_0_reg (vector unsigned char p) { return vec_extract (p, 0); } +unsigned char extract_uqi_1_reg5 (vector unsigned char p) { return vec_extract (p, 15); } +unsigned char extract_uqi_n_reg (vector unsigned char p, int n) { return vec_extract (p, n); } + +unsigned char extract_uqi_0_mem (vector unsigned char *p) { return vec_extract (*p, 0); } +unsigned char extract_uqi_1_mem5 (vector unsigned char *p) { return vec_extract (*p, 15); } +unsigned char extract_uqi_n_mem (vector unsigned char *p, int n) { return vec_extract (*p, n); } + +vector unsigned char insert_uqi_0 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 0); } +vector unsigned char insert_uqi_15 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 15); } +vector unsigned char insert_uqi_n (vector unsigned char p, unsigned char x, int n) { return vec_insert (x, p, n); } + +vector unsigned char splat_uqi_reg (unsigned char x) { return vec_splats (x); } +vector unsigned char splat_uqi_mem (unsigned char *x) { return vec_splats (*x); } diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c new file mode 100644 index 000000000..836b3851c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c @@ -0,0 +1,97 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mcpu=power7" } */ + +/* Test the various load/store varients. */ + +#include <altivec.h> + +#define TEST_COPY(NAME, TYPE) \ +void NAME ## _copy_native (vector TYPE *a, vector TYPE *b) \ +{ \ + *a = *b; \ +} \ + \ +void NAME ## _copy_vec (vector TYPE *a, vector TYPE *b) \ +{ \ + vector TYPE x = vec_ld (0, b); \ + vec_st (x, 0, a); \ +} \ + +#define TEST_COPYL(NAME, TYPE) \ +void NAME ## _lvxl (vector TYPE *a, vector TYPE *b) \ +{ \ + vector TYPE x = vec_ldl (0, b); \ + vec_stl (x, 0, a); \ +} \ + +#define TEST_VSX_COPY(NAME, TYPE) \ +void NAME ## _copy_vsx (vector TYPE *a, vector TYPE *b) \ +{ \ + vector TYPE x = vec_vsx_ld (0, b); \ + vec_vsx_st (x, 0, a); \ +} \ + +#define TEST_ALIGN(NAME, TYPE) \ +void NAME ## _align (vector unsigned char *a, TYPE *b) \ +{ \ + vector unsigned char x = vec_lvsl (0, b); \ + vector unsigned char y = vec_lvsr (0, b); \ + vec_st (x, 0, a); \ + vec_st (y, 8, a); \ +} + +#ifndef NO_COPY +TEST_COPY(uchar, unsigned char) +TEST_COPY(schar, signed char) +TEST_COPY(bchar, bool char) +TEST_COPY(ushort, unsigned short) +TEST_COPY(sshort, signed short) +TEST_COPY(bshort, bool short) +TEST_COPY(uint, unsigned int) +TEST_COPY(sint, signed int) +TEST_COPY(bint, bool int) +TEST_COPY(float, float) +TEST_COPY(double, double) +#endif /* NO_COPY */ + +#ifndef NO_COPYL +TEST_COPYL(uchar, unsigned char) +TEST_COPYL(schar, signed char) +TEST_COPYL(bchar, bool char) +TEST_COPYL(ushort, unsigned short) +TEST_COPYL(sshort, signed short) +TEST_COPYL(bshort, bool short) +TEST_COPYL(uint, unsigned int) +TEST_COPYL(sint, signed int) +TEST_COPYL(bint, bool int) +TEST_COPYL(float, float) +TEST_COPYL(double, double) +#endif /* NO_COPYL */ + +#ifndef NO_ALIGN +TEST_ALIGN(uchar, unsigned char) +TEST_ALIGN(schar, signed char) +TEST_ALIGN(ushort, unsigned short) +TEST_ALIGN(sshort, signed short) +TEST_ALIGN(uint, unsigned int) +TEST_ALIGN(sint, signed int) +TEST_ALIGN(float, float) +TEST_ALIGN(double, double) +#endif /* NO_ALIGN */ + + +#ifndef NO_VSX_COPY +TEST_VSX_COPY(uchar, unsigned char) +TEST_VSX_COPY(schar, signed char) +TEST_VSX_COPY(bchar, bool char) +TEST_VSX_COPY(ushort, unsigned short) +TEST_VSX_COPY(sshort, signed short) +TEST_VSX_COPY(bshort, bool short) +TEST_VSX_COPY(uint, unsigned int) +TEST_VSX_COPY(sint, signed int) +TEST_VSX_COPY(bint, bool int) +TEST_VSX_COPY(float, float) +TEST_VSX_COPY(double, double) +#endif /* NO_VSX_COPY */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c new file mode 100644 index 000000000..445dc1992 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c @@ -0,0 +1,554 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -mveclibabi=mass" } */ +/* { dg-final { scan-assembler "bl atan2d2" } } */ +/* { dg-final { scan-assembler "bl atan2f4" } } */ +/* { dg-final { scan-assembler "bl hypotd2" } } */ +/* { dg-final { scan-assembler "bl hypotf4" } } */ +/* { dg-final { scan-assembler "bl powd2" } } */ +/* { dg-final { scan-assembler "bl powf4" } } */ +/* { dg-final { scan-assembler "bl acosd2" } } */ +/* { dg-final { scan-assembler "bl acosf4" } } */ +/* { dg-final { scan-assembler "bl acoshd2" } } */ +/* { dg-final { scan-assembler "bl acoshf4" } } */ +/* { dg-final { scan-assembler "bl asind2" } } */ +/* { dg-final { scan-assembler "bl asinf4" } } */ +/* { dg-final { scan-assembler "bl asinhd2" } } */ +/* { dg-final { scan-assembler "bl asinhf4" } } */ +/* { dg-final { scan-assembler "bl atand2" } } */ +/* { dg-final { scan-assembler "bl atanf4" } } */ +/* { dg-final { scan-assembler "bl atanhd2" } } */ +/* { dg-final { scan-assembler "bl atanhf4" } } */ +/* { dg-final { scan-assembler "bl cbrtd2" } } */ +/* { dg-final { scan-assembler "bl cbrtf4" } } */ +/* { dg-final { scan-assembler "bl cosd2" } } */ +/* { dg-final { scan-assembler "bl cosf4" } } */ +/* { dg-final { scan-assembler "bl coshd2" } } */ +/* { dg-final { scan-assembler "bl coshf4" } } */ +/* { dg-final { scan-assembler "bl erfd2" } } */ +/* { dg-final { scan-assembler "bl erff4" } } */ +/* { dg-final { scan-assembler "bl erfcd2" } } */ +/* { dg-final { scan-assembler "bl erfcf4" } } */ +/* { dg-final { scan-assembler "bl exp2d2" } } */ +/* { dg-final { scan-assembler "bl exp2f4" } } */ +/* { dg-final { scan-assembler "bl expd2" } } */ +/* { dg-final { scan-assembler "bl expf4" } } */ +/* { dg-final { scan-assembler "bl expm1d2" } } */ +/* { dg-final { scan-assembler "bl expm1f4" } } */ +/* { dg-final { scan-assembler "bl lgamma" } } */ +/* { dg-final { scan-assembler "bl lgammaf" } } */ +/* { dg-final { scan-assembler "bl log10d2" } } */ +/* { dg-final { scan-assembler "bl log10f4" } } */ +/* { dg-final { scan-assembler "bl log1pd2" } } */ +/* { dg-final { scan-assembler "bl log1pf4" } } */ +/* { dg-final { scan-assembler "bl log2d2" } } */ +/* { dg-final { scan-assembler "bl log2f4" } } */ +/* { dg-final { scan-assembler "bl logd2" } } */ +/* { dg-final { scan-assembler "bl logf4" } } */ +/* { dg-final { scan-assembler "bl sind2" } } */ +/* { dg-final { scan-assembler "bl sinf4" } } */ +/* { dg-final { scan-assembler "bl sinhd2" } } */ +/* { dg-final { scan-assembler "bl sinhf4" } } */ +/* { dg-final { scan-assembler "bl tand2" } } */ +/* { dg-final { scan-assembler "bl tanf4" } } */ +/* { dg-final { scan-assembler "bl tanhd2" } } */ +/* { dg-final { scan-assembler "bl tanhf4" } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +double d1[SIZE] __attribute__((__aligned__(32))); +double d2[SIZE] __attribute__((__aligned__(32))); +double d3[SIZE] __attribute__((__aligned__(32))); + +float f1[SIZE] __attribute__((__aligned__(32))); +float f2[SIZE] __attribute__((__aligned__(32))); +float f3[SIZE] __attribute__((__aligned__(32))); + +void +test_double_atan2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_atan2 (d2[i], d3[i]); +} + +void +test_float_atan2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_atan2f (f2[i], f3[i]); +} + +void +test_double_hypot (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_hypot (d2[i], d3[i]); +} + +void +test_float_hypot (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_hypotf (f2[i], f3[i]); +} + +void +test_double_pow (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_pow (d2[i], d3[i]); +} + +void +test_float_pow (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_powf (f2[i], f3[i]); +} + +void +test_double_acos (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_acos (d2[i]); +} + +void +test_float_acos (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_acosf (f2[i]); +} + +void +test_double_acosh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_acosh (d2[i]); +} + +void +test_float_acosh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_acoshf (f2[i]); +} + +void +test_double_asin (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_asin (d2[i]); +} + +void +test_float_asin (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_asinf (f2[i]); +} + +void +test_double_asinh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_asinh (d2[i]); +} + +void +test_float_asinh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_asinhf (f2[i]); +} + +void +test_double_atan (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_atan (d2[i]); +} + +void +test_float_atan (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_atanf (f2[i]); +} + +void +test_double_atanh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_atanh (d2[i]); +} + +void +test_float_atanh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_atanhf (f2[i]); +} + +void +test_double_cbrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_cbrt (d2[i]); +} + +void +test_float_cbrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_cbrtf (f2[i]); +} + +void +test_double_cos (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_cos (d2[i]); +} + +void +test_float_cos (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_cosf (f2[i]); +} + +void +test_double_cosh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_cosh (d2[i]); +} + +void +test_float_cosh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_coshf (f2[i]); +} + +void +test_double_erf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_erf (d2[i]); +} + +void +test_float_erf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_erff (f2[i]); +} + +void +test_double_erfc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_erfc (d2[i]); +} + +void +test_float_erfc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_erfcf (f2[i]); +} + +void +test_double_exp2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_exp2 (d2[i]); +} + +void +test_float_exp2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_exp2f (f2[i]); +} + +void +test_double_exp (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_exp (d2[i]); +} + +void +test_float_exp (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_expf (f2[i]); +} + +void +test_double_expm1 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_expm1 (d2[i]); +} + +void +test_float_expm1 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_expm1f (f2[i]); +} + +void +test_double_lgamma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_lgamma (d2[i]); +} + +void +test_float_lgamma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_lgammaf (f2[i]); +} + +void +test_double_log10 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_log10 (d2[i]); +} + +void +test_float_log10 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_log10f (f2[i]); +} + +void +test_double_log1p (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_log1p (d2[i]); +} + +void +test_float_log1p (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_log1pf (f2[i]); +} + +void +test_double_log2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_log2 (d2[i]); +} + +void +test_float_log2 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_log2f (f2[i]); +} + +void +test_double_log (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_log (d2[i]); +} + +void +test_float_log (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_logf (f2[i]); +} + +void +test_double_sin (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_sin (d2[i]); +} + +void +test_float_sin (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_sinf (f2[i]); +} + +void +test_double_sinh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_sinh (d2[i]); +} + +void +test_float_sinh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_sinhf (f2[i]); +} + +void +test_double_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_sqrt (d2[i]); +} + +void +test_float_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_sqrtf (f2[i]); +} + +void +test_double_tan (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_tan (d2[i]); +} + +void +test_float_tan (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_tanf (f2[i]); +} + +void +test_double_tanh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + d1[i] = __builtin_tanh (d2[i]); +} + +void +test_float_tanh (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + f1[i] = __builtin_tanhf (f2[i]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c b/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c new file mode 100644 index 000000000..d05ee19d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xsmaxdp" } } */ +/* { dg-final { scan-assembler "xsmindp" } } */ + +float +do_fmin (float a, float b) +{ + return __builtin_fminf (a, b); +} + +float +do_fmax (float a, float b) +{ + return __builtin_fmaxf (a, b); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c new file mode 100644 index 000000000..5d23c0ae3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c @@ -0,0 +1,152 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xvadddp" } } */ +/* { dg-final { scan-assembler "xvsubdp" } } */ +/* { dg-final { scan-assembler "xvmuldp" } } */ +/* { dg-final { scan-assembler "xvdivdp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvsqrtdp" } } */ +/* { dg-final { scan-assembler "xvcpsgndp" } } */ +/* { dg-final { scan-assembler "xvrdpim" } } */ +/* { dg-final { scan-assembler "xvrdpip" } } */ +/* { dg-final { scan-assembler "xvrdpiz" } } */ +/* { dg-final { scan-assembler "xvrdpic" } } */ +/* { dg-final { scan-assembler "xvrdpi " } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +double a[SIZE] __attribute__((__aligned__(32))); +double b[SIZE] __attribute__((__aligned__(32))); +double c[SIZE] __attribute__((__aligned__(32))); +double d[SIZE] __attribute__((__aligned__(32))); +double e[SIZE] __attribute__((__aligned__(32))); + +void +vector_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +void +vector_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + +void +vector_multiply (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] * c[i]; +} + +void +vector_multiply_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) + d[i]; +} + +void +vector_multiply_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) - d[i]; +} + +void +vector_divide (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] / c[i]; +} + +extern double sqrt (double); +extern double floor (double); +extern double ceil (double); +extern double trunc (double); +extern double nearbyint (double); +extern double rint (double); +extern double copysign (double, double); + +void +vector_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = sqrt (b[i]); +} + +void +vector_floor (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = floor (b[i]); +} + +void +vector_ceil (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = ceil (b[i]); +} + +void +vector_trunc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = trunc (b[i]); +} + +void +vector_nearbyint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = nearbyint (b[i]); +} + +void +vector_rint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = rint (b[i]); +} + +void +vector_copysign (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = copysign (b[i], c[i]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c new file mode 100644 index 000000000..404e0403f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c @@ -0,0 +1,152 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvsqrtsp" } } */ +/* { dg-final { scan-assembler "xvcpsgnsp" } } */ +/* { dg-final { scan-assembler "xvrspim" } } */ +/* { dg-final { scan-assembler "xvrspip" } } */ +/* { dg-final { scan-assembler "xvrspiz" } } */ +/* { dg-final { scan-assembler "xvrspic" } } */ +/* { dg-final { scan-assembler "xvrspi " } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +float a[SIZE] __attribute__((__aligned__(32))); +float b[SIZE] __attribute__((__aligned__(32))); +float c[SIZE] __attribute__((__aligned__(32))); +float d[SIZE] __attribute__((__aligned__(32))); +float e[SIZE] __attribute__((__aligned__(32))); + +void +vector_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +void +vector_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + +void +vector_multiply (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] * c[i]; +} + +void +vector_multiply_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) + d[i]; +} + +void +vector_multiply_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) - d[i]; +} + +void +vector_divide (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] / c[i]; +} + +extern float sqrtf (float); +extern float floorf (float); +extern float ceilf (float); +extern float truncf (float); +extern float nearbyintf (float); +extern float rintf (float); +extern float copysignf (float, float); + +void +vector_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = sqrtf (b[i]); +} + +void +vector_floor (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = floorf (b[i]); +} + +void +vector_ceil (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = ceilf (b[i]); +} + +void +vector_trunc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = truncf (b[i]); +} + +void +vector_nearbyint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = nearbyintf (b[i]); +} + +void +vector_rint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = rintf (b[i]); +} + +void +vector_copysign (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = copysignf (b[i], c[i]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c new file mode 100644 index 000000000..25cf376f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvadddp" } } */ +/* { dg-final { scan-assembler "xvsubdp" } } */ +/* { dg-final { scan-assembler "xvmuldp" } } */ +/* { dg-final { scan-assembler "xvdivdp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ + +__vector double a, b, c, d; + +void +vector_add (void) +{ + a = b + c; +} + +void +vector_subtract (void) +{ + a = b - c; +} + +void +vector_multiply (void) +{ + a = b * c; +} + +void +vector_multiply_add (void) +{ + a = (b * c) + d; +} + +void +vector_multiply_subtract (void) +{ + a = (b * c) - d; +} + +void +vector_divide (void) +{ + a = b / c; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c new file mode 100644 index 000000000..f2a9c59df --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ + +__vector float a, b, c, d; + +void +vector_add (void) +{ + a = b + c; +} + +void +vector_subtract (void) +{ + a = b - c; +} + +void +vector_multiply (void) +{ + a = b * c; +} + +void +vector_multiply_add (void) +{ + a = (b * c) + d; +} + +void +vector_multiply_subtract (void) +{ + a = (b * c) - d; +} + +void +vector_divide (void) +{ + a = b / c; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c new file mode 100644 index 000000000..65843e93f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c @@ -0,0 +1,392 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +/* This will run, and someday we should add the support to test whether we are + running on VSX hardware. */ + +#include <altivec.h> +#include <stdlib.h> + +#ifdef DEBUG +#include <stdio.h> + +static int errors = 0; +#endif + +union args { + double scalar[2]; + vector double vect; +}; + +union largs { + unsigned long scalar[2]; + vector bool long vect; +}; + +static void +do_test (union args *expected, union args *got, const char *name) +{ + if (expected->scalar[0] != got->scalar[0] + || expected->scalar[1] != got->scalar[1]) + { +#ifdef DEBUG + printf ("%s failed!\n", name); + errors++; +#else + abort (); +#endif + } +} + +static void +do_ltest (union largs *expected, union largs *got, const char *name) +{ + if (expected->scalar[0] != got->scalar[0] + || expected->scalar[1] != got->scalar[1]) + { +#ifdef DEBUG + printf ("%s failed!\n", name); + errors++; +#else + abort (); +#endif + } +} + + +/* Vec functions taking a single argument. */ +static vector double +vabs (vector double arg) +{ + return vec_abs (arg); +} + +static vector double +vceil (vector double arg) +{ + return vec_ceil (arg); +} + +static vector double +vfloor (vector double arg) +{ + return vec_floor (arg); +} + +static vector double +vnearbyint (vector double arg) +{ + return vec_nearbyint (arg); +} + +static vector double +vrint (vector double arg) +{ + return vec_rint (arg); +} + +static vector double +vsqrt (vector double arg) +{ + return vec_sqrt (arg); +} + +/* Single argument tests. */ +static struct +{ + union args result; + union args input; + vector double (*func) (vector double); + const char *name; +} arg1_tests[] = { + /* result input function name */ + { { 1.0, 2.0 }, { -1.0, 2.0 }, vabs, "vabs" }, + { { 1.0, 2.0 }, { 1.0, -2.0 }, vabs, "vabs" }, + { { 2.0, 2.0 }, { 1.1, 1.7 }, vceil, "vceil" }, + { { -1.0, -1.0 }, { -1.1, -1.7 }, vceil, "vceil" }, + { { -1.0, 2.0 }, { -1.5, 1.5 }, vceil, "vceil" }, + { { 1.0, 1.0 }, { 1.1, 1.7 }, vfloor, "vfloor" }, + { { -2.0, -2.0 }, { -1.1, -1.7 }, vfloor, "vfloor" }, + { { -2.0, 1.0 }, { -1.5, 1.5 }, vfloor, "vfloor" }, + { { 1.0, 2.0 }, { 1.1, 1.7 }, vnearbyint, "vnearbyint" }, + { { -1.0, -2.0 }, { -1.1, -1.7 }, vnearbyint, "vnearbyint" }, + { { -2.0, 2.0 }, { -1.5, 1.5 }, vnearbyint, "vnearbyint" }, + { { 1.0, 2.0 }, { 1.1, 1.7 }, vrint, "vrint" }, + { { -1.0, -2.0 }, { -1.1, -1.7 }, vrint, "vrint" }, + { { -2.0, 2.0 }, { -1.5, 1.5 }, vrint, "vrint" }, + { { 2.0, 4.0 }, { 4.0, 16.0 }, vsqrt, "vsqrt" }, +}; + +static void +test_arg1 (void) +{ + unsigned i; + +#ifdef DEBUG + printf ("Single argument tests:\n"); +#endif + + for (i = 0; i < sizeof (arg1_tests) / sizeof (arg1_tests[0]); i++) + { + union args u; + u.vect = arg1_tests[i].func (arg1_tests[i].input.vect); + +#ifdef DEBUG + printf ("test %-16s: expected { %4g, %4g }, got { %4g, %4g }, input { %4g, %4g }\n", + arg1_tests[i].name, + arg1_tests[i].result.scalar[0], + arg1_tests[i].result.scalar[1], + u.scalar[0], + u.scalar[1], + arg1_tests[i].input.scalar[0], + arg1_tests[i].input.scalar[1]); +#endif + + do_test (&arg1_tests[i].result, &u, arg1_tests[i].name); + } + + return; +} + + +/* Vect functions taking 2 arguments. */ +static vector double +vadd (vector double arg1, vector double arg2) +{ + return vec_add (arg1, arg2); +} + +static vector double +vadd2 (vector double arg1, vector double arg2) +{ + return arg1 + arg2; +} + +static vector double +vsub (vector double arg1, vector double arg2) +{ + return vec_sub (arg1, arg2); +} + +static vector double +vsub2 (vector double arg1, vector double arg2) +{ + return arg1 - arg2; +} + +static vector double +vmul (vector double arg1, vector double arg2) +{ + return vec_mul (arg1, arg2); +} + +static vector double +vmul2 (vector double arg1, vector double arg2) +{ + return arg1 * arg2; +} + +static vector double +vdiv (vector double arg1, vector double arg2) +{ + return vec_div (arg1, arg2); +} + +static vector double +vdiv2 (vector double arg1, vector double arg2) +{ + return arg1 / arg2; +} + +static vector double +vmax (vector double arg1, vector double arg2) +{ + return vec_max (arg1, arg2); +} + +static vector double +vmin (vector double arg1, vector double arg2) +{ + return vec_min (arg1, arg2); +} + +/* 2 argument tests. */ +static struct +{ + union args result; + union args input[2]; + vector double (*func) (vector double, vector double); + const char *name; +} arg2_tests[] = { + /* result */ + { { 4.0, 6.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vadd, "vadd" }, + { { 4.0, -6.0 }, { { 1.0, -2.0 }, { 3.0, -4.0 } }, vadd, "vadd" }, + { { 4.0, 6.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vadd2, "vadd2" }, + { { 4.0, -6.0 }, { { 1.0, -2.0 }, { 3.0, -4.0 } }, vadd2, "vadd2" }, + { { -2.0, -2.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vsub, "vsub" }, + { { -2.0, 2.0 }, { { 1.0, -2.0 }, { 3.0, -4.0 } }, vsub, "vsub" }, + { { -2.0, -2.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vsub2, "vsub2" }, + { { -2.0, 2.0 }, { { 1.0, -2.0 }, { 3.0, -4.0 } }, vsub2, "vsub2" }, + { { 6.0, 4.0 }, { { 2.0, 8.0 }, { 3.0, 0.5 } }, vmul, "vmul" }, + { { 6.0, 4.0 }, { { 2.0, 8.0 }, { 3.0, 0.5 } }, vmul2, "vmul2" }, + { { 2.0, 0.5 }, { { 6.0, 4.0 }, { 3.0, 8.0 } }, vdiv, "vdiv" }, + { { 2.0, 0.5 }, { { 6.0, 4.0 }, { 3.0, 8.0 } }, vdiv2, "vdiv2" }, + { { 3.0, 4.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vmax, "vmax" }, + { { 1.0, 4.0 }, { { 1.0, -2.0 }, { -3.0, 4.0 } }, vmax, "vmax" }, + { { 1.0, 2.0 }, { { 1.0, 2.0 }, { 3.0, 4.0 } }, vmin, "vmin" }, + { { -3.0, -2.0 }, { { 1.0, -2.0 }, { -3.0, 4.0 } }, vmin, "vmin" }, +}; + +static void +test_arg2 (void) +{ + unsigned i; + +#ifdef DEBUG + printf ("\nTwo argument tests:\n"); +#endif + + for (i = 0; i < sizeof (arg2_tests) / sizeof (arg2_tests[0]); i++) + { + union args u; + u.vect = arg2_tests[i].func (arg2_tests[i].input[0].vect, + arg2_tests[i].input[1].vect); + +#ifdef DEBUG + printf ("test %-16s: expected { %4g, %4g }, got { %4g, %4g }, input { %4g, %4g }, { %4g, %4g }\n", + arg2_tests[i].name, + arg2_tests[i].result.scalar[0], + arg2_tests[i].result.scalar[1], + u.scalar[0], + u.scalar[1], + arg2_tests[i].input[0].scalar[0], + arg2_tests[i].input[0].scalar[1], + arg2_tests[i].input[1].scalar[0], + arg2_tests[i].input[1].scalar[1]); +#endif + + do_test (&arg2_tests[i].result, &u, arg2_tests[i].name); + } + + return; +} + + +/* Comparisons, returnning a boolean vector. */ +static vector bool long +vcmpeq (vector double arg1, vector double arg2) +{ + return vec_cmpeq (arg1, arg2); +} + +static vector bool long +vcmplt (vector double arg1, vector double arg2) +{ + return vec_cmplt (arg1, arg2); +} + +static vector bool long +vcmple (vector double arg1, vector double arg2) +{ + return vec_cmple (arg1, arg2); +} + +static vector bool long +vcmpgt (vector double arg1, vector double arg2) +{ + return vec_cmpgt (arg1, arg2); +} + +static vector bool long +vcmpge (vector double arg1, vector double arg2) +{ + return vec_cmpge (arg1, arg2); +} + +#define ONE 0xffffffffffffffffUL +#define ZERO 0x0000000000000000UL + +/* comparison tests. */ +static struct +{ + union largs result; + union args input[2]; + vector bool long (*func) (vector double, vector double); + const char *name; +} argcmp_tests[] = { + { { ONE, ZERO }, { { 1.0, 2.0 }, { 1.0, -2.0 } }, vcmpeq, "vcmpeq" }, + { { ZERO, ONE }, { { -1.0, 2.0 }, { 1.0, 2.0 } }, vcmpeq, "vcmpeq" }, + + { { ONE, ONE }, { { 1.0, -2.0 }, { 1.0, -2.0 } }, vcmple, "vcmple" }, + { { ONE, ONE }, { { 1.0, -2.0 }, { 2.0, -1.0 } }, vcmple, "vcmple" }, + { { ZERO, ZERO }, { { 2.0, -1.0 }, { 1.0, -2.0 } }, vcmple, "vcmple" }, + + { { ZERO, ZERO }, { { 1.0, -2.0 }, { 1.0, -2.0 } }, vcmplt, "vcmplt" }, + { { ONE, ONE }, { { 1.0, -2.0 }, { 2.0, -1.0 } }, vcmplt, "vcmplt" }, + { { ZERO, ZERO }, { { 2.0, -1.0 }, { 1.0, -2.0 } }, vcmplt, "vcmplt" }, + + { { ZERO, ZERO }, { { 1.0, -2.0 }, { 1.0, -2.0 } }, vcmpgt, "vcmpgt" }, + { { ZERO, ZERO }, { { 1.0, -2.0 }, { 2.0, -1.0 } }, vcmpgt, "vcmpgt" }, + { { ONE, ONE }, { { 2.0, -1.0 }, { 1.0, -2.0 } }, vcmpgt, "vcmpgt" }, + + { { ONE, ONE }, { { 1.0, -2.0 }, { 1.0, -2.0 } }, vcmpge, "vcmpge" }, + { { ZERO, ZERO }, { { 1.0, -2.0 }, { 2.0, -1.0 } }, vcmpge, "vcmpge" }, + { { ONE, ONE }, { { 2.0, -1.0 }, { 1.0, -2.0 } }, vcmpge, "vcmpge" }, +}; + +static void +test_argcmp (void) +{ + unsigned i; + +#ifdef DEBUG + printf ("\nComparison tests:\n"); +#endif + + for (i = 0; i < sizeof (argcmp_tests) / sizeof (argcmp_tests[0]); i++) + { + union largs u; + u.vect = argcmp_tests[i].func (argcmp_tests[i].input[0].vect, + argcmp_tests[i].input[1].vect); + +#ifdef DEBUG + printf ("test %-16s: expected { 0x%016lx, 0x%016lx }, got { 0x%016lx, 0x%016lx }, input { %4g, %4g }, { %4g, %4g }\n", + argcmp_tests[i].name, + argcmp_tests[i].result.scalar[0], + argcmp_tests[i].result.scalar[1], + u.scalar[0], + u.scalar[1], + argcmp_tests[i].input[0].scalar[0], + argcmp_tests[i].input[0].scalar[1], + argcmp_tests[i].input[1].scalar[0], + argcmp_tests[i].input[1].scalar[1]); +#endif + + do_ltest (&argcmp_tests[i].result, &u, argcmp_tests[i].name); + } + + return; +} + + +int +main (int argc, char *argv[]) +{ + test_arg1 (); + test_arg2 (); + test_argcmp (); + +#ifdef DEBUG + if (errors) + { + printf ("There were %d error(s)\n", errors); + return errors; + } + else + printf ("There were no errors\n"); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c new file mode 100644 index 000000000..f8e644bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c @@ -0,0 +1,81 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> + +void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, vector unsigned char *p_uc, int *i) +{ + vector double in0 = in[0]; + vector double in1 = in[1]; + vector double in2 = in[2]; + vector long inl = *p_l; + vector bool long inb = *p_b; + vector unsigned char uc = *p_uc; + + *out++ = vec_abs (in0); + *out++ = vec_add (in0, in1); + *out++ = vec_and (in0, in1); + *out++ = vec_and (in0, inb); + *out++ = vec_and (inb, in0); + *out++ = vec_andc (in0, in1); + *out++ = vec_andc (in0, inb); + *out++ = vec_andc (inb, in0); + *out++ = vec_ceil (in0); + *p_b++ = vec_cmpeq (in0, in1); + *p_b++ = vec_cmpgt (in0, in1); + *p_b++ = vec_cmpge (in0, in1); + *p_b++ = vec_cmplt (in0, in1); + *p_b++ = vec_cmple (in0, in1); + *out++ = vec_div (in0, in1); + *out++ = vec_floor (in0); + *out++ = vec_madd (in0, in1, in2); + *out++ = vec_msub (in0, in1, in2); + *out++ = vec_max (in0, in1); + *out++ = vec_min (in0, in1); + *out++ = vec_msub (in0, in1, in2); + *out++ = vec_mul (in0, in1); + *out++ = vec_nearbyint (in0); + *out++ = vec_nmadd (in0, in1, in2); + *out++ = vec_nmsub (in0, in1, in2); + *out++ = vec_nor (in0, in1); + *out++ = vec_or (in0, in1); + *out++ = vec_or (in0, inb); + *out++ = vec_or (inb, in0); + *out++ = vec_perm (in0, in1, uc); + *out++ = vec_rint (in0); + *out++ = vec_sel (in0, in1, inl); + *out++ = vec_sel (in0, in1, inb); + *out++ = vec_sub (in0, in1); + *out++ = vec_sqrt (in0); + *out++ = vec_trunc (in0); + *out++ = vec_xor (in0, in1); + *out++ = vec_xor (in0, inb); + *out++ = vec_xor (inb, in0); + + *i++ = vec_all_eq (in0, in1); + *i++ = vec_all_ge (in0, in1); + *i++ = vec_all_gt (in0, in1); + *i++ = vec_all_le (in0, in1); + *i++ = vec_all_lt (in0, in1); + *i++ = vec_all_nan (in0); + *i++ = vec_all_ne (in0, in1); + *i++ = vec_all_nge (in0, in1); + *i++ = vec_all_ngt (in0, in1); + *i++ = vec_all_nle (in0, in1); + *i++ = vec_all_nlt (in0, in1); + *i++ = vec_all_numeric (in0); + *i++ = vec_any_eq (in0, in1); + *i++ = vec_any_ge (in0, in1); + *i++ = vec_any_gt (in0, in1); + *i++ = vec_any_le (in0, in1); + *i++ = vec_any_lt (in0, in1); + *i++ = vec_any_nan (in0); + *i++ = vec_any_ne (in0, in1); + *i++ = vec_any_nge (in0, in1); + *i++ = vec_any_ngt (in0, in1); + *i++ = vec_any_nle (in0, in1); + *i++ = vec_any_nlt (in0, in1); + *i++ = vec_any_numeric (in0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c new file mode 100644 index 000000000..2538ad987 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c @@ -0,0 +1,54 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-align-1.c. */ +#include <stdlib.h> +#include <stdarg.h> + +/* Compile time known misalignment. Cannot use loop peeling to align + the store. */ + +#define N 16 + +struct foo { + char x; + int y[N]; +} __attribute__((packed)); + +int x[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + +__attribute__ ((noinline)) int +main1 (struct foo * __restrict__ p) +{ + int i; + + for (i = 0; i < N; i++) + { + p->y[i] = x[i]; + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (p->y[i] != x[i]) + abort (); + } + return 0; +} + + +int main (void) +{ + int i; + struct foo *p = malloc (2*sizeof (struct foo)); + + main1 (p); + return 0; +} + +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c new file mode 100644 index 000000000..7bb7db0fa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (float *pd, float *pa, float *pb, float *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, float * __restrict__ pd, float * __restrict__ pa, float * __restrict__ pb, float * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + float a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + float d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c new file mode 100644 index 000000000..b99bcca49 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (short *pa, short *pb, short *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, short * __restrict__ pa, short * __restrict__ pb, short * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + } + + bar (pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + short a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + short b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + short c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,a,b,c); + main1 (N-2,a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c new file mode 100644 index 000000000..ad6f8f0fe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (double *pa, double *pb, double *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + } + + bar (pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,a,b,c); + main1 (N-2,a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 3 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c new file mode 100644 index 000000000..32d05b298 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (char *pa, char *pb, char *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] + pc[i])) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, char * __restrict__ pa, char * __restrict__ pb, char * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] + pc[i]; + } + + bar (pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + char a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + char b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + char c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,a,b,c); + main1 (N-2,a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c new file mode 100644 index 000000000..8e6e288b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (double *pd, double *pa, double *pb, double *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, double * __restrict__ pd, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c new file mode 100644 index 000000000..c09583535 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (int *pd, int *pa, int *pb, int *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, int * __restrict__ pd, int * __restrict__ pa, int * __restrict__ pb, int * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + int a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + int d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + int b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + int c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c new file mode 100644 index 000000000..af671ee79 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include <stdlib.h> +#include <stdarg.h> + +#define N 256 + +__attribute__ ((noinline)) +void bar (short *pd, short *pa, short *pb, short *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, short * __restrict__ pd, short * __restrict__ pa, short * __restrict__ pb, short * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + short a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + short d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + short b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + short c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-1.c b/gcc/testsuite/gcc.target/powerpc/warn-1.c new file mode 100644 index 000000000..c00aff08c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/warn-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O -mvsx -mno-altivec" } */ + +/* { dg-warning "-mvsx and -mno-altivec are incompatible" "" { target *-*-* } 1 } */ + +double +foo (double *x, double *y) +{ + double z[2]; + int i; + + for (i = 0; i < 2; i++) + z[i] = x[i] + y[i]; + return z[0] * z[1]; +} + +/* { dg-final { scan-assembler-not "xsadddp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-2.c b/gcc/testsuite/gcc.target/powerpc/warn-2.c new file mode 100644 index 000000000..0a9fa1e3f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/warn-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O -mcpu=power7 -mno-altivec" } */ + +/* { dg-warning "-mno-altivec disables vsx" "" { target *-*-* } 1 } */ + +double +foo (double *x, double *y) +{ + double z[2]; + int i; + + for (i = 0; i < 2; i++) + z[i] = x[i] + y[i]; + return z[0] * z[1]; +} + +/* { dg-final { scan-assembler-not "xsadddp" } } */ |